Besser; Paul R.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Besser; Paul R..The latest application filed is for "methods of forming gate structures for transistor devices for cmos applications and the resulting products".

Company Profile

0.131.66

Besser; Paul R. - Sunnyvale CA
Besser; Paul R. - Suunyvale CA
Besser; Paul R. - Austin TX
Besser; Paul R. - Cupertino CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Gate structures for transistor devices for CMOS applications and products Grant 9,362,283 - Hong , et al. June 7, 2	2016-06-07
Multi-layer barrier layer for interconnect structure Grant 9,269,615 - Ryan , et al. February 23, 2	2016-02-23
Method for manufacturing a contact for a semiconductor component and related structure Grant 9,202,758 - Besser , et al. December 1, 2	2015-12-01
Methods Of Forming Gate Structures For Transistor Devices For Cmos Applications And The Resulting Products App 20150311206 - Hong; Zhendong ; et al.	2015-10-29
Integrated circuits and methods for fabricating integrated circuits with silicide contacts on non-planar structures Grant 9,142,633 - Besser , et al. September 22, 2	2015-09-22
Methods of forming gate structures for transistor devices for CMOS applications Grant 9,105,497 - Hong , et al. August 11, 2	2015-08-11
Multi-layer barrier layer stacks for interconnect structures Grant 9,076,792 - Ryan , et al. July 7, 2	2015-07-07
Methods Of Forming Gate Structures For Transistor Devices For Cmos Applications And The Resulting Products App 20150061027 - Hong; Zhendong ; et al.	2015-03-05
Multi-layer Barrier Layer Stacks For Interconnect Structures App 20140264876 - Ryan; Vivian W. ; et al.	2014-09-18
Microwave-assisted Heating Of Strong Acid Solution To Remove Nickel Platinum/platinum Residues App 20140248770 - FITZ; Clemens ; et al.	2014-09-04
Multi-layer Barrier Layer For Interconnect Structure App 20140217591 - Ryan; Vivian W. ; et al.	2014-08-07
Methods for fabricating integrated circuits having low resistance metal gate structures Grant 8,778,789 - Besser , et al. July 15, 2	2014-07-15
Multi-layer barrier layer stacks for interconnect structures Grant 8,772,158 - Ryan , et al. July 8, 2	2014-07-08
Integrated Circuits And Methods For Fabricating Integrated Circuits With Silicide Contacts On Non-planar Structures App 20140167264 - Besser; Paul R. ; et al.	2014-06-19
Methods For Fabricating Integrated Circuits Having Low Resistance Metal Gate Structures App 20140154877 - Besser; Paul R. ; et al.	2014-06-05
Multi-layer barrier layer for interconnect structure Grant 8,728,931 - Ryan , et al. May 20, 2	2014-05-20
Method for forming contact in an integrated circuit Grant 8,709,941 - Besser April 29, 2	2014-04-29
Methods for fabricating integrated circuits having low resistance device contacts Grant 8,691,689 - Besser , et al. April 8, 2	2014-04-08
Multi-layer Barrier Layer For Interconnect Structure App 20140021613 - Ryan; Vivian W. ; et al.	2014-01-23
Multi-layer Barrier Layer Stacks For Interconnect Structures App 20140021615 - Ryan; Vivian W. ; et al.	2014-01-23
Multi-layer Barrier Layer For Interconnect Structure App 20140024212 - Ryan; Vivian W. ; et al.	2014-01-23
Subtractive metal multi-layer barrier layer for interconnect structure Grant 8,623,758 - Ryan , et al. January 7, 2	2014-01-07
Method for Forming Contact in an Integrated Circuit App 20130072014 - Besser; Paul R.	2013-03-21
Silicidation Of Device Contacts Using Pre-amorphization Implant Of Semiconductor Substrate App 20130049200 - Besser; Paul R. ; et al.	2013-02-28
Silicidation Of Device Contacts Using Pre-amorphization Implant Of Semiconductor Substrate App 20130049199 - Besser; Paul R. ; et al.	2013-02-28
Method to reduce mol damage on NiSi Grant 8,330,235 - Ramani , et al. December 11, 2	2012-12-11
Integrated circuit system with contact integration Grant 8,283,786 - Besser October 9, 2	2012-10-09
Integrated circuit eliminating source/drain junction spiking Grant 8,102,009 - Chan , et al. January 24, 2	2012-01-24
METHOD TO REDUCE MOL DAMAGE ON NiSi App 20110198670 - Ramani; Karthik ; et al.	2011-08-18
Method to reduce MOL damage on NiSi Grant 7,994,038 - Ramani , et al. August 9, 2	2011-08-09
Semiconductor device and method of manufacturing a semiconductor device Grant 7,910,996 - Besser , et al. March 22, 2	2011-03-22
Multi-silicide system in integrated circuit technology Grant 7,843,015 - Chiu , et al. November 30, 2	2010-11-30
METHOD TO REDUCE MOL DAMAGE ON NiSi App 20100193876 - Ramani; Karthik ; et al.	2010-08-05
Methods for fabricating low contact resistance CMOS circuits Grant 7,754,554 - Peidous , et al. July 13, 2	2010-07-13
Silicide interconnect structure Grant 7,749,898 - Besser , et al. July 6, 2	2010-07-06
Resist trim process to define small openings in dielectric layers Grant 7,737,021 - Dakshina-Murthy , et al. June 15, 2	2010-06-15
Low contact resistance CMOS circuits and methods for their fabrication Grant 7,719,035 - Besser May 18, 2	2010-05-18
Method of forming isolation regions for integrated circuits Grant 7,713,834 - Wang , et al. May 11, 2	2010-05-11
Tensile strained substrate Grant 7,701,019 - Ngo , et al. April 20, 2	2010-04-20
Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect Grant 7,696,092 - Lopatin , et al. April 13, 2	2010-04-13
Contact liner in integrated circuit technology Grant 7,670,915 - Ryan , et al. March 2, 2	2010-03-02
Shallow trench isolation process Grant 7,648,886 - Ngo , et al. January 19, 2	2010-01-19
Silicide Interconnect Structure App 20090315182 - Besser; Paul R. ; et al.	2009-12-24
Semiconductor Devices Having Rare Earth Metal Silicide Contact Layers And Methods For Fabricating The Same App 20090294871 - BESSER; Paul R.	2009-12-03
Low Contact Resistance Semiconductor Devices And Methods For Fabricating The Same App 20090289370 - BESSER; Paul R. ; et al.	2009-11-26
Semiconductor Device And Method Of Manufacturing A Semiconductor Device App 20090267152 - Besser; Paul R. ; et al.	2009-10-29
Semiconductor device and method of manufacturing a semiconductor device Grant 7,572,705 - Besser , et al. August 11, 2	2009-08-11
Integrated Circuit System With Contact Integration App 20090159985 - Besser; Paul R.	2009-06-25
MOS TRANSISTORS HAVING NiPtSi CONTACT LAYERS AND METHODS FOR FABRICATING THE SAME App 20090127594 - ARUNACHALAM; Valli ; et al.	2009-05-21
Method Of Forming Isolation Regions For Integrated Circuits App 20090047770 - Wang; Haihong ; et al.	2009-02-19
Semiconductor Device App 20090032888 - En; William G. ; et al.	2009-02-05
Method of forming a semiconductor device Grant 7,456,062 - En , et al. November 25, 2	2008-11-25
Low Contact Resistance Cmos Circuits And Methods For Their Fabrication App 20080251855 - BESSER; Paul R.	2008-10-16
Method of forming isolation regions for integrated circuits Grant 7,422,961 - Wang , et al. September 9, 2	2008-09-09
Semiconductor component having a contact structure and method of manufacture Grant 7,407,882 - Wang , et al. August 5, 2	2008-08-05
Method Of Forming Vias In A Semiconductor Device App 20080182407 - Zhai; Jun ; et al.	2008-07-31
Methods For Fabricating Low Contact Resistance Cmos Circuits App 20080182370 - Peidous; Igor ; et al.	2008-07-31
Low contact resistance CMOS circuits and methods for their fabrication Grant 7,405,112 - Besser July 29, 2	2008-07-29
Method and apparatus for controlling the thickness of a selective epitaxial growth layer Grant 7,402,207 - Besser , et al. July 22, 2	2008-07-22
Memory System With Poly Metal Gate App 20080149990 - Wang; Connie Pin Chin ; et al.	2008-06-26
Integrated Circuit System With Memory System App 20080150011 - Chan; Simon Siu-Sing ; et al.	2008-06-26
Integrated Circuit System With Memory System App 20080153224 - Wang; Connie Pin Chin ; et al.	2008-06-26
Fully depleted strained semiconductor on insulator transistor and method of making the same Grant 7,312,125 - Xiang , et al. December 25, 2	2007-12-25
Ultra-uniform silicide system in integrated circuit technology Grant 7,307,322 - Chiu , et al. December 11, 2	2007-12-11
Method for manufacturing a semiconductor component that inhibits formation of wormholes Grant 7,217,660 - Wang , et al. May 15, 2	2007-05-15
Method And Apparatus For Detecting The Endpoint Of A Chemical-Mechanical Polishing Operation App 20070105247 - Mauersberger; Frank ; et al.	2007-05-10
Integrated Circuit Eliminating Source/drain Junction Spiking App 20070085149 - Chan; Simon Siu-Sing ; et al.	2007-04-19
Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition Grant 7,169,706 - Lopatin , et al. January 30, 2	2007-01-30
Conversion of transition metal to silicide through back end processing in integrated circuit technology Grant 7,151,020 - Patton , et al. December 19, 2	2006-12-19
Method of forming a semiconductor device having an epitaxial layer and device thereof App 20060281271 - Brown; David E. ; et al.	2006-12-14
Multi-silicide system in integrated circuit technology App 20060267087 - Chiu; Robert J. ; et al.	2006-11-30
Ultra-uniform silicide system in integrated circuit technology App 20060267107 - Chiu; Robert J. ; et al.	2006-11-30
Method of eliminating source/drain junction spiking, and device produced thereby Grant 7,132,352 - Chan , et al. November 7, 2	2006-11-07
Low Contact Resistance Cmos Circuits And Methods For Their Fabrication App 20060220141 - Besser; Paul R.	2006-10-05
Tensile strained substrate App 20060138479 - Ngo; Minh V. ; et al.	2006-06-29
Semiconductor device with metal gate and high-k tantalum oxide or tantalum oxynitride gate dielectric Grant 7,060,571 - Ngo , et al. June 13, 2	2006-06-13
Low power pre-silicide process in integrated circuit technology Grant 7,049,666 - Chiu , et al. May 23, 2	2006-05-23
Engineered metal gate electrode Grant 7,033,888 - Pan , et al. April 25, 2	2006-04-25
Ultra-uniform silicides in integrated circuit technology Grant 7,005,376 - Chiu , et al. February 28, 2	2006-02-28
Low stress sidewall spacer in integrated circuit technology Grant 7,005,357 - Ngo , et al. February 28, 2	2006-02-28
Semiconductor with tensile strained substrate and method of making the same Grant 7,001,837 - Ngo , et al. February 21, 2	2006-02-21
Implanted barrier layer to improve line reliability and method of forming same Grant 6,992,004 - Besser , et al. January 31, 2	2006-01-31
Method of self-annealing conductive lines that separates grain size effects from alloy mobility Grant 6,979,642 - Buynoski , et al. December 27, 2	2005-12-27
Multi-silicide in integrated circuit technology Grant 6,969,678 - Chiu , et al. November 29, 2	2005-11-29
Method of decontaminating equipment Grant 6,951,220 - Arasnia , et al. October 4, 2	2005-10-04
Method, system and apparatus to detect defects in semiconductor devices Grant 6,943,569 - Pressley , et al. September 13, 2	2005-09-13
Low stress sidewall spacer in integrated circuit technology App 20050153496 - Ngo, Minh Van ; et al.	2005-07-14
One step deposition method for high-k dielectric and metal gate electrode Grant 6,893,910 - Woo , et al. May 17, 2	2005-05-17
Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition App 20050085073 - Lopatin, Sergey D. ; et al.	2005-04-21
Selective epitaxy to improve silicidation Grant 6,878,592 - Besser , et al. April 12, 2	2005-04-12
Strained silicon NMOS having silicon source/drain extensions and method for its fabrication Grant 6,867,428 - Besser , et al. March 15, 2	2005-03-15
Siliciding spacer in integrated circuit technology App 20050048731 - Patton, Jeffrey P. ; et al.	2005-03-03
Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode Grant 6,861,350 - Ngo , et al. March 1, 2	2005-03-01
Method of forming an adhesion layer with an element reactive with a barrier layer Grant 6,861,349 - Lopatin , et al. March 1, 2	2005-03-01
Depletion to avoid cross contamination Grant 6,858,503 - Ngo , et al. February 22, 2	2005-02-22
Ultra-uniform silicides in integrated circuit technology App 20050006705 - Chiu, Robert J. ; et al.	2005-01-13
Method of implanting copper barrier material to improve electrical performance Grant 6,835,655 - Besser , et al. December 28, 2	2004-12-28
Method of forming ultra-shallow junctions in a semiconductor wafer with a deposited silicon layer and in-situ anneal to reduce silicon consumption during salicidation Grant 6,835,656 - Besser , et al. December 28, 2	2004-12-28
Method of forming an electroless nucleation layer on a via bottom Grant 6,815,340 - Lopatin , et al. November 9, 2	2004-11-09
Pre-cleaning for silicidation in an SMOS process Grant 6,811,448 - Paton , et al. November 2, 2	2004-11-02
Method and apparatus for detecting the endpoint of a chemical-mechanical polishing operation using optical techniques Grant 6,809,032 - Mauersberger , et al. October 26, 2	2004-10-26
Nickel alloy for SMOS process silicidation Grant 6,797,614 - Paton , et al. September 28, 2	2004-09-28
Shallow trench isolation for strained silicon processes App 20040180509 - Wang, Haihong ; et al.	2004-09-16
Engineered metal gate electrode App 20040175910 - Pan, James N. ; et al.	2004-09-09
Mosfets incorporating nickel germanosilicided gate and methods for their formation Grant 6,787,864 - Paton , et al. September 7, 2	2004-09-07
Silicide process using high K-dielectrics Grant 6,784,506 - Xiang , et al. August 31, 2	2004-08-31
Semiconductor with tensile strained substrate and method of making the same App 20040142545 - Ngo, Minh V. ; et al.	2004-07-22
Passivation of nitride spacer Grant 6,764,912 - Foster , et al. July 20, 2	2004-07-20
Shallow trench isolation for strained silicon processes App 20040137742 - Ngo, Minh-Van ; et al.	2004-07-15
Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer Grant 6,730,576 - Wang , et al. May 4, 2	2004-05-04
Engineered metal gate electrode Grant 6,727,560 - Pan , et al. April 27, 2	2004-04-27
Laminated conductive lines and methods of forming the same Grant 6,724,087 - Buynoski , et al. April 20, 2	2004-04-20
Method of reducing voiding in copper interconnects with copper alloys in the seed layer App 20040061237 - Zhao, Larry ; et al.	2004-04-01
Mosfets incorporating nickel germanosilicided gate and methods for their formation App 20040061191 - Paton, Eric N. ; et al.	2004-04-01
Method of implantation after copper seed deposition Grant 6,703,307 - Lopatin , et al. March 9, 2	2004-03-09
Method of inserting alloy elements to reduce copper diffusion and bulk diffusion Grant 6,703,308 - Besser , et al. March 9, 2	2004-03-09
Selective deposition process for allowing damascene-type Cu interconnect lines Grant 6,689,689 - Besser , et al. February 10, 2	2004-02-10
Method Of Implantation After Copper Seed Deposition App 20040023486 - Lopatin, Sergey D. ; et al.	2004-02-05
Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect App 20040005773 - Lopatin, Sergey D. ; et al.	2004-01-08
Metal gate stack with etch stop layer Grant 6,664,604 - Besser , et al. December 16, 2	2003-12-16
Nitrogen-plasma treatment for reduced nickel silicide bridging Grant 6,661,067 - Ngo , et al. December 9, 2	2003-12-09
Reverse mask and oxide layer deposition for reduction of vertical capacitance variation in multi-layer metallization systems Grant 6,660,618 - Chen , et al. December 9, 2	2003-12-09
Method of forming ultra-shallow junctions in a semiconductor wafer with silicon layer deposited from a gas precursor to reduce silicon consumption during salicidation Grant 6,660,621 - Besser , et al. December 9, 2	2003-12-09
Metal gate stack with etch stop layer having implanted metal species Grant 6,657,268 - Besser , et al. December 2, 2	2003-12-02
Method of selectively alloying interconnect regions by deposition process Grant 6,656,834 - Besser , et al. December 2, 2	2003-12-02
Method of performing a two stage anneal in the formation of an alloy interconnect Grant 6,656,836 - Wang , et al. December 2, 2	2003-12-02
Method Of Selectively Alloying Interconnect Regions By Deposition Process App 20030216029 - Besser, Paul R. ; et al.	2003-11-20
Metal gate with PVD amorphous silicon layer and barrier layer for CMOS devices and method of making with a replacement gate process Grant 6,642,590 - Besser , et al. November 4, 2	2003-11-04
Method of selectively alloying interconnect regions by ion implantation Grant 6,633,085 - Besser , et al. October 14, 2	2003-10-14
Method of controlling barrier metal polishing processes based upon X-ray fluorescence measurements Grant 6,629,879 - Kim , et al. October 7, 2	2003-10-07
Method Of Determining Barrier Layer Effectiveness For Preventing Metallization Diffusion By Forming A Test Specimen Device And Using A Metal Penetration Measurement Technique For Fabricating A Production Semiconductor Device And A Test Specimen Device Thereby Formed Grant 6,617,176 - Sanchez, Jr. , et al. September 9, 2	2003-09-09
Transistor having a gate stick comprised of a metal, and a method of making same Grant 6,614,064 - Besser , et al. September 2, 2	2003-09-02
Automated control of metal thickness during film deposition Grant 6,611,576 - Besser , et al. August 26, 2	2003-08-26
Locally increasing sidewall density by ion implantation Grant 6,610,594 - Apelgren , et al. August 26, 2	2003-08-26
Method of controlling the formation of metal layers Grant 6,610,181 - Besser , et al. August 26, 2	2003-08-26
Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing Grant 6,605,513 - Paton , et al. August 12, 2	2003-08-12
Nitrogen implant into nitride spacer to reduce nickel silicide formation on spacer Grant 6,602,754 - Kluth , et al. August 5, 2	2003-08-05
Metal silicide gate transistors Grant 6,602,781 - Xiang , et al. August 5, 2	2003-08-05
Metal gate with PVD amorphous silicon layer having implanted dopants for CMOS devices and method of making with a replacement gate process Grant 6,589,866 - Besser , et al. July 8, 2	2003-07-08
Process for forming fully silicided gates Grant 6,562,718 - Xiang , et al. May 13, 2	2003-05-13
Electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors Grant 6,559,051 - Buynoski , et al. May 6, 2	2003-05-06
Method for forming openings for conductive interconnects Grant 6,555,479 - Hause , et al. April 29, 2	2003-04-29
Improved Silicide Process Using High K-dielectrics App 20030042515 - Xiang, Qi ; et al.	2003-03-06
Silicide stop layer in a damascene semiconductor structure App 20030034533 - Paton, Eric N. ; et al.	2003-02-20
Method of forming semiconductor devices with differently composed metal-based gate electrodes Grant 6,518,154 - Buynoski , et al. February 11, 2	2003-02-11
Method of forming a metal or metal nitride interface layer between silicon nitride and copper Grant 6,518,167 - You , et al. February 11, 2	2003-02-11
Test structure for providing depth of polish feedback Grant 6,514,858 - Hause , et al. February 4, 2	2003-02-04
Locally increasing sidewall density by ion implantation App 20030013296 - Apelgren, Eric M. ; et al.	2003-01-16
Metal gate stack with etch stop layer having implanted metal species App 20030003645 - Besser, Paul R. ; et al.	2003-01-02
Resist trim process to define small openings in dielectric layers Grant 6,500,755 - Dakshina-Murthy , et al. December 31, 2	2002-12-31
Method for forming copper interconnects Grant 6,489,240 - Iacoponi , et al. December 3, 2	2002-12-03
Damascene NiSi metal gate high-k transistor Grant 6,475,874 - Xiang , et al. November 5, 2	2002-11-05
Silicide gate transistors Grant 6,465,309 - Xiang , et al. October 15, 2	2002-10-15
Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors Grant 6,465,334 - Buynoski , et al. October 15, 2	2002-10-15
Non-arsenic N-type dopant implantation for improved source/drain interfaces with nickel silicides App 20020146904 - Buynoski, Matthew S. ; et al.	2002-10-10
Selective deposition process for passivating top interface of damascene-type Cu interconnect lines Grant 6,455,425 - Besser , et al. September 24, 2	2002-09-24
Metal Gate Stack With Etch Stop Layer Having Implanted Metal Species App 20020132415 - Besser, Paul R. ; et al.	2002-09-19
Metal gate stack with etch stop layer having implanted metal species Grant 6,444,513 - Besser , et al. September 3, 2	2002-09-03
Damascene nisi metal gate high-k transistor App 20020102848 - Xiang, Qi ; et al.	2002-08-01
Contact each methodology and integration scheme Grant 6,413,846 - Besser , et al. July 2, 2	2002-07-02
Resist trim process to define small openings in dielectric layers App 20020068436 - Dakshina-Murthy, Srikanteswara ; et al.	2002-06-06
Method Of Forming Nickel Silicide Using A One-step Rapid Thermal Anneal Process And Backend Processing App 20020068408 - Paton, Eric N. ; et al.	2002-06-06
Method of selectively controlling contact resistance by controlling impurity concentration and silicide thickness Grant 6,391,750 - Chen , et al. May 21, 2	2002-05-21
Metal gate with PVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process Grant 6,392,280 - Besser , et al. May 21, 2	2002-05-21
Method of forming junction-leakage free metal salicide in a semiconductor wafer with ultra-low silicon consumption Grant 6,383,906 - Wieczorek , et al. May 7, 2	2002-05-07
Enhancement of nickel silicide formation by use of nickel pre-amorphizing implant Grant 6,380,057 - Buynoski , et al. April 30, 2	2002-04-30
Method to control mechanical stress of copper interconnect line using post-plating copper anneal Grant 6,368,967 - Besser April 9, 2	2002-04-09
Silicide gate transistors Grant 6,368,950 - Xiang , et al. April 9, 2	2002-04-09
Selective Deposition Process For Passivating Top Interface Of Damascene-Type Cu Interconnect Lines App 20020027261 - Besser, Paul R. ; et al.	2002-03-07
Method For Reducing Stress-induced Voids For 0.25u And Smaller Semiconductor Chip Technology By Annealing Interconnect Lines And Using Low Bias Voltage And Low Interlayer Dielectric Deposition Rate And Semiconductor Chip Made Thereby App 20020003306 - NGO, MINH VAN ; et al.	2002-01-10
Dielectric formation to seal porosity of low dielectic constant (low k) materials after etch App 20010051420 - Besser, Paul R. ; et al.	2001-12-13
Method for reducing stress-induced voids for 0.25m.mu. and smaller semiconductor chip technology by annealing interconnect lines and using low bias voltage and low interlayer dielectric deposition rate and semiconductor chip made thereby Grant 6,329,718 - Van Ngo , et al. December 11, 2	2001-12-11
Method of forming cobalt silicide Grant 6,329,277 - Liu , et al. December 11, 2	2001-12-11
Method For Reducing Stress-induced Voids For 0.25 Micron And Smaller Semiconductor Chip Technology By Annealing Interconnect Lines Prior To Ild Deposition And Semiconductor Chip Made Thereby App 20010040295 - TRACY, BRYAN ; et al.	2001-11-15
Photoresist removal using a polishing tool Grant 6,315,637 - Apelgren , et al. November 13, 2	2001-11-13
Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors Grant 6,300,203 - Buynoski , et al. October 9, 2	2001-10-09
High dielectric constant materials as gate dielectrics Grant 6,297,107 - Paton , et al. October 2, 2	2001-10-02
Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of refractory metal layer Grant 6,274,511 - Wieczorek , et al. August 14, 2	2001-08-14
Method of forming a semiconductor device with metal silicide regions Grant 6,268,255 - Besser , et al. July 31, 2	2001-07-31
Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of source and drain regions Grant 6,255,214 - Wieczorek , et al. July 3, 2	2001-07-03
Wire bonding CU interconnects Grant 6,239,494 - Besser , et al. May 29, 2	2001-05-29
Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide Grant 6,228,761 - Ngo , et al. May 8, 2	2001-05-08
Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide Grant 6,201,303 - Ngo , et al. March 13, 2	2001-03-13
Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines Grant 6,174,743 - Pangrle , et al. January 16, 2	2001-01-16
Shallow junction formation by out-diffusion from a doped dielectric layer through a salicide layer Grant 6,150,243 - Wieczorek , et al. November 21, 2	2000-11-21
High density plasma oxide gap filled patterned metal layers with improved electromigration resistance Grant 6,046,106 - Tran , et al. April 4, 2	2000-04-04
Manufacturing capping layer for the fabrication of cobalt salicide structures Grant 5,970,370 - Besser , et al. October 19, 1	1999-10-19
Deposition of a conductor in a via hole or trench Grant 5,918,149 - Besser , et al. June 29, 1	1999-06-29
Eliminating metal extrusions by controlling the liner deposition temperature Grant 5,789,315 - Besser , et al. August 4, 1	1998-08-04
Method for producing alloy films using cold sputter deposition process Grant 5,597,458 - Sanchez, Jr. , et al. January 28, 1	1997-01-28