U.S. patent application number 12/251959 was filed with the patent office on 2009-02-05 for semiconductor device.
This patent application is currently assigned to ADVANCED MICRO DEVICES, INC.. Invention is credited to Paul R. Besser, Simon Siu-Sing Chan, William G. En, Thorsten Kammler, Eric N. Paton.
Application Number | 20090032888 12/251959 |
Document ID | / |
Family ID | 40029455 |
Filed Date | 2009-02-05 |
United States Patent
Application |
20090032888 |
Kind Code |
A1 |
En; William G. ; et
al. |
February 5, 2009 |
SEMICONDUCTOR DEVICE
Abstract
A sidewall spacer structure is formed adjacent to a gate
structure whereby a material forming an outer surface of the
sidewall spacer structure contains nitrogen. Subsequent to its
formation the sidewall spacer structure is annealed to harden the
sidewall spacer structure from a subsequent cleaning process. An
epitaxial layer is formed subsequent to the cleaning process.
Inventors: |
En; William G.; (Milpitas,
CA) ; Kammler; Thorsten; (Ottendorf-Okrilla, DE)
; Paton; Eric N.; (Morgan Hill, CA) ; Besser; Paul
R.; (Sunnyvale, CA) ; Chan; Simon Siu-Sing;
(Saratoga, CA) |
Correspondence
Address: |
LARSON NEWMAN ABEL & POLANSKY, LLP
5914 WEST COURTYARD DRIVE, SUITE 200
AUSTIN
TX
78730
US
|
Assignee: |
ADVANCED MICRO DEVICES,
INC.
Sunnyvale
CA
|
Family ID: |
40029455 |
Appl. No.: |
12/251959 |
Filed: |
October 15, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11209871 |
Aug 23, 2005 |
7456062 |
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12251959 |
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10969774 |
Oct 20, 2004 |
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11209871 |
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Current U.S.
Class: |
257/408 ;
257/E29.266 |
Current CPC
Class: |
H01L 29/6656 20130101;
H01L 21/28123 20130101; H01L 29/42376 20130101; H01L 29/6659
20130101; H01L 29/66628 20130101; H01L 21/28035 20130101; H01L
29/7834 20130101 |
Class at
Publication: |
257/408 ;
257/E29.266 |
International
Class: |
H01L 29/78 20060101
H01L029/78 |
Claims
1. A device comprising: a conductive gate of a transistor overlying
a semiconductor substrate; a sidewall spacer structure abutting the
conductive gate, the sidewall spacer structure comprising a first
sidewall spacer and a second sidewall spacer between the first
sidewall spacer and the conductive gate; a source/drain extension
region underlying the second sidewall spacer; a deep source/drain
region underlying the first sidewall spacer; and an epitaxial layer
abutting the outer surface of the sidewall spacer structure.
2. The device of claim 1 wherein the first sidewall spacer
comprises a first offset spacer and a first liner layer, the first
liner layer underlying and abutting the first offset spacer, and
wherein the second sidewall spacer comprises a second offset spacer
between the first liner layer and the conductive gate.
3. The device of claim 2 wherein the first liner layer contains an
oxide selectively etchable from the first offset layer.
4. The device of claim 3 wherein the first offset spacer contains
nitrogen.
5. The device of claim 3 wherein the first liner layer of the first
sidewall spacer contains a silicon oxynitride.
6. The device of claim 5 further comprising an epitaxial layer
overlying the conductive gate structure.
7. The device of claim 5 further comprises a silicide at the
epitaxial layer.
8. The device of claim 2, wherein the second sidewall spacer
further comprises a second liner layer between the second offset
spacer and the conductive gate.
9. The device of claim 1, wherein the material forming an outer
surface of the sidewall spacer contains nitrogen.
10. The device of claim 9 wherein the material forming the outer
surface contains a silicon oxynitride.
11. The device of claim 10 further comprising an epitaxial layer
overlying the conductive gate structure.
12. The device of claim 10 further comprises a silicide at the
epitaxial layer.
13. The device of claim 1 further comprises a silicide at the
epitaxial layer.
14. The device of claim 1 further comprising an epitaxial layer
overlying the conductive gate structure.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application is a divisional of U.S. patent
application Ser. No. 11/209,871 (Attorney Docket number 1458-H1949)
entitled "METHOD OF FORMING A SEMICONDUCTOR DEVICE," filed on Aug.
23, 2005, which is a continuation-in-part of U.S. patent
application Ser. No. 10/969,774 (now abandoned) entitled "DEVICE
COMPRISING AN EPITAXIAL LAYER AND METHOD THEREOF", filed on Oct.
20, 2004.
FIELD OF THE DISCLOSURE
[0002] The present disclosure relates generally to semiconductor
devices having sidewall structures.
DESCRIPTION OF THE RELATED ART
[0003] As critical dimensions of semiconductor-based transistors
become smaller the effects of surface contamination on various
processing stages can become more pronounced. For example,
increased junction leakage can occur subsequent to silicidation of
an epitaxial layer when the epitaxial layer is disposed upon a
rough surface as a result of surface contamination. Therefore, a
method of manufacturing overcoming problems such as this would be
useful.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] It will be appreciated that for simplicity and clarity of
illustration, elements illustrated in the Figures have not
necessarily been drawn to scale. For example, the dimensions of
some of the elements are exaggerated relative to other elements for
clarity.
[0005] FIGS. 1-9 illustrate cross-sectional views of a substrate
location during various processing stages used to form a transistor
in accordance with a specific embodiment of the present disclosure;
and
[0006] FIG. 10 illustrates a portion of a device formed using the
methods described in accordance with a specific embodiment of the
present disclosure.
[0007] The use of the same reference symbols in different drawings
indicates similar or identical items.
DESCRIPTION OF THE PREFERRED EMBODIMENT(S)
[0008] In accordance with a specific embodiment of the present
disclosure a sidewall spacer structure is formed adjacent to a gate
structure whereby a material forming an outer surface of the
sidewall spacer structure contains nitrogen. Subsequent to its
formation the sidewall spacer structure is annealed to harden the
sidewall spacer structure from a subsequent cleaning process.
Improved epitaxial regions are realized as a result of hardening
the sidewall spacer structure prior to epitaxial formation. The
present disclosure will be better understood with respect to FIGS.
1-8.
[0009] FIGS. 1 through 9 illustrate, in cross section, a location
10 of a workpiece where a transistor of a semiconductor device is
being manufactured according to specific embodiments of the present
disclosure. At the manufacturing stage illustrated in FIG. 1,
deposition, photolithography, and etch processes have been
conducted on location 10 such that a conductive gate structure 14
of the transistor being manufactured has been formed overlying a
gate dielectric layer 12 that overlies a substrate 5. Substrate 5
is typically a semiconductor substrate that is a mono-crystalline
silicon substrate, a gallium arsenide substrate, a
silicon-on-insulator substrate, a silicon-on-sapphire substrate, or
the like. The gate dielectric layer 12 is typically an oxide layer
physically separating the conductive gate structure 14 from the
underlying substrate 5 where a channel location of the transistor
being formed resides. The gate dielectric will typically have a
thickness in the range of 0.5 to 5 Angstroms.
[0010] The conductive gate structure 14 will typically contain
polysilicon, though it may contain other materials and multiple
layers. Conductive gate structure 14 is illustrated in FIG. 1 to
have a left sidewall and a right sidewall substantially parallel to
each other, and perpendicular to a planer interface between the
gate oxide layer 12 and the substrate 5. A length of the conductive
gate structure 14 is the distance between its left and right
sidewalls as illustrated in FIG. 1 and will typically be in the
range of 10 to 500 nm.
[0011] FIGS. 2-7 illustrate a specific embodiment of forming a
sidewall spacer structure having two spacers adjacent to conductive
gate structure 14. FIG. 2 illustrates location 10 subsequent to
forming liner 16 overlying conductive gate structures 14 and a
layer 18 overlying layer 16 from which a sidewall offset spacer
will be formed. Layer 16 is thinner than layer 18, and is referred
to as a liner, or liner layer. Layer 16 is typically a dielectric
material such as an oxide, a nitride (i.e., Silicon oxynitride), or
polysilicon that protects conductive gate structure 14 and
substrate 5 from subsequent processing and need not be present
depending upon subsequent processing steps. The material of layer
18 is typically chosen to be selectively etchable relative to the
material of layer 16, and is used to create a sidewall spacer
referred to as a sidewall offset spacer. In one embodiment, when
layer 16 is an oxide, layer 18 will be a nitride, such as a silicon
oxynitride; alternately, if liner 16 is a nitride, layer 18 will be
an oxide. Materials forming layers 16 and 18 selected such that an
etch chemistry that is used to etch layer 18 will etch layer 18 at
a faster rate than layer 16.
[0012] FIG. 3 illustrates location 10 subsequent to etching of
layer 18 thereby forming a sidewall offset spacer 19 that is
adjacent to conductive gate structure 14. An anisotropic etch is
typically used to remove portions of layer 18 not forming sidewall
offset spacer 19. The anisotropic etch of layer 18, as illustrated
in the embodiment of FIG. 3, results in sidewall offset spacer 19
having a "D" shape, so called because a width of spacer 19 narrows
in a non-linear manner at locations further from gate dielectric 12
to provide a profile similar to the top half of the capital letter
"D". The etch process that forms sidewall offset spacer 19
illustrated in FIG. 3 selectively etches layer 18 relative to layer
16, thereby leaving layer 16. However, in an alternate embodiment
the etch that forms sidewall offset spacer 19 can also remove
portions of layer 16, though typically it is desirable to leave
layer 16 to protect active silicon regions from exposure to the
etch that removes layer 18.
[0013] FIG. 4 illustrates location 10 subsequent to etching
portions of layer 16, thereby exposing a top portion of conductive
gate structure 14 and active silicon at source/drain locations of
the transistor being formed, thus leaving sidewall liner 17, which
is that portion of layer 16 abutting offset spacer 19 to form a
sidewall spacer structure. Conductive gate structure 14, gate
dielectric 13, offset spacer 19, and liner 17 are all part of a
gate structure at the transistor location. A dopant has been
implanted, either prior or subsequent to removal of layer 16, to
form a doped region 20 that facilitates formation of a source/drain
(S/D) extension region. Doped region 20 will have either an N-type
or P-type conductivity depending upon whether an NMOS or PMOS
transistor is being formed.
[0014] FIG. 5 illustrates location 10 subsequent to disposing a
layer 30 overlying the single gate structure of FIG. 4 and a layer
32 overlying layer 30. Layer 30 is typically a liner comprising a
dielectric material, such as an oxide or a nitride that protects
the previously formed gate structure from subsequent processing,
and need not be present depending upon subsequent processing. Layer
32 is typically formed from a material that is selectively etchable
relative liner 30, such as an oxide or a nitride, and will be
etched to create a second sidewall spacer. In accordance with a
specific embodiment of the present disclosure, liner 30 is an oxide
and layer 32 is a material containing nitrogen. For example, layer
32 can be a silicon nitride, such as silicon oxynitride.
[0015] FIG. 6 illustrates location 10 subsequent to etching of
layer 32 to form a sidewall spacer 33 that contains Nitrogen.
Sidewall spacer 19 is between sidewall spacer 33 and conductive
gate 14. An anisotropic etch is typically used to remove portions
of layer 32 not forming sidewall spacer 33, thereby forming a
sidewall spacer 33 with a "D" shape. A subsequent etch is performed
to remove portions of liner 30 to expose a top surface of
conductive gate structure 14 and a surface of substrate 5 as
illustrated in FIG. 7. This subsequent etch leaves a portion 31 of
layer 30 as part of a sidewall spacer structure that includes
spacer 33.
[0016] FIG. 8 illustrates a sidewall spacer structure that includes
both sidewall spacers 19 and 33 being exposed to an anneal 40 to
harden the nitrogen containing spacer 33 from subsequent cleaning
processes. In one embodiment, the anneal 40 is a rapid thermal
anneal (RTA) that spikes at a maximum temperature without holding
the temperature for a substantial amount of time. For example, the
RTA typically will reach a temperature in the range of
400-1200.degree. C. in less than approximately 40 seconds. In one
embodiment, an anneal temperature of 850-1000.degree. C. and a time
of 1-10 seconds. Other temperature ranges for the RTA include
950-1050.degree. C. While anneal 40 has been found to be
advantageous, in other embodiments it can be omitted.
[0017] In one embodiment, location 10 is exposed to a solution
containing HF, after anneal 40 followed by forming an epitaxial
layer 42 at source/drain locations of the transistor being formed.
After the epitaxial layer is formed dopants are implanted to form
doped regions 46 that facilitate formation of deep source/drain
regions of the transistor location. The HF containing solution can
include an aqueous solution of deionized water and hydrofluoric
acid (HF or hydrogen fluoride in water) aqueous solution of
approximately 30:1 (volumetric ratio) at 21 degrees Celsius, for a
time period ranging from between 50-60 seconds. The weight
percentage of HF recommended for the HF aqueous solution is 49% in
a balance of deionized water (H.sub.2O). Bulk HF aqueous solution
can be purchased from various chemical suppliers in the HF weight
percent range of 10% to 49%. In semiconductor fabrication
facilities, this aqueous HF aqueous solution is typically diluted
in the range 10:1 to 200:1. A 10:1 HF is 1 part aqueous HF (at 49%
weight percent) and 10 parts H.sub.2O. The thickness of the
epitaxial layer depends upon device requirements, but typically has
a thickness in the range of 30-300 nm, and more typically in the
range of 30-100 nm. Dopants implanted to form regions 46 will
include P-Type or N-Type dopants based upon whether a NMOS or PMOS
transistor is being formed.
[0018] In an alternate embodiment location 10 is implanted with
dopants at source/drain locations of the transistor location prior
to the anneal 40, and the location 10 is exposed to a solution
containing HF subsequent to anneal 40 and prior to formation of an
epitaxial layer. FIG. 9 illustrates location 10 after formation of
the epitaxial layer 42 at source/drain active regions of transistor
being formed (i.e., abutting the source/drain region). Note that in
the particular embodiment an epitaxial layer 44 is also formed
overlying conductive gate structure 14. In a typical embodiment,
epitaxial layers 42 and 44 are exposed to a silicidation process to
form silicide layers. It will be appreciated that the locations of
the epitaxial layers 42 are defined by the outer surfaces of the
sidewall gate structure to which they abut as well as by
structures, i.e., isolation regions, not illustrated in the
figures.
[0019] FIG. 9 further illustrates semiconductor substrate 5
comprising a semiconductor-on-insulator (SOI) substrate, where
layer 6 represents a semiconductor layer, such as silicon,
overlying an insulator region layer 7, such as an oxide, and layer
7 overlying layer 8, which is a support substrate, which can also
be a semiconductor material, such as silicon.
[0020] FIG. 10 illustrates location 11 after completion of device
processing. Specifically, FIG. 11 includes dielectric layers 71, 72
and 73. Contacts and vias, such as 61 and 50, are formed through
the layers 71 and 72 to contact structures at lower levels.
Dielectric layer 73 is an upper most protective layer of the
completed device, and is commonly referred to as a passivation
layer. A first metal layer includes metal trace 62; a second metal
layer includes conductive trace 51.
[0021] The method described herein provides for a flexible
implementation. Although the disclosure has been described using
certain specific examples, it will be apparent to those skilled in
the art that the invention is not limited to these few examples.
Fore example, various types of deposition and etch techniques are
currently available which could be suitable for use in employing
the method as taught herein. Note also, that although an embodiment
of the present invention has been shown and described in detail
herein, along with certain variants thereof, many other varied
embodiments that incorporate the teachings of the invention may be
easily constructed by those skilled in the art.
[0022] For example, it will be appreciated that any number of
substrate preclean steps can occur before the formation of any
epitaxial layer. For example, U.S. patent application Ser. No.
10/791,346, which is hereby incorporated in its entirety by
reference, discloses several substrate preclean techniques
appropriate for cleaning a substrate prior to forming an epitaxial
layer.
[0023] In one example, contaminates on the surface of a substrate
are subjected to a cleaning process comprising applying a plasma to
a surface of the active regions produce a reduction reaction with
the contaminates in an upper portion of the surface of the active
regions. In an embodiment, the plasma comprises H.sub.2. While the
plasma is being applied to the upper portion of the exposed active
regions, the resultant products or vapor byproducts of the
reduction reaction are removed by the normal vacuum process within
the chamber. Therefore, contaminates contained in the vapor
byproducts and are vented away, leaving the upper portion of the
surface of the active regions suitably clean for the ensuing
epitaxial process. In one embodiment, the plasma process parameters
comprise a gas flow of 450 sccm H2 and 300 sccm argon, at a chamber
temperature of 400 degrees Celsius, with a high frequency (HF)
power setting of 700 W, and a low frequency (LF) power setting of
between approximately 50 to 100 W. Chamber pressure is 1 Torr, and
the spacing between the surface of the active region and the
faceplate of the tool (not shown) should be 300 mils. In other
embodiments, plasma process parameters comprise a gas flow ranging
from between 100-800 sccm H.sub.2 and from between 100 and 600 sccm
argon. Chamber temperatures can range between 300 to 450 degrees
Celsius, and HF power settings from between 400-900 W, with LF
power settings varying from between 0-150 W. Chamber pressures can
range from between 1 mT-5 Torr, with spacing between the surface of
the active region and the faceplate of the tool varying from
between 200 to 400 mils. Exposure times for the various embodiments
utilizing plasma range from between approximately 10 seconds up to
approximately 120 seconds.
[0024] Various tool types are suitable for this cleaning, for
example, CVD (Chemical Vapor Deposition) equipment, HDP (High
Density Plasma) tools, etch chambers, or the like. Differences in
chamber design, power settings, and species, e.g., H.sub.2 with or
H.sub.2 without helium or nitrogen, will result in different
thickness of the layer after anneal. Typically the layer after
anneal will be between 20 and 50 Angstroms thick. This plasma
cleaning process also results in passivation of Si--H bonds in the
layer after anneal. No wet cleaning dip with hydrofluoric (HF) acid
prior to SEG is necessary.
[0025] In addition to no longer requiring an HF dip prior to SEG,
the reduced temperature of this H.sub.2 plasma cleaning treatment
results in a reduction of the SEG process thermal budget of more
than 100 degrees Celsius. Typically pre-SEG cleaning processes are
conducted at approximately 900 degrees Celsius or greater. In an
embodiment of the present disclosure, the cleaning process occurs
at less than approximately 800 degrees Celsius. In another
embodiment, the cleaning process occurs at less than approximately
500 degrees Celsius or less. In addition, the cleaning processes of
the present disclosure could be conducted at less than
approximately 700 degrees Celsius or less, or even at less than
approximately 600 degrees Celsius or less.
[0026] In another embodiment, location including includes a gate
structure and active regions is subjected to a cleaning process
utilizing a low-power dry etch to selectively remove an upper
atomic layer of material from the active regions. The thickness of
the upper atomic layer of material to be removed ranges from
between 20 to about 50 Angstroms. In one embodiment, the dry etch
process is an anisotropic dry etch utilizing a carbon-free gas as
an etchant gas. In another embodiment, the anisotropic dry etch
utilizes an oxygen- and carbon-free gas as an etchant gas. The
etchant gas can comprise HBr, NF.sub.3, SF.sub.6, gaseous
fluorine-interhalogenics such as ClF.sub.3, or any gas containing
fluorine, suitable to disassociate F-radicals, which does not
contain oxygen and carbon. Prior to undergoing the anisotropic dry
etch process, location 200 is subjected to a standard wet etch
chemistry process utilizing a dilute HF solution (100:1) at room
temperature, e.g., 20 to 26 degrees Celsius, for a time period
ranging from 50 to 200 seconds. Following the HF clean, a low-power
dry etch utilizing a temperature of approximately 400 degrees
Celsius, RF power of approximately 375 W, pressure of approximately
150 mTorr, and a gas flow rate ranging from 50 to 100 sccm, is
conducted. In other embodiments, the low-power dry etch utilizes a
temperature ranging from between 300-500 degrees Celsius, with RF
power ranging from between 200-700 W, a pressure ranging between
0-1 Torr, and a gas flow rate ranging from between 10-300 sccm, for
a time ranging between 10 to 60 seconds.
[0027] This low-power dry etch removes carbon and oxygen
contamination, and provides a very clean surface for SEG. The low
temperature HF clean followed by the low-power dry etch does not
require a high temperature bake. This results in a reduction of
thermal budget for SEG of more than 100 degrees Celsius.
[0028] In another embodiment, a cleaning process is used that forms
an oxidation layer of between 20 to 50 Angstroms on an upper
surface of the active regions using a plasma to produce the
oxidation layer on doped active regions. In an embodiment, the
plasma is an O.sub.2 plasma. In another embodiment, the plasma is
an O.sub.3 plasma.
[0029] An O.sub.2 plasma production utilizes O.sub.2 gas at a flow
rate of 400 sccm, a pressure of 5 Torr, an HF of 300 W, an LF of
100 W, and a temperature of 400 degrees Celsius, with the time
ranging from between about 10 to about 120 seconds. The spacing
between the surface of the active regions and the faceplate of the
vapor deposition apparatus (not shown) should be 400 mils. In other
embodiments, the plasma production utilizes O.sub.2 gas at a flow
rate of between 100 and 1000 sccm, a pressure ranging from between
2-10 Torr, an HF ranging between 200-500 W, an LF ranging between
50-200 W, a temperature ranging between 300-450 degrees Celsius,
for a time ranging from between approximately 10 to approximately
120 seconds. In an embodiment, the spacing between the surface of
the active regions and the faceplate of the vapor deposition
apparatus ranges from between 200 and 600 mils. The tool type used
to generate the plasma could be CVD equipment, HDP tools, or etch
chambers. In an embodiment where the plasma is O.sub.3, plasma
production utilizes O.sub.3 gas at a flow rate of 300 sccm, a
pressure of 5 Torr, an HF of 300 W, an LF of 100 W, and a
temperature of 400 degrees Celsius for a time period ranging from
between 10 to 120 seconds. The spacing between the surface of the
active regions and the face plate of the vapor deposition apparatus
(not shown) should be 400 mils. In other embodiments, plasma
production utilizes O.sub.3 gas at a flow rate of between 50 and
600 sccm, a pressure ranging from between 2-10 Torr, an HF ranging
between 200-500 W, an LF ranging between 50-200 W, and a
temperature ranging from between 300-450 degrees Celsius for a time
period ranging from between about 10 to about 120 seconds. In an
embodiment, the spacing between the surface of the active regions
and the faceplate of the vapor deposition apparatus ranges from
between 200 and 600 mils. As was the case with the O.sub.2 plasma,
the tool type used to generate the plasma could be HDP tools, CVD
equipment, or etch chambers.
[0030] Forming the oxidation layer facilitates trapping or fixing
contamination in the oxide layer overlying the upper layer of the
doped active regions for subsequent removal using a wet chemistry
process. The wet etch chemistry process utilizes a dilute HF acid
solution of 100:1 at room temperature, e.g. 20 to 26 degrees
Celsius, for a time ranging from 50 to 200 seconds. Differences in
chamber design, power settings and species employed, e.g., O.sub.2
or O.sub.3, results in differing thickness of the oxidation layer,
hence the wide range in times for the HF dip. The use of an O.sub.2
or O.sub.3 plasma to create a contamination-trapping oxidation
layer for removal by a room temperature HF dip results in a
reduction of the thermal input for location 300.
[0031] Another possible pre-clean, different from the one described
above, prior to formation of an SEG that facilitates a reduced
temperature H.sub.2 bake is performed following formation of any
desired spacers, which can comprise one or more nitride or oxide
layers and prior to SEG formation. This pre-clean and comprises a
first pre-rinse with deionized water, followed by an oxide etch
utilizing an aqueous solution of deionized water and hydrofluoric
acid (HF or hydrogen fluoride in water) aqueous solution of
approximately 30:1 (volumetric ratio) at 21 degrees Celsius, for a
time period ranging from between 50-60 seconds. The weight
percentage of HF recommended for the HF aqueous solution is 49% in
a balance of deionized water (H.sub.2O). Bulk HF aqueous solution
can be purchased from various chemical suppliers in the HF weight
percent range of 10% to 49%. In semiconductor fabrication
facilities, this aqueous HF aqueous solution is typically diluted
in the range 10:1 to 200:1. A 10:1 HF is 1 part aqueous HF (at 49%
weight percent) and 10 parts H.sub.2O. It will be appreciated that
the etch rate of the HF aqueous solution is substantially linear
with respect to both the concentration of the HF aqueous solution
and the etch time. Therefore, various combinations of HF
concentrations and etch times can be used to accomplish the oxide
etch. Additionally, the temperature may vary.
[0032] After the HF etch, an overflow rinse utilizing deionized
water is performed for a period ranging from approximately 120 to
600 seconds with a typical rinse being about 400 seconds. The
cleaning process of portion 100 results in etching away of the
surface contamination/debris located on substrate 10 resulting from
offset spacer formation and/or dopant implantation. The upper
semiconductor surface, i.e. silicon surface, of substrate 10 is
also slightly etched, for example, from one to several mono layers
of silicon, during the HF etch.
[0033] It should be noted that the amount of material removed
during the HF etch is dependent upon the type of material being
removed. For example, when native oxide is present, the HF etch
will remove approximately 20 to 30 Angstroms of oxide. If a
deposited oxide layer is present in addition to a native oxide, an
over-etch of approximately 30% is generally desirable. For example,
if removal of 100 Angstroms of a chemical vapor deposition (CVD)
oxide is desired, the HF etch could be employed to remove
approximately 120 to 130 Angstroms oxide removal. This latter
example would be applicable in applications where a liner oxide of
approximately 100 Angstroms thickness is employed between a
conductive gate 25 and a nitride spacer.
[0034] The next steps in the cleaning process comprise a second
pre-rinse with deionized water of approximately 30 seconds duration
precedes the performance of a Standard Clean-1 (SC-1), a quick dry
rinse (QDR), and a Standard Clean-2 (SC-2). The SC-1 and SC-2
components are followed by a second QDR, and an HF: H.sub.2O etch,
a third rinse, and an isopropyl alcohol (IPA) dry. The amount of
material removed by the SC-1 and SC-2 components are implemented
such that they etch from approximately one monolayer of silicon to
approximately 10 to 100 Angstroms of silicon.
[0035] In an embodiment, the SC-1 utilizes an aqueous solution of
ammonium hydroxide:hydrogen peroxide:deionized water at a ratio of
approximately 1:1-4:6-40, at a temperature of approximately 60
degrees Celsius for approximately 72 minutes, to etch approximately
100 Angstroms of silicon. Synonyms for ammonium hydroxide
(NH.sub.4OH) include ammonia solution (typically contains between
12% and 44% ammonia before dilution), dilute ammonia, or
concentrated ammonia. A first quick dry rinse is conducted for
approximately 3 minutes. In an embodiment, the SC-2 utilizes a
solution of hydrochloric acid:hydrogen peroxide:deionized water at
an initial ratio of approximately 1:1:50 at a temperature of
approximately 60 degrees for about 5 minutes. A second quick dry
rinse is then conducted. Synonyms for hydrochloric acid (HCl) are
hydrogen chloride, anhydrous hydrogen chloride, aqueous hydrogen
chloride, chlorohydric acid, spirit of salts, and muriatic
acid.
[0036] In a particular embodiment, the SC-1 utilizes a solution of
ammonium hydroxide:hydrogen peroxide:deionized water at a ratio of
approximately 1:4:20 at a temperature ranging of approximately 60
degrees Celsius for approximately 72 minutes. The SC-1 is the step
in the clean sequence that etches the silicon. This occurs because
the H.sub.2O.sub.2 (the oxidizer) becomes depleted in the solution
with increasing time and increasing temperature. The methods of the
present disclosure allow the initial concentration of hydrogen
peroxide to be depleted to facilitate etching of the upper-most
semiconductor portion. Depletion of the H.sub.2O.sub.2 is greatly
enhanced when the solution temperature rises above 80 degrees
Celsius, which can lead to an etch that is difficult to control if
not carefully monitored. The temperature range of the SC-1 is
expected to be approximately 55 to 85 degrees Celsius, with the
etch occurring in a shorter period of time at higher temperatures
than at lower temperatures. It is expected that the SC-1 etching
will be better controlled at temperatures in the range of 55-80
degrees Celsius and better still at temperatures in the range of
55-75 degrees Celsius. Generally, it is expected that the substrate
will be exposed to the SC-1 etch process for longer that 60
minutes. When the oxidizer stops protecting the silicon surface,
the ammonium hydroxide (NH.sub.4OH) starts to etch the silicon.
Thus, a small amount of silicon can be etched in a controlled
manner. The SC-1 can be performed in a re-usable bath where the
solution is re-circulated and heated to maintain the desired
temperature.
[0037] The mechanism of silicon and SiO.sub.2 etching by a
NH.sub.4OH/H.sub.2O.sub.2 solution occurs when the solution is
allowed to be depleted of H.sub.2O.sub.2. An alkaline solution,
such as NH4OH4 in our example, will attack silicon by water
molecules, according to the reaction:
Si+2H.sub.2O+2OH.sup.-.fwdarw.Si(OH).sub.2(O.sup.-).sub.2+2H.sub.2.uparw-
.
A passivation layer formed by the H.sub.2O.sub.2 prevents this
attack by the NH.sub.4OH. H.sub.2O.sub.2 decomposes in the course
to form O.sub.2 and H.sub.2O.
H.sub.2O.sub.2-.fwdarw.H.sub.2O+1/2O.sub.2
When the concentration of H.sub.2O.sub.2 is below
3.times.10.sup.-3M, then silicon will begin to etch, because of the
absence of the inhibition layer.
[0038] As indicated in the above equations, heat is given off as
the H.sub.2O.sub.2 is depleted. If a bath is used that is not
recharged with fresh solution all H.sub.2O.sub.2 will be depleted,
thereby no longer releasing heat. Therefore, the temperature can be
monitored on the low end to indicate when the solution should be
refreshed, while the temperature on the high end is monitored to
prevent unusually rapid decomposition of the H.sub.2O.sub.2, which
can lead to a process that is difficult to control.
[0039] The first quick dry rinse is conducted for approximately 3
minutes. The subsequent SC-2 utilizes a solution of hydrochloric
acid:hydrogen peroxide:deionized water at a ratio of approximately
1:1:50 at a temperature of approximately 60 degrees for about 5
minutes. A quick dry rinse with deionized water, followed by an IPA
dry process, is performed following the SC-2.
[0040] The IPA dry process uses a heated IPA vapor at approximately
82 degrees Celsius. The IPA vapor is generated in a separate
chamber with 100% N.sub.2 bubbled through 100% IPA (heated to 82
degrees Celsius). The IPA condenses on the wafer, and the solution
drips off the bottom of the wafer. The IPA vapor concentration is
slowly diluted to 100% N.sub.2 before the wafers are removed from
the rinsing/drying tank.
[0041] Subsequent to the SC-1 and SC-2 processes, the substrate
will be further recessed (etched) as a result of the cleaning
process. Next, an HF: H2O etch can be conducted at an aqueous
solution ratio of 200:1 for about 65 seconds, which typically
results in approximately 30 Angstroms of oxide removal. The HF: H2O
etch 8 is followed by a rinse with deionized water for
approximately a 10 minute duration. The deionized water rinse is
followed by an IPA dry as described in the preceding paragraph. At
this time, the source/drain regions of the substrate are ready for
ion implantation or selective epitaxial growth.
[0042] In a particular embodiment, the SC-1 process comprises a
pre-rinse with deionized water of approximately 30 seconds
duration. The pre-rinse is followed by a SC-1 solution at a ratio
of approximately 1:1-4:6-40, which includes the subranges of
0.25:1:5, 0.5:1:5, 1:1:5, 1:1:6, 1:4:20, and 1:1:40, ammonium
hydroxide: hydrogen peroxide: deionized water at a temperature of
approximately 60 degrees Celsius for approximately 5 minutes. A
quick dump rinse (QDR) is then performed for approximately 3
minutes.
[0043] Following the SC-1 cleaning process, an SC-2 cleaning
process is performed. In an embodiment, the SC-2 cleaning process
includes utilizing an aqueous solution of hydrochloric
acid:hydrogen peroxide:deionized water at a ratio of approximately
1:1:50 at a temperature of approximately 60 degrees Celsius for
approximately 5 minutes. A QDR is then performed, and portion 200
is ready for the third cleaning. The weight percent composition of
the hydrochloric acid: hydrogen peroxide: deionized water is 29%
(weight percent) hydrochloric acid and 30% (weight percent)
hydrogen peroxide in a balance of deionized water.
[0044] After the SC-1 and SC-2, a third cleaning process comprising
an approximate 30 second pre-rinse, an oxide etch, an overflow
rinse and an IP dry is performed. The oxide etch is accomplished
utilizing a solution of deionized water and hydrofluoric acid at a
ratio of approximately 200:1 for a time period ranging from between
450-650 seconds. Following the HF etch, an overflow rinse is
performed for approximately 10 minutes. A final isopropyl alcohol
(IPA) dry is then performed. Approximately 120-140 Angstroms of the
surface of substrate 20 is removed in this process. Portion 200 is
ready to undergo selective epitaxial growth.
[0045] The above-described cleaning process has been found to
facilitate formation of an epitaxial layer on a semiconductor
surface, specifically silicon. Because various etch processes can
etch N- and P-type regions at different rates, it can be useful to
amorphize an upper-most surface of the source/drain regions prior
to the above-described clean to reduce any preferential etch
differences between substrate regions of differing dopant
types.
[0046] For example, the above-described clean process can etch the
N-type silicon preferentially, as compared to the P-type silicon,
resulting in a quality difference of the SEG between the N and P
regions after SEG processing. Etch rate differences between N- and
P-type regions can allow for contaminates to remain in the
lesser-etched region. For example, an etch process that does not
etch P-type regions at the same rate as N-type regions can result
in P-regions maintaining embedded carbon that is incorporated from
previous process steps. Without appropriate etching of silicon in
the P-type regions during the clean, the carbon will remain, and
the SEG will grow inconsistently. A high bake temperature of
900.degree. C. can be used to overcome this growth issue on P
areas, however, as stated previously, high bake temperatures can be
detrimental to the device in that it causes diffusion and
deactivation of the dopants. Amorphizing the source/drain regions
can reduce etch differences associated with the above-described
cleaning process as well as other processes that are used to etch
doped substrate regions, thereby improving the quality of both the
N and P regions.
[0047] It has been observed that the selective etching may be
P-type over N-type, or N-type over P-type depending on the solution
temperature, flow rate of the aqueous ammonia, concentration of the
aqueous ammonia, agitation, or illumination of light. By
amorphizing the silicon in this manner to a pre-defined depth, it
has been observed that unbiased etching to the depth of the
amorphized silicon can be achieved.
[0048] In one embodiment, N- and P-type extensions formed in the
source/drain regions are amorphized by being implanted with the Xe,
at a dose of 2E14 and energy of 10 keV, to create an amorphous
depth of 100 A.
[0049] In accordance with another embodiment, a spacer structure
having an undercut can be used to reduce or inhibit facet formation
during a selective epitaxial growth process. Such a process can
allow for greater lateral uniformity of junction or silicide
features during implantation or silicidation processes, and can be
accomplished by using a spacer formed with a bi-layer of materials,
e.g., a thin liner, such as portion 29 of FIG. 1, of one material
underlying another layer of material from which the `main` spacer
is formed. The thin liner and other material layer are selected
such that the two materials are selectively etchable with respect
to the other, for example, a thin oxide liner and a nitride layer.
By etching the underlying portion of the spacer, an undercut can be
formed that reduces facets during epitaxial formation.
[0050] In addition, a number of etch chemistries can be used to
form nitride spacers. These etch chemistries are known in the art,
and include the use of gas mixtures such as NF3/HBr, CF4/HBr,
SF6/HBr, or any combination of these gases. In an embodiment,
helium or argon can be included in the gas mixture to dilute the
etch chemistry.
[0051] To improve the selectivity of the nitride etch over oxide,
oxygen (O.sub.2) can be added to the gas mixture flowing into the
plasma reactor during etch. In an embodiment, the addition of
oxygen during the etching process is an amount between 2 percent
and 15 percent by volume. The plasma reactor may be of any type
which provides ion bombardment, e.g., capacitively-coupled
parallel-plate reactor, or inductively coupled plasma with wafer
(RF) bias. The wall temperature of the plasma reactor during
etching is between 20 degrees C. and 60 degrees C., while the wafer
platen (chuck) temperature is between 50 degrees C. and 80 degrees
C. The gas mixture has a total gas flow during etching of between
75 sccm and 150 sccm for 200 mm wafers. The total gas flow would
require an increase for 300 mm wafers, in order to compensate for
the increase in the plasma reactor chamber volume. The chamber
pressure is in the range of 50-150 mtorr for 200 mm wafers using
capacitively coupled plasma reactor systems. It should be noted
that the chamber pressure necessarily depends upon the size of the
chamber, as well as the manufacturer of the plasma reactor
equipment. The examples presented herein reference Applied
Material's MERIE (magnetically enhanced reactive ion etch)
systems.
[0052] The amount of oxygen added is dependant upon the particular
etch chemistry chosen. An exemplary etch chemistry could be CF4,
HBr, and He--O2, with gas flow ratios, by volume, of CF4:HBr:He--O2
of approximately 10:(2-6):(1-6). The ratio of He--O2 used is 70/30
percent by volume, however, other appropriate ratios would work as
well. In an embodiment, addition of oxygen during the etching
process is an amount between 2% and 15% by volume. The addition of
oxygen does not greatly alter the resultant spacer 16 profile,
although small alterations are possible. This could, however, be
compensated for by changing (i.e., increasing or decreasing) the
thickness of nitride layer. Hence the addition of oxygen during the
etching process does not require adjustments of other etch process
parameters. The addition of oxygen enhances the etch selectivity of
the nitride layer 14 to the liner oxide layer 15. In an embodiment,
the etch selectivity for silicon nitride is between 1:2 and
1:3.
[0053] Benefits, other advantages, and solutions to problems have
been described above with regard to specific embodiments. However,
the benefits, advantages, solutions to problems, and any element(s)
that may cause any benefit, advantage, or solution to occur or
become more pronounced are not to be construed as a critical,
required, or essential feature or element of any or all the claims.
Accordingly, the present invention is not intended to be limited to
the specific form set forth herein, but on the contrary, it is
intended to cover such alternatives, modifications, and
equivalents, as can be reasonably included within the spirit and
scope of the invention.
* * * * *