Paton; Eric N.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Paton; Eric N..The latest application filed is for "method of forming isolation regions for integrated circuits".

Company Profile

0.52.11

Paton; Eric N. - Morgan Hill CA
Paton; Eric N. - Morgan Hills CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method of forming isolation regions for integrated circuits Grant 7,713,834 - Wang , et al. May 11, 2	2010-05-11
Shallow trench isolation process Grant 7,648,886 - Ngo , et al. January 19, 2	2010-01-19
Method Of Forming Isolation Regions For Integrated Circuits App 20090047770 - Wang; Haihong ; et al.	2009-02-19
Semiconductor Device App 20090032888 - En; William G. ; et al.	2009-02-05
Method of forming a semiconductor device Grant 7,456,062 - En , et al. November 25, 2	2008-11-25
Method of forming isolation regions for integrated circuits Grant 7,422,961 - Wang , et al. September 9, 2	2008-09-09
Method of forming a semiconductor device Grant 7,402,485 - En , et al. July 22, 2	2008-07-22
Method and apparatus for controlling the thickness of a selective epitaxial growth layer Grant 7,402,207 - Besser , et al. July 22, 2	2008-07-22
Scanning laser thermal annealing Grant 7,351,638 - Tabery , et al. April 1, 2	2008-04-01
Fully depleted strained semiconductor on insulator transistor and method of making the same Grant 7,312,125 - Xiang , et al. December 25, 2	2007-12-25
Methods for post offset spacer clean for improved selective epitaxy silicon growth Grant 7,241,700 - En , et al. July 10, 2	2007-07-10
Localized halo implant region formed using tilt pre-amorphization implant and laser thermal anneal Grant 7,211,489 - Xiang , et al. May 1, 2	2007-05-01
End-of-range defect minimization in semiconductor device Grant 7,091,097 - Paton , et al. August 15, 2	2006-08-15
Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication Grant 7,071,065 - Xiang , et al. July 4, 2	2006-07-04
Remote monitoring of critical parameters for calibration of manufacturing equipment and facilities Grant 6,966,235 - Paton November 22, 2	2005-11-22
Shallow trench isolation process using oxide deposition and anneal Grant 6,962,857 - Ngo , et al. November 8, 2	2005-11-08
Strained silicon MOSFET having reduced leakage and method of its formation Grant 6,924,182 - Xiang , et al. August 2, 2	2005-08-02
Front side seal to prevent germanium outgassing Grant 6,921,709 - Paton , et al. July 26, 2	2005-07-26
Offset spacer process for forming N-type transistors Grant 6,905,923 - Paton , et al. June 14, 2	2005-06-14
Low-temperature post-dopant activation process Grant 6,902,966 - Yu , et al. June 7, 2	2005-06-07
Selective epitaxy to improve silicidation Grant 6,878,592 - Besser , et al. April 12, 2	2005-04-12
Strained silicon NMOS having silicon source/drain extensions and method for its fabrication Grant 6,867,428 - Besser , et al. March 15, 2	2005-03-15
Polysilicon tilting to prevent geometry effects during laser thermal annealing Grant 6,867,080 - Paton , et al. March 15, 2	2005-03-15
Depletion to avoid cross contamination Grant 6,858,503 - Ngo , et al. February 22, 2	2005-02-22
Post silicide laser thermal annealing to avoid dopant deactivation Grant 6,825,115 - Xiang , et al. November 30, 2	2004-11-30
Pre-cleaning for silicidation in an SMOS process Grant 6,811,448 - Paton , et al. November 2, 2	2004-11-02
Reduced dopant deactivation of source/drain extensions using laser thermal annealing Grant 6,812,106 - Xiang , et al. November 2, 2	2004-11-02
Physical vapor deposition of nickel Grant 6,806,172 - Woo , et al. October 19, 2	2004-10-19
Nickel alloy for SMOS process silicidation Grant 6,797,614 - Paton , et al. September 28, 2	2004-09-28
Shallow trench isolation for strained silicon processes App 20040180509 - Wang, Haihong ; et al.	2004-09-16
Mosfets incorporating nickel germanosilicided gate and methods for their formation Grant 6,787,864 - Paton , et al. September 7, 2	2004-09-07
Silicide process using high K-dielectrics Grant 6,784,506 - Xiang , et al. August 31, 2	2004-08-31
Laser thermal oxidation to form ultra-thin gate oxide Grant 6,780,789 - Yu , et al. August 24, 2	2004-08-24
Passivation of nitride spacer Grant 6,764,912 - Foster , et al. July 20, 2	2004-07-20
Shallow trench isolation for strained silicon processes App 20040137742 - Ngo, Minh-Van ; et al.	2004-07-15
Low nisi/si interface contact resistance with preamorphizing and laser thermal annealing Grant 6,746,944 - Xiang , et al. June 8, 2	2004-06-08
Method of fabrication SOI devices with accurately defined monocrystalline source/drain extensions Grant 6,743,689 - Paton , et al. June 1, 2	2004-06-01
Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer Grant 6,730,576 - Wang , et al. May 4, 2	2004-05-04
Mosfets incorporating nickel germanosilicided gate and methods for their formation App 20040061191 - Paton, Eric N. ; et al.	2004-04-01
Reducing agent for high-K gate dielectric parasitic interfacial layer Grant 6,703,277 - Paton , et al. March 9, 2	2004-03-09
Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication Grant 6,703,648 - Xiang , et al. March 9, 2	2004-03-09
Formation of well-controlled thin SiO, SiN, SiON layer for multilayer high-K dielectric applications Grant 6,682,973 - Paton , et al. January 27, 2	2004-01-27
Formation of deep amorphous region to separate junction from end-of-range defects Grant 6,680,250 - Paton , et al. January 20, 2	2004-01-20
In-situ monitoring during laser thermal annealing Grant 6,656,749 - Paton , et al. December 2, 2	2003-12-02
MOSFET having a double gate Grant 6,646,307 - Yu , et al. November 11, 2	2003-11-11
Laser thermal annealing of high-k gate oxide layers Grant 6,632,729 - Paton October 14, 2	2003-10-14
Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing Grant 6,605,513 - Paton , et al. August 12, 2	2003-08-12
Metal silicide gate transistors Grant 6,602,781 - Xiang , et al. August 5, 2	2003-08-05
Process for forming fully silicided gates Grant 6,562,718 - Xiang , et al. May 13, 2	2003-05-13
Electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors Grant 6,559,051 - Buynoski , et al. May 6, 2	2003-05-06
Low-temperature post-dopant activation process App 20030082880 - Yu, Bin ; et al.	2003-05-01
Improved Silicide Process Using High K-dielectrics App 20030042515 - Xiang, Qi ; et al.	2003-03-06
Silicide stop layer in a damascene semiconductor structure App 20030034533 - Paton, Eric N. ; et al.	2003-02-20
Damascene NiSi metal gate high-k transistor Grant 6,475,874 - Xiang , et al. November 5, 2	2002-11-05
Silicide gate transistors Grant 6,465,309 - Xiang , et al. October 15, 2	2002-10-15
Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors Grant 6,465,334 - Buynoski , et al. October 15, 2	2002-10-15
Ozone oxide as a mediating layer in nickel silicide formation App 20020111021 - Paton, Eric N. ; et al.	2002-08-15
Damascene nisi metal gate high-k transistor App 20020102848 - Xiang, Qi ; et al.	2002-08-01
Method Of Forming Nickel Silicide Using A One-step Rapid Thermal Anneal Process And Backend Processing App 20020068408 - Paton, Eric N. ; et al.	2002-06-06
Silicide gate transistors Grant 6,368,950 - Xiang , et al. April 9, 2	2002-04-09
Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors Grant 6,300,203 - Buynoski , et al. October 9, 2	2001-10-09
Method and apparatus for chemical polishing using field responsive materials Grant 6,297,159 - Paton October 2, 2	2001-10-02
Metalorganic decomposition deposition of thin conductive films on integrated circuits using reducing ambient Grant 6,048,790 - Iacoponi , et al. April 11, 2	2000-04-11

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