Chan; Simon Siu-Sing

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chan; Simon Siu-Sing.The latest application filed is for "non-volatile memory with silicided bit line contacts".

Company Profile

1.27.22

Chan; Simon Siu-Sing - Saratoga CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Non-volatile memory with silicided bit line contacts Grant 11,183,509 - Lu , et al. November 23, 2	2021-11-23
Non-Volatile Memory With Silicided Bit Line Contacts App 20200411537 - LU; Ching-Huang ; et al.	2020-12-31
Self-aligned trench isolation in integrated circuits Grant 10,256,137 - Lu , et al.	2019-04-09
Self-aligned Trench Isolation In Integrated Circuits App 20180166323 - LU; Ching-Huang ; et al.	2018-06-14
Self-aligned trench isolation in integrated circuits Grant 9,831,114 - Lu , et al. November 28, 2	2017-11-28
Non-volatile memory with silicided bit line contacts Grant 9,666,591 - Lu , et al. May 30, 2	2017-05-30
Self-aligned trench isolation in integrated circuits Grant 9,437,470 - Lu , et al. September 6, 2	2016-09-06
Buried Trench Isolation in Integrated Circuits App 20160211321 - Sugino; Rinji ; et al.	2016-07-21
Non-Volatile Memory With Silicided Bit Line Contacts App 20160211271 - LU; Ching-Huang ; et al.	2016-07-21
Non-volatile memory with silicided bit line contacts Grant 9,252,154 - Lu , et al. February 2, 2	2016-02-02
Self-aligned Trench Isolation In Integrated Circuits App 20150097245 - LU; Ching-Huang ; et al.	2015-04-09
Buried Trench Isolation In Integrated Circuits App 20150097224 - XUE; Lei ; et al.	2015-04-09
Non-Volatile Memory With Silicided Bit Line Contacts App 20150017795 - Lu; Ching-Huang ; et al.	2015-01-15
Non-Volatile memory with silicided bit line contacts Grant 8,866,213 - Lu , et al. October 21, 2	2014-10-21
Non-Volatile Memory With Silicided Bit Line Contacts App 20140209993 - LU; Ching-Huang ; et al.	2014-07-31
Method and manufacture for embedded flash to achieve high quality spacers for core and high voltage devices and low temperature spacers for high performance logic devices Grant 8,598,005 - Chan , et al. December 3, 2	2013-12-03
Method And Manufacture For Embedded Flash To Achieve High Quality Spacers For Core And High Voltage Devices And Low Temperature Spacers For High Performance Logic Devices App 20130023101 - Chan; Simon Siu-Sing ; et al.	2013-01-24
Integrated circuit system with memory system Grant 8,114,736 - Chan , et al. February 14, 2	2012-02-14
Integrated circuit eliminating source/drain junction spiking Grant 8,102,009 - Chan , et al. January 24, 2	2012-01-24
Multi-silicide system in integrated circuit technology Grant 7,843,015 - Chiu , et al. November 30, 2	2010-11-30
Contact liner in integrated circuit technology Grant 7,670,915 - Ryan , et al. March 2, 2	2010-03-02
Semiconductor Device App 20090032888 - En; William G. ; et al.	2009-02-05
Method of forming a semiconductor device Grant 7,456,062 - En , et al. November 25, 2	2008-11-25
Memory System With Poly Metal Gate App 20080149990 - Wang; Connie Pin Chin ; et al.	2008-06-26
Integrated Circuit System With Memory System App 20080153224 - Wang; Connie Pin Chin ; et al.	2008-06-26
Integrated Circuit System With Memory System App 20080150011 - Chan; Simon Siu-Sing ; et al.	2008-06-26
Integrated Circuit System With Memory System App 20080150042 - Chan; Simon Siu-Sing ; et al.	2008-06-26
Integrated Circuit System With Implant Oxide App 20080142874 - Fang; Shenqing ; et al.	2008-06-19
Selectable open circuit and anti-fuse element Grant 7,250,667 - Chan , et al. July 31, 2	2007-07-31
Integrated Circuit Eliminating Source/drain Junction Spiking App 20070085149 - Chan; Simon Siu-Sing ; et al.	2007-04-19
Multi-silicide system in integrated circuit technology App 20060267087 - Chiu; Robert J. ; et al.	2006-11-30
Method of eliminating source/drain junction spiking, and device produced thereby Grant 7,132,352 - Chan , et al. November 7, 2	2006-11-07
Selectable Open Circuit And Anti-fuse Element App 20060208321 - Chan; Darin A. ; et al.	2006-09-21
Reduction of lateral silicide growth in integrated circuit technology Grant 7,064,067 - King , et al. June 20, 2	2006-06-20
Trenches to reduce lateral silicide growth in integrated circuit technology Grant 7,023,059 - Chan , et al. April 4, 2	2006-04-04
Selectable open circuit and anti-fuse element, and fabrication method therefor Grant 7,015,076 - Chan , et al. March 21, 2	2006-03-21
Low stress sidewall spacer in integrated circuit technology Grant 7,005,357 - Ngo , et al. February 28, 2	2006-02-28
Multi-silicide in integrated circuit technology Grant 6,969,678 - Chiu , et al. November 29, 2	2005-11-29
Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance Grant 6,964,875 - En , et al. November 15, 2	2005-11-15
Method of forming planarized shallow trench isolation App 20050158963 - Chan, Darin ; et al.	2005-07-21
Low stress sidewall spacer in integrated circuit technology App 20050153496 - Ngo, Minh Van ; et al.	2005-07-14
Siliciding spacer in integrated circuit technology App 20050048731 - Patton, Jeffrey P. ; et al.	2005-03-03
Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance Grant 6,841,832 - En , et al. January 11, 2	2005-01-11
Selective thickening of the source-drain and gate areas of field effect transistors Grant 6,743,666 - Chan June 1, 2	2004-06-01
Method of preventing dopant depletion in surface semiconductor layer of semiconductor-on-insulator (SOI) device Grant 6,737,337 - Chan , et al. May 18, 2	2004-05-18
Inert atom implantation method for SOI gettering Grant 6,670,259 - Chan December 30, 2	2003-12-30
Semiconductor-on-insulator (SOI) substrate having selective dopant implant in insulator layer and method of fabricating Grant 6,624,476 - Chan , et al. September 23, 2	2003-09-23