U.S. patent application number 09/128057 was filed with the patent office on 2001-11-15 for method for reducing stress-induced voids for 0.25 micron and smaller semiconductor chip technology by annealing interconnect lines prior to ild deposition and semiconductor chip made thereby.
Invention is credited to BESSER, PAUL R., NGO, MINH VAN, TRACY, BRYAN.
Application Number | 20010040295 09/128057 |
Document ID | / |
Family ID | 22433396 |
Filed Date | 2001-11-15 |
United States Patent
Application |
20010040295 |
Kind Code |
A1 |
TRACY, BRYAN ; et
al. |
November 15, 2001 |
METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25 MICRON AND
SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT
LINES PRIOR TO ILD DEPOSITION AND SEMICONDUCTOR CHIP MADE
THEREBY
Abstract
A method for making 0.25 micron semiconductor chips includes
annealing the metal interconnect lines prior to depositing an
inter-layer dielectric (ILD) between the lines. During annealing,
an alloy of aluminum and titanium forms, which subsequently
volumetrically contracts, with the contraction being absorbed by
the aluminum. Because the alloy is reacted prior to ILD deposition,
however, the aluminum is not constrained by the ILD when it
attempts to absorb the contraction of the alloy. Consequently, the
likelihood of undesirable void formation in the interconnect lines
is reduced.
Inventors: |
TRACY, BRYAN; (OAKLAND,
CA) ; BESSER, PAUL R.; (SUNNYVALE, CA) ; NGO,
MINH VAN; (UNION CITY, CA) |
Correspondence
Address: |
LARIVIERE, GRUBMAN & PAYNE, LLP
1 LOWER RAGSDALE, BLDG. 1, SUITE 130
P.O. BOX 3140
MONTEREY
CA
93942
US
|
Family ID: |
22433396 |
Appl. No.: |
09/128057 |
Filed: |
July 29, 1998 |
Current U.S.
Class: |
257/770 ;
257/E21.584; 257/E21.589; 257/E23.16 |
Current CPC
Class: |
H01L 21/76841 20130101;
H01L 21/76858 20130101; H01L 2924/0002 20130101; H01L 21/76885
20130101; H01L 2924/0002 20130101; H01L 2924/00 20130101; H01L
21/7685 20130101; H01L 23/53223 20130101 |
Class at
Publication: |
257/770 |
International
Class: |
H01L 023/48; H01L
023/52; H01L 029/40 |
Claims
What is claimed is:
1. A method for making a semiconductor chip having electrically
conductive lines, comprising: providing at least one substrate;
establishing at least one predetermined pattern of electrically
conductive lines on the substrate; annealing the electrically
conductive lines; then depositing an inter-layer dielectric (ILD)
between the lines.
2. The method of claim 1, wherein each line establishes a stack
including at least one layer having aluminum therein.
3. The method of claim 2, wherein each stack includes at least one
layer having titanium therein, and wherein an alloy of titanium and
aluminum is formed during the annealing step.
4. The method of claim 3, wherein the annealing step is undertaken
by heating the electrically conductive lines to a temperature of
between three hundred fifty degrees Celsius and four hundred fifty
degrees Celsius (350.degree. C.-450.degree. C.) for a period of
between ten minutes and ninety minutes.
5. The method of claim 3, wherein the electrically conductive lines
are exposed to one or more annealing gases during the annealing
step, the annealing gases including nitrogen and hydrogen.
6. The method of claim 3, wherein the ILD is TEOS, and the TEOS is
deposited by directing TEOS onto the lines while simultaneously
removing excess TEOS by sputtering.
7. A chip made according to the method of claim 1.
8. A computing device incorporating the chip of claim 7.
9. A semiconductor chip, comprising: at least one substrate; at
least one predetermined pattern of aluminum lines supported by the
substrate, adjacent lines being separated by distances equal to or
less than about three-eighths of a micron; and an alloy of aluminum
and titanium on the lines, the alloy being reacted prior to
insulating the lines from each other.
10. A computing device incorporating the semiconductor chip of
claim 9.
11. A method for making a semiconductor chip, comprising the steps
of: establishing plural electrically conductive lines on at least
one substrate, at least first lines being separated from second
lines by distances equal to or less than three-eighths of a micron;
reacting a metal alloy on the lines; and after reacting the alloy,
depositing a dielectric between at least two lines that are
adjacent each other, such that the dielectric does not constrain
the lines during the reacting step.
12. The method of claim 11, wherein each line establishes a stack
including at least one layer having aluminum therein and at least
one layer having titanium therein, and the metal alloy is an alloy
of aluminum and titanium.
13. The method of claim 12, wherein the reacting step is undertaken
by annealing the electrically conductive lines to a temperature of
between three hundred fifty degrees Celsius and four hundred fifty
degrees Celsius (350.degree. C.-450.degree. C.) for a period of
between ten minutes and ninety minutes.
14. The method of claim 12, wherein the electrically conductive
lines are exposed to one or more annealing gases during the
reacting step, the annealing gases including nitrogen and
hydrogen.
15. The method of claim 12, wherein the dielectric is TEOS, and the
TEOS is deposited by directing TEOS onto the lines while
simultaneously removing excess TEOS by sputtering.
16. A chip made according to the method of claim 11.
17. A computing device incorporating the chip of claim 16.
Description
TECHNICAL FIELD
[0001] The present invention relates generally to semiconductor
fabrication, and more particularly to methods for improving the
reliability of 0.25.mu. technology semiconductors by alleviating
stress in interconnect lines that might otherwise result in the
formation of voids in the interconnect lines.
BACKGROUND OF THE INVENTION
[0002] Semiconductor chips or wafers are used in many applications,
including as integrated circuits and as flash memory for hand held
computing devices, wireless telephones, and digital cameras.
Regardless of the application, it is desirable that a semiconductor
chip hold as many circuits or memory cells as possible per unit
area. In this way, the size, weight, and energy consumption of
devices that use semiconductor chips advantageously is minimized,
while nevertheless improving the memory capacity and computing
power of the devices.
[0003] In chips that hold integrated circuits, the individual
circuit components are interconnected by conductive elements
referred to as "interconnect lines". These interconnect lines are
typically arranged in a multi-layered pattern that is deposited on
a semiconductive substrate such as silicon. To insulate the
interconnect lines from each other, insulative material is
deposited between adjacent interconnect line layers.
[0004] With the above in mind, so-called 0.25 micron technology has
been developed, in which the distance between adjacent layers of
interconnect lines in an integrated circuit on a semiconductor chip
is equal to or less than about three-eighths of a micron. With such
a small spacing between interconnect lines, which have heights of
about 1.1 microns, the size of the circuits on the chip can be
reduced to result in the above-noted advantages.
[0005] Typically, each electrically conductive interconnect line is
made of a "stack" of metal layers that typically includes a layer
made of aluminum or aluminum alloy, and one or more other metal
layers. The aluminum is deposited as a film over the substrate and
is then lithographically patterned and chemically etched to form a
desired pattern for the circuit's connector lines. Then, a process
referred to as high density plasma (HDP) inter-layer dielectric
(ILD) formation is used to fill the gaps between adjacent metal
stacks with an electrically non-conductive material. Ordinarily,
the ILD deposition step is undertaken at relatively high
temperature, incidentally precipitating the formation of an
intermetallic structure. In current applications, titanium is
commonly used as an underlayer for the aluminum, and the
intermetallic structure that forms in such a device is TiAl.sub.3.
Also, an overlayer that includes TiN anti-reflective coating (ARC)
is disposed over the stacks, for lithography purposes.
[0006] As understood herein, however, voids caused by hydrostatic
stresses undesirably can form in the aluminum, and the voiding of
the aluminum can be accelerated by the formation of the
intermetallic structure. This is undesirable, because when a void
forms in a thin aluminum line, the current path through the line
unfortunately is diverted, thereby adversely affecting the
reliability of the chip.
[0007] The present invention understands that the above-mentioned
hydrostatic stresses arise because the thermal expansion
coefficient of the aluminum layer is different from the thermal
expansion coefficient of the encapsulating ILD and the silicon
substrate, both of which mechanically constrain the aluminum.
Furthermore, when an intermetallic structure such as TiAl.sub.3 is
formed, the intermetallic structure can volumetrically contract (by
5.9%, in the case of TiAl.sub.3), and the aluminum in the
intermetallic structure, which is the most compliant metal in the
stack, will consequently absorb the contraction-induced strain and
thus have an even higher stress state as a result.
[0008] Fortunately, the present invention recognizes that contrary
to previous methods, it is possible to anneal the metal stacks
prior to ILD deposition in 0.25.mu. semiconductors, when only the
substrate, and not the ILD, constrains the aluminum in the stacks.
As recognized by the present invention, the consequence is that the
likelihood of void formation in the interconnect lines is reduced,
thereby improving 0.25.mu. chip reliability.
BRIEF SUMMARY OF THE INVENTION
[0009] A method is disclosed for making a semiconductor chip having
electrically conductive interconnect lines. The method includes
providing at least one substrate, and establishing at least one
predetermined pattern of electrically conductive interconnect lines
on the substrate. In accordance with the present invention, prior
to depositing a dielectric layer between the interconnect lines,
the lines are annealed.
[0010] In a preferred embodiment, each line establishes a stack
including at least one layer having aluminum therein and at least
one layer having titanium therein, and an alloy of titanium and
aluminum is formed during the annealing step. Preferably, the
annealing step is undertaken by heating the electrically conductive
lines to a temperature of between three hundred fifty degrees
Celsius and four hundred fifty degrees Celsius (350.degree.
C.-450.degree. C.) for a period of between ten minutes and ninety
minutes. Moreover, the electrically conductive lines are exposed to
one or more annealing gases, including nitrogen and hydrogen,
during the annealing step. In one preferred embodiment, the ILD is
TEOS that is deposited by directing TEOS onto the lines while
simultaneously removing excess TEOS by sputtering. A chip made
according to the present method, and a computing device
incorporating the chip, are also disclosed.
[0011] In another aspect, a semiconductor chip includes at least
one substrate and at least one predetermined pattern of aluminum
lines supported by the substrate, with adjacent lines being
separated by distances equal to or less than about three-eighths of
a micron. An alloy of aluminum and titanium is on the lines, with
the alloy (TiAl.sub.3) having been reacted prior to insulating the
lines from each other.
[0012] In still another aspect, a method for making a semiconductor
chip includes establishing plural electrically conductive lines on
at least one substrate. At least first lines are separated from
second lines by distances equal to or less than three-eighths of a
micron. The method further includes reacting a metal alloy on the
lines, and, after reacting the alloy, depositing a dielectric
between at least two lines that are adjacent each other. With this
method, the dielectric does not constrain the lines during the
reacting step.
[0013] Other features of the present invention are disclosed or
apparent in the section entitled: "DETAILED DESCRIPTION OF THE
INVENTION."
BRIEF DESCRIPTION OF DRAWINGS
[0014] For fuller understanding of the present invention, reference
is made to the accompanying drawing in the following detailed
description of the Best Mode of Carrying Out the Present Invention.
In the drawings:
[0015] FIG. 1 is a flow chart of the present process for making a
0.25.mu. technology semiconductor chip;
[0016] FIG. 2 is a schematic diagram of the substrate showing the
chip after conductor line stack formation;
[0017] FIG. 3 is a schematic cross-sectional diagram of the
substrate showing the chip after ILD deposition/etching,
schematically showing a computing device that incorporates the
chip; and
[0018] FIG. 4 is a schematic diagram of a high density plasma gap
fill deposition chamber.
[0019] Reference numbers refer to the same or equivalent parts of
the present invention throughout the several figures of the
drawing. In the description, the terms "vertical" and "horizontal"
refer to the orientations of the figures shown, for purposes of
disclosure, and do not necessarily refer to the orientation of the
present wafer once the wafer is embodied in a computing device.
DETAILED DESCRIPTION OF THE INVENTION
[0020] Referring initially to FIGS. 1 and 2, the process of the
present invention in producing 0.25.mu. technology computer chips
can be understood. Commencing at block 10 in FIG. 1 and as shown in
FIG. 2, plural stacks 12 are formed on a substrate 14. Each stack
12 is a metallic, electrically-conductive stack that defines a
respective interconnect line for an integrated circuit chip,
generally designated 16. The chip 16 can establish an integrated
circuit such as a microprocessor or a flash memory chip (e.g., an
electrically programmable memory (EPROM)) for use in the computer
arts. Although only two stacks 12 are shown for clarity of
disclosure, it is to be understood that more than two stacks
typically are formed on the substrate 14.
[0021] Preferably, the substrate 14 includes a semiconductor such
as silicon. Also, the substrate 14 can include a number of devices,
such as metal oxide silicon field effect transistor (MOSFET)
devices, that are electrically connected to one or more of the
stacks 12 via connector plugs.
[0022] In the preferred embodiment, each stack 12 includes a
respective lower titanium layer 18 abutting the substrate 14, an
upper titanium layer 20 parallel to and spaced from the lower
titanium layer 18, and an aluminum layer 22 sandwiched
therebetween. The titanium layers can be titanium or a titanium
alloy such as titanium nitride. It is to be understood that greater
or fewer layers can be provided. In a preferred embodiment, the
aluminum layer 22 is made of aluminum or an aluminum alloy
including aluminum and from 0.1% to about 10% by weight of one or
more of copper, nickel, zinc, gold, titanium, indium, chromium,
silver, palladium, and platinum.
[0023] The stacks are patterned on the wafer substrate 14 in
accordance with means known in the art, e.g., by depositing the
various metallic layers as films, covering the films with a mask,
and then directing ultraviolet light against the exposed portions
of the films. After lithographic patterning, chemical etching is
used to remove portions of metal not in the pattern to establish
the predetermined pattern of aluminum conductive lines of the chip
16, as shown in FIG. 2.
[0024] As can be appreciated in reference to FIG. 2, the chip 16 a
so-called "quarter micron chip", in that the distance 6 between
adjacent stacks 12 is about equal to or less than three-eighths of
a micron (0.375.mu.).
[0025] Moving to block 24 in FIG. 1, after forming the stacks 12,
the stacks 12 are annealed to form an intermetallic the stacks 12,
with an alloy structure 25 being formed at the interface between
each layer of aluminum and a layer of titanium (only a single alloy
structure 25 shown for clarity of disclosure). In the preferred
embodiment, the metal alloy is an alloy of aluminum and titanium,
and more specifically is TiAl.sub.3. Preferably, the annealing at
block 24 is undertaken by heating the stacks 12 to a temperature of
between three hundred fifty degrees Celsius and four hundred fifty
degrees Celsius (350.degree. C.-450.degree. C.) for a period of
between ten minutes and ninety minutes. Also, during the annealing
step the stacks 12 are exposed to one or more annealing gases,
preferably nitrogen at a flow rate of between eleven standard
liters per minute and fourteen standard liters per minute (11.0
slm-14.0 slm) and hydrogen at a flow rate of between one standard
liter per minute and two standard liters per minute (1.0 slm-2.0
slm).
[0026] After annealing, the chip 16 is cooled, during which time
the TiAl.sub.3 contracts. Accordingly, as provided by the present
invention the TiAl.sub.3, which would otherwise form during ILD
deposition and contract during the subsequent cool down when the
stacks 12 are constrained by the ILD, is instead formed prior to
ILD deposition, thus permitting the aluminum in the stacks 12 to
absorb contraction from the TiAl.sub.3 before the stacks 12 are
constrained by the ILD. This reduces the likelihood that voids will
undesirably form in the interconnect lines of the chip 16.
[0027] Moving to block 26 of FIG. 1 and referring to FIG. 3, an
interlayer dielectric (ILD) 28 is deposited between the stacks 12
to insulate the stacks 12.
[0028] While the present invention envisions using any appropriate
high density plasma (HDP) ILD such as silane, in the preferred
embodiment the ILD used is tetraethoxy silane (TEOS), to avoid the
production of free hydrogen that could otherwise embrittle the
aluminum.
[0029] Accordingly, to understand the preferred embodiment
cross-reference is made to FIGS. 3 and 4. An HDP chamber 30 (FIG.
4) is enclosed by a wall 32. A support 34 is disposed in the
chamber 30, and the support 34 may hold an e-chuck 36. One or more
wafers or substrates 22 are in turn disposed on the e-chuck 36.
[0030] To provide for depositing ILD on the wafer 22, a TEOS inlet
38 and an oxygen inlet 40 are associated with the chamber wall 32
to respectively direct TEOS and oxygen into the chamber 30, and a
source power lead 42 is likewise associated with the chamber 30. In
the preferred embodiment, TEOS is directed into the chamber 30 at a
rate ranging from one half milliliter per minute to three
milliliters per minute (0.5 mL/min-3.0 mL/min). In contrast, oxygen
is directed into the chamber 30 at a rate ranging from ten standard
cubic centimeters per minute to fifty standard cubic centimeters
per minute (10 SCCM-50 SCCM). The pressure within the chamber 30 is
maintained between one milliTorr and three Torr (1 mTorr-3 Torr),
and the source power applied to the chamber 30 is between five
hundred watts and five thousand watts (500 w-5000 w).
[0031] To provide for simultaneous sputtering of TEOS while the
TEOS is being deposited, an etchant inlet 44 is associated with the
wall 32 to port a gaseous sputtering agent, preferably argon, into
the chamber 30. Also, a bias power lead 46 is connected to the
e-chuck 36, and bias power is maintained at about three thousand
watts (3000 w).
[0032] If desired, both the annealing step and the subsequent ILD
deposition step can be undertaken in the chamber 30. If the
annealing step is to be undertaken in the chamber 30, nitrogen and
hydrogen inlets (not shown) are provided in the chamber 30.
[0033] The completion of the chip 16 may proceed in any such manner
as is required by its design. The resulting chip 16 can be
incorporated into a computing device 50 (FIG. 3), e.g., a computer,
digital camera, wireless telephone, or hand held computer, for use
by the computing device 50.
[0034] The principles of the present invention are equally
applicable to a wide range of semiconductor and integrated circuit
design and manufacture regimens, including but not necessarily
limited to the production of non-volatile memory devices. All such
implementations are specifically contemplated by the principles of
the present intention.
[0035] The present invention has been particularly shown and
described with respect to certain preferred embodiments and
features thereof. However, it should be readily apparent to those
of ordinary skill in the art that various changes and modifications
in form and detail may be made without departing from the spirit
and scope of the inventions as set forth in the appended claims, in
which reference to an element in the singular is not intended to
mean "one and only one" unless explicitly so stated, but rather
"one or more". The inventions illustratively disclosed herein may
be practiced without any element which is not specifically
disclosed herein.
* * * * *