U.S. patent application number 09/484412 was filed with the patent office on 2002-03-07 for selective deposition process for passivating top interface of damascene-type cu interconnect lines.
Invention is credited to Besser, Paul R., Erb, Darrell M., Lopatin, Sergey.
Application Number | 20020027261 09/484412 |
Document ID | / |
Family ID | 23924072 |
Filed Date | 2002-03-07 |
United States Patent
Application |
20020027261 |
Kind Code |
A1 |
Besser, Paul R. ; et
al. |
March 7, 2002 |
Selective Deposition Process For Passivating Top Interface Of
Damascene-Type Cu Interconnect Lines
Abstract
The reliability, electromigration resistance, adhesion, and
electrical contact resistance of planarized, in-laid metallization
patterns, e.g., of copper, are enhanced by a process comprising
selectively depositing on the planarized, upper surfaces of the
metallization features at least one thin layer comprising at least
one passivant element for the metal of the features, reacting the
at least one passivant element to chemically reduce any deleterious
oxide layer present at the upper surfaces of the metallization
features, and diffusing the at least one passivant element for a
distance below the upper surface to form a passivated top
interface. The passivated top interfaces advantageously exhibit
reduced electromigration and improved adhesion to overlying
metallization with lower ohmic contact resistance. Planarization,
as by CMP, may be performed subsequent to reaction/diffusion to
remove any elevated, reacted and/or unreacted portions of the at
least one thin layer. The invention finds particular utility in
"back-end" metallization processing of high-density integrated
circuit semiconductor devices having sub-micron dimensioned
metallization features.
Inventors: |
Besser, Paul R.; (Austin,
TX) ; Erb, Darrell M.; (Los Altos, CA) ;
Lopatin, Sergey; (Santa Clara, CA) |
Correspondence
Address: |
MCDERMOTT WILL & EMERY
600 13TH STREET, N.W.
WASHINGTON
DC
20005-3096
US
|
Family ID: |
23924072 |
Appl. No.: |
09/484412 |
Filed: |
January 18, 2000 |
Current U.S.
Class: |
257/584 ;
257/626; 257/645; 257/678; 257/927; 257/E21.582; 257/E21.583 |
Current CPC
Class: |
H01L 2924/0002 20130101;
H01L 2924/0002 20130101; H01L 2924/00 20130101; H01L 21/76867
20130101; H01L 21/7684 20130101; H01L 21/76883 20130101; H01L
21/76849 20130101; H01L 23/53233 20130101; H01L 21/76886
20130101 |
Class at
Publication: |
257/584 ;
257/626; 257/645; 257/678; 257/927 |
International
Class: |
H01L 021/20 |
Claims
What is claimed is:
1. A method of manufacturing an electrical device, which method
comprises the sequential steps of: (a) providing a substrate
including at least one damascene-type, metal feature in-laid in the
exposed, upper surface of a layer of dielectric material overlying
at least a portion of said substrate, the at least one metal
feature including an upper, exposed surface substantially co-planar
with said upper surface of said layer of dielectric material; (b)
selectively depositing on said exposed upper surface of said at
least one metal feature at least one layer comprising at least one
metallic passivant element for passivating said upper surface of
said at least one metal feature; and (c) effecting reaction between
at least a portion of said at least one layer comprising at least
one metallic passivant element and said upper surface of said at
least one metal feature to form a passivating layer thereat,
whereby electromigration of the metal of said at least one metal
feature is minimized or substantially prevented.
2. The method as in claim 1, further comprising the step of: (d)
selectively removing any elevated, remaining reacted and/or
unreacted portion(s) of said at least one layer comprising at least
one metallic passivant element which extend(s) above said upper
surface of said layer of dielectric material, thereby making said
upper surface of said at least one metal feature substantially
co-planar with said upper surface of said dielectric layer.
3. The method as in claim 1, wherein said electrical device
comprises a semiconductor integrated circuit device, and: step (a)
comprises providing as said substrate a semiconductor wafer of
monocrystalline silicon (Si) or gallium arsenide (GaAs) having a
major surface, said dielectric layer is formed over at least a
portion of said major surface, and said at least one
damascene-type, in-laid metal feature comprises a plurality of
features of different widths and/or depths for providing vias,
interlevel metallization, and/or interconnection lines of at least
one active device region or component formed on or within said
semiconductor wafer.
4. The method as in claim 3, wherein: said metal of said at least
one in-laid metal feature is unalloyed copper (Cu).
5. The method as in claim 4, wherein: step (b) comprises
selectively depositing at least one layer comprising at least one
metallic passivant element capable of chemically reducing any
copper oxide present on said upper surface of said at least one Cu
metal feature.
6. The method as in claim 5, wherein: step (b) comprises
selectively depositing at least one layer comprising at least one
metallic passivant element selected from the group consisting of:
magnesium (Mg), titanium (Ti), tantalum (Ta), cobalt (Co), nickel
(Ni), palladium (Pd), and chromium (Cr).
7. The method as in claim 6, wherein: said at least one metallic
passivant element is Mg.
8. The method as in claim 5, wherein: step (b) comprises
selectively depositing said at least one layer comprising said at
least one metallic passivant element by electroless deposition or
chemical vapor deposition (CVD).
9. The method as in claim 5, comprising: performing step (c)
substantially simultaneously with step (b).
10. The method as in claim 9, comprising: performing step (c) at
ambient temperature.
11. The method as in claim 5, comprising: performing step (c) after
step (b) by annealing at an elevated temperature in an inert
atmosphere.
12. The method as in claim 3, further comprising the step of: (d)
selectively removing any elevated, remaining reacted and/or
unreacted portion(s) of said at least one layer comprising at least
one metallic passivant element which extend(s) above said upper
surface of said layer of dielectric material, thereby making said
upper surface of said at least one metal feature substantially
co-planar with said upper surface of said dielectric layer.
13. The method as in claim 12, wherein: step (d) comprises
selectively removing by etching.
14. The method as in claim 12, wherein: step (d) comprises
selectively removing by chemical-mechanical polishing (CMP).
15. The method as in claim 1, wherein: step (a) for providing said
substrate including at least one damascene-type, in-laid metal
feature comprises the preliminary steps of: i. forming a dielectric
layer on a surface of a substrate, said dielectric layer having an
exposed, upper surface; ii. forming at least one recess in said
exposed, upper surface of said dielectric layer; iii. depositing a
metal layer filling the at least one recess and extending over said
upper surface of said dielectric layer; iv. removing the portion(s)
of the metal layer extending over said upper surface of said
dielectric layer; and v. removing any excess thickness portion(s)
of the metal layer filling the at least one recess which extend(s)
above said upper surface of said dielectric layer, thereby making
the upper, exposed surface of said at least one in-laid metal
feature substantially co-planar with said upper surface of said
dielectric layer.
16. The method as in claim 15, wherein: preliminary step v.
comprises planarizing by chemical-mechanical polishing (CMP).
17. A method of manufacturing a semiconductor integrated circuit
device, which method comprises the sequential steps of: (a)
providing a substrate comprising a semiconductor wafer of
monocrystalline Si or GaAs and having a major surface, a dielectric
layer formed on at least a portion of said major surface and having
an exposed, upper surface, at least one damascene-type, unalloyed
Cu metal feature in-laid in said exposed, upper surface of said
dielectric layer, the at least one Cu metal feature including an
exposed, upper surface substantially co-planar with said exposed,
upper surface of said dielectric layer; (b) selectively depositing
at least one layer comprising at least one metallic passivant
element for said Cu metal feature on said upper surface of said at
least one Cu metal feature, said at least one metallic passivant
element being capable of chemically reducing any copper oxide
present on said upper surface of said at least one metal feature
and selected from the group consisting of: magnesium (Mg), titanium
(Ti), tantalum (Ta), cobalt (Co), nickel (Ni), palladium (Pd), and
chromium (Cr); and (c) effecting reaction between at least a
portion of said at least one layer comprising at least one metallic
passivant element and said upper surface of said at least one Cu
metal feature to form a passivating layer thereat, whereby
electromigration of Cu atoms from said at least one Cu metal
feature is minimized or substantially prevented.
18. The method as in claim 17, wherein: step (b) comprises
selectively depositing said at least one layer comprising at least
one metallic passivant element by electroless deposition or
chemical vapor deposition (CVD); and step (c) is performed
substantially simultaneously with step (b) at ambient temperature
or subsequent to step (b) by annealing at an elevated temperature
in an inert atmosphere.
19. The method as in claim 17, farther comprising the step of: (d)
selectively removing any elevated, remaining reacted and/or
unreacted portion(s) of said at least one layer comprising at least
one metallic passivant element which extend(s) above said upper
surface of said layer of dielectric material, thereby making said
upper surface of said at least one Cu metal feature substantially
co-planar with said upper surface of said dielectric layer.
20. The method as in claim 17, wherein: step (a) comprises
providing a semiconductor wafer having a dielectric layer on a
major surface thereof which comprises a plurality of in-laid,
unalloyed Cu metal features of different widths and/or depths for
providing vias, inter-level metallization, and/or interconnection
lines of at least one active device region or component formed on
or within said semiconductor wafer.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application contains subject matter related to subject
matter disclosed in co-pending U.S. patent application Ser. No.
09/132,282, filed on Aug. 11, 1998 and Ser. No. 09/225,546, filed
on Jan. 5, 1999.
FIELD OF THE INVENTION
[0002] The present invention relates to electrical devices, e.g.,
semiconductor integrated circuit devices, having in-laid (
"damascene"-type) metallization patterns, e.g., interconnection
lines, etc., and to a method for minimizing, or substantially
preventing, deleterious electromigration of the metallic element(s)
of the metallization pattern. More specifically, the present
invention relates to semiconductor devices comprising copper (Cu)
interconnection patterns and is applicable to manufacture of high
speed integrated circuits having sub-micron dimensioned design
features and high electrical conductivity interconnect
structures.
BACKGROUND OF THE INVENTION
[0003] The present invention relates to a method for forming metal
films as part of metallization processing of particular utility in
the manufacture of electrical and electronic devices, e.g., circuit
boards and semiconductor integrated circuits, and is especially
adapted for use in processing employing "in-laid" or
"damascene"-type technology.
[0004] The escalating requirements for high density and performance
associated with ultra-large scale integration (ULSI) semiconductor
device wiring are difficult to satisfy in terms of providing
sub-micron-sized (e.g., 0.18 .mu.m and under), low
resistance-capacitance (RC) time constant metallization patterns,
particularly wherein the sub-micron-sized metallization features,
such as vias, contact areas, lines, etc. require grooves, trenches,
and other shaped openings or recesses having very high aspect
(i.e., depth-to-width) ratios due to microminiaturization.
[0005] Semiconductor devices of the type contemplated herein
typically comprise a semiconductor wafer substrate, usually of
doped monocrystalline silicon (Si) or, in some instances, gallium
arsenide (GaAs), and a plurality of sequentially formed interlayer
dielectrics and electrically conductive patterns formed therein
and/or therebetween. An integrated circuit is formed therefrom
containing a plurality of patterns of conductive lines separated by
inter-wiring spacings, and a plurality of interconnect lines, such
as bus lines, bit lines, word lines, and logic interconnect lines.
Typically, the conductive patterns of vertically spaced-apart
metallization layers or strata are electrically interconnected by a
vertically oriented conductive plug filling a via hole formed in
the inter-layer dielectric layer separating the layers or strata,
while another conductive plug filling a contact area hole
establishes electrical contact with an active device region, such
as a source/drain region of a transistor, formed in or on the
semiconductor substrate. Conductive lines formed in groove- or
trench-like openings in overlying inter-layer dielectrics extend
substantially parallel to the semiconductor substrate.
Semiconductor devices of such type fabricated according to current
technology may comprise five or more layers or strata of such
metallization in order to satisfy device geometry and
microminiaturization requirements.
[0006] Electrically conductive films or layers of the type
contemplated for use in e.g., "back-end" semiconductor
manufacturing technology for fabricating devices having multi-level
metallization patterns such as described supra, typically comprise
a metal such as titanium (Ti), tantalum (Ta), tungsten (W),
aluminum (Al), chromium (Cr), nickel (Ni), cobalt (Co), silver
(Ag), gold (Au), copper (Cu) and their alloys. In use, each of the
enumerated metals presents advantages as well as drawbacks. For
example, Al is relatively inexpensive, exhibits low resistivity,
and is relatively easy to etch. However, in addition to being
difficult to deposit by lower cost, lower temperature, more rapid
"wet" type technology such as electrodeposition, step coverage with
Al is poor when the metallization features are scale down to
sub-micron size, resulting in decreased reliability of
interconnections, high current densities at certain locations, and
increased electro-migration. In addition, certain low dielectric
constant materials, e.g., polyimides, when employed as dielectric
inter-layers, create moisture/bias reliability problems when in
contact with Al.
[0007] Copper (Cu) and Cu-based alloys are particularly attractive
for use in large scale integration (LSI), very large-scale
integration (VLSI), and ultra-large scale (ULSI) semiconductor
devices requiring multi-level metallization systems for "back-end"
processing of the semiconductor wafers on which the devices are
based. Cu- and Cu alloy-based metallization systems have very low
resistivities, i.e., significantly lower than that of W and even
lower than those of previously preferred systems utilizing Al and
its alloys, as well as a higher (but not complete) resistance to
electromigration. Moreover, Cu and its alloys enjoy a considerable
cost advantage over a number of the above-enumerated metals,
notably Ag and Au. Also, in contrast to Al and the refractory-type
metals (e.g., Ti, Ta, and W), Cu and its alloys can be readily
deposited at low temperatures in good quality, bright layer form by
well-known "wet" plating techniques, such as electroless and
electroplating techniques, at deposition rates fully compatible
with the requirements of device manufacturing throughput.
[0008] Electroless plating of Cu generally involves the controlled
auto-catalytic deposition of a continuous film of Cu or an alloy
thereof on a catalytic surface by the interaction of at least a
Cu-containing salt and a chemical reducing agent contained in a
suitable solution, whereas electroplating comprises employing
electrons supplied to an electrode (comprising the surface(s) to be
plated) from an external source (i.e., a power supply) for reducing
Cu ions in solution and depositing reduced Cu metal atoms on the
plating surface(s). In either case, a nucleation/seed layer is
required for catalysis and/or deposition on the types of substrates
contemplated herein. Finally, while electroplating requires a
continuous nucleation/seed layer, very thin and discontinuous
islands of a catalytic metal may be employed with electroless
plating.
[0009] As indicated above, a commonly employed method for forming
"in-laid" metallization patterns as are required for "back-end"
metallization processing of semiconductor wafers employs
"damascene"-type technology. Generally, in such processing
methodology, a recess (i.e., an opening) for forming, e.g., a via
hole in a dielectric layer for electrically connecting vertically
separated metallization layers, or a groove or trench for a
metallization line, is created in the dielectric layer by
conventional photolithographic and etching techniques, and filled
with a selected metal. Any excess metal overfilling the recess
and/or extending over the surface of the dielectric layer is then
removed by, e.g., chemical-mechanical polishing (CMP), wherein a
moving pad is biased against the surface to be polished/planarized,
with the interposition of a slurry containing abrasive particles
(and other ingredients) therebetween.
[0010] A variant of the above-described technique, termed "dual
damascene" processing, involves the formation of an opening
comprising a lower contact or via hole section in communication
with an upper groove or trench section, which opening is filled
with a conductive material, typically a metal, to simultaneously
form a conductive via plug in electrical contact with a conductive
line.
[0011] Referring now to FIG. 1, schematically shown therein in
simplified cross-sectional view, is a conventional damascene-type
processing sequence employing relatively low cost, high
manufacturing throughput plating and CMP techniques for forming
recessed "back-end" metallization patterns (illustratively of
Cu-based metallurgy but not limited thereto) in a semiconductor
device formed in or on a semiconductor wafer substrate 1. In a
first step, the desired arrangement of conductors is defined as a
pattern of recesses 2 such as via holes, grooves, trenches, etc.
formed (as by conventional photolithographic and etching
techniques) in the surface 4 of a dielectric layer 3 (e.g., a
silicon oxide and/or nitride or an organic polymeric material)
deposited or otherwise formed over the semiconductor substrate 1.
In a second step, a layer of Cu or Cu-based alloy 5 is deposited by
conventional plating techniques, e.g., electroless or
electroplating techniques, to fill the recesses 2. In order to
ensure complete filling of the recesses, the Cu-containing layer 5
is deposited as a blanket (or "overburden") layer of excess
thickness t so as to overfill the recesses 2 and cover the upper
surface 4 of the dielectric layer 3. Next, the entire excess
thickness t of the metal overburden layer 5 over the surface of the
dielectric layer 3 is removed by a CMP process utilizing an alumina
(Al.sub.2O.sub.3)-based slurry, leaving metal portions 5' in the
recesses 2 with their exposed upper surfaces 6 substantially
co-planar with the surface 4 of the dielectric layer 3.
[0012] The above-described conventional damascene-type process
forms in-laid conductors 5' in the dielectric layer 3 while
avoiding problems associated with other types of metallization
patterning processing, e.g., blanket metal layer deposition,
followed by photolithographic masking/etching and dielectric gap
filling. In addition, such single or dual damascene-type processing
can be performed with a variety of other types of substrates, e.g.,
printed circuit boards, with and/or without intervening dielectric
layers, and with a plurality of metallization levels, i.e., five or
more levels.
[0013] A drawback associated with Cu-based "back-end" metallization
is the possibility of Cu diffusion into adjacent structures, e.g.,
an underlying semiconductor substrate (typically Si) or a
dielectric layer, resulting in degradation of semiconductive or
insulative properties, as well as poor adhesion of the deposited Cu
or Cu alloy layer to various materials employed as dielectric
inter-layers, etc. As a consequence of these phenomena associated
with Cu-based metallurgy, it is generally necessary to provide an
adhesion promoting and/or diffusion barrier layer intermediate the
semiconductor substrate and the overlying Cu-based metallization
layer. Suitable materials for such adhesion/barrier layers include,
e.g., Ti, W, Cr, Ta, and TaN.
[0014] Another drawback associated with the use of Cu or Cu-based
metallurgy for "back-end" metallization processing of semiconductor
devices, results from the undesirable formation of copper oxide(s),
e.g., Cu.sub.2O, CuO, CuO.sub.2, etc., on the planarized Cu or
Cu-based alloy surfaces of the in-laid metallization features as a
result of oxidation, etc., due to the strong chemical oxidizing
agents conventionally included in CMP slurries for enhancing Cu
dissolution/removal rates or as a result of exposure of the freshly
abraded Cu-based surfaces to an oxidizing atmosphere, e.g., air or
oxygen. The thickness of the copper oxide layer can vary depending
upon the particular CMP processing conditions, e.g., stronger
oxidizing agents contained in the CMP slurry result in thicker
oxide layers, as does increased duration of exposure of freshly
abraded, post CMP Cu surfaces to oxidizing atmospheres, e.g.,
air.
[0015] Such copper oxide-containing layer(s) disadvantageously
increase contact resistance and reduce or prevent adhesion of
layers thereto, e.g., silicon nitride-based capping layers.
Moreover, the copper oxide layers are brittle, increasing the
likelihood of circuit disconnect or reduced conductivity due to
separation, as by peeling, of the copper oxide layer from conductor
layers in contact therewith. Yet another significant disadvantage
attributable to the presence of copper oxide at the interface
between adjacent electrical conductors results from the rapid
diffusion of Cu atoms and/or ions along the oxide layer. The latter
characteristic of copper oxide layers disadvantageously results in
enhanced material transport during electrical current flow and thus
increases the electromigration rate of Cu atoms and/or ions along
Cu-based conductor lines.
[0016] Electromigration occurs in extended runs or lengths of metal
conductor lines carrying significant currents. According to a
conventional theory for explaining the mechanism of
electromigration, the current flow within the conductor line can be
sufficient to result in movement of metal (Cu) atoms and/or ions
along the line via momentum transfer engendered by collision of the
metal (Cu) atoms and/or ions with energetic, flowing electrons. The
current flow also creates a thermal gradient along the conductor
length which increases the mobility of the metal ions and/or atoms.
As a consequence of the momentum transfer and the thermally
enhanced mobility, metal (Cu) atoms and/or ions diffuse in the
direction of the current flow, and metal loss at the source end of
the conductor eventually results in thinning of the conductor line.
The electromigration effect can continue until the conductor line
becomes so thin that it separates from the current input or forms
an open circuit, resulting in circuit (i.e., semiconductor chip)
failure. As this usually occurs over an extended period of
operation, the failure is often seen by the end-user.
[0017] As design rules for high integration density, high speed
semiconductor devices extend deeper into the sub-micron range,
e.g., about 0.18 .mu.m and under, e.g., about 0.15 .mu.m and below,
and the number of metallization levels increases, the reliability
of the "back-end" interconnection patterns and systems become
particularly critical for the obtainment of desired operating
characteristics and performance.
[0018] Thus, there exists a need for metallization process
methodology which avoids the above-mentioned drawbacks associated
with oxide layer formation, electromigration, etc., and which
enables formation of metallization members, e.g., interconnect and
routing lines, particularly of Cu or Cu-based alloys, having high
reliability, high product yield, improved electromigration
resistance, and high performance. In particular, there exists a
need for eliminating the problems associated with electromigration
and oxide layer formation resulting from CMP processing to form
"in-laid", "damascene-type" Cu-based metallization patterns.
Moreover, there exists a need for improved metallization processing
technology which is fully compatible with conventional process
flow, methodology, and throughput requirements in the manufacture
of integrated circuit semiconductor devices and other devices
requiring "in-laid" metallization patterns.
DISCLOSURE OF THE INVENTION
[0019] An advantage of the present invention is a method of
manufacturing an electrical or electronic device having highly
reliable, electromigration-resistant metallization patterns.
[0020] Another advantage of the present invention is a method of
manufacturing a semiconductor integrated circuit device having
highly reliable, electromigration-resistant Cu-based metallization
patterns.
[0021] Yet another advantage of the present invention is a method
of manufacturing "in-laid", "damascene"-type Cu-based metallization
patterns having improved reliability, high conductivity, and
improved electromigration resistance.
[0022] Still another advantage of the present invention is an
improved method of forming high-density, "in-laid" metallization
patterns by a "damascene"-type, CMP-based process which is fully
compatible with existing process methodology for forming integrated
circuit semiconductor devices and printed circuit boards.
[0023] Additional advantages and other features of the present
invention will be set forth in the description which follows and in
part will become apparent to those having ordinary skill in the art
upon examination of the following or will be learned from the
practice of the invention. The advantages of the present invention
may be realized and obtained as particularly pointed out in the
appended claims.
[0024] According to one aspect of the present invention, the
foregoing and other advantages are achieved in part by a method of
manufacturing an electrical device, the method comprising the
sequential steps of:
[0025] (a) providing a substrate including at least one
damascene-type, metal feature in-laid in the upper, exposed surface
of a layer of dielectric material overlying at least a portion of
the substrate, the at least one metal feature including an upper,
exposed surface substantially co-planar with the upper surface of
the layer of dielectric material;
[0026] (b) selectively depositing on the exposed upper surface of
the at least one metal feature at least one layer comprising at
least one metallic passivant element for passivating the upper
surface of the at least one metal feature; and
[0027] (c) effecting reaction between at least a portion of the at
least one layer comprising at least one metallic passivant element
and the upper surface of the at least one metal feature to form a
passivating layer thereat, whereby electromigration of the metal of
the at least one metal feature is minimized or substantially
prevented.
[0028] According to embodiments of the present invention, the
method further comprises the step of:
[0029] (d) selectively removing any remaining reacted and/or
unreacted portion(s) of the at least one layer comprising at least
one metallic passivant element which extend(s) above the upper
surface of the layer of dielectric material, thereby making the
upper surface of the at least one in-laid metal feature
substantially co-planar with the upper surface of the layer of
dielectric material.
[0030] In accordance with embodiments of the present invention, the
electrical device comprises a semiconductor integrated circuit
device, and step (a) comprises providing as the substrate a
semiconductor wafer of monocrystalline silicon (Si) or gallium
arsenide (GaAs) having a major surface, the dielectric layer is
formed over at least a portion of the major surface, the at least
one damascene-type, in-laid metal feature comprises a plurality of
features of different widths and/or depths for providing vias,
inter-level metallization, and/or interconnection lines of at least
one active device region or component formed on or within the
semiconductor wafer, and the metal of the at least one in-laid
metal feature is unalloyed copper (Cu); and step (b) comprises
selectively depositing, as by electroless deposition or chemical
vapor deposition (CVD), at least one layer comprising at least one
metallic passivant element capable of chemically reducing any
copper oxide present on the upper surface of the at least one Cu
metal feature, the at least one metallic passivant element being
selected from the group consisting of: magnesium (Mg), titanium
(Ti), tantalum (Ta), cobalt (Co), nickel (Ni), palladium (Pd) and
chromium (Cr).
[0031] In embodiments according to the present invention, step (c)
is performed substantially simultaneously with step (b), e.g., at
ambient temperatures; whereas according to other embodiments of the
present invention, step (c) is performed after step (b), as by
annealing in an inert atmosphere; and step (d) comprises
selectively removing, as by etching or chemical-mechanical
polishing (CMP), any remaining elevated, reacted and/or unreacted
portion(s) of the layer comprising at least one metallic passivant
element which extend(s) above the upper surface of the layer of
dielectric material, thereby making the upper surface of the at
least one in-laid metal feature substantially co-planar with the
upper surface of the dielectric layer.
[0032] According to further embodiments of the present invention,
step (a) for providing the substrate including at least one
damascene-type, in-laid metal feature comprises the preliminary
steps of:
[0033] i. forming a dielectric layer on a surface of a substrate,
the dielectric layer having an exposed, upper surface;
[0034] ii. forming at least one recess in the exposed, upper
surface of the dielectric layer;
[0035] iii. depositing a metal layer filling the at least one
recess and extending over the upper surface of the dielectric
layer;
[0036] iv. removing the portion(s) of the metal layer extending
over the upper surface of the dielectric layer; and
[0037] v. removing (e.g., by CMP) any excess thickness portion(s)
of the metal layer filling the at least one recess which extend(s)
above the upper surface of the dielectric layer, thereby making the
upper, exposed, upper surface of the at least one in-laid metal
feature substantially co-planar with the exposed, upper surface of
the dielectric layer.
[0038] According to another aspect of the present invention, a
method of manufacturing a semiconductor integrated circuit device
comprises the sequential steps of:
[0039] (a) providing a substrate comprising a semiconductor wafer
of monocrystalline Si or GaAs and having a major surface, a
dielectric layer formed on at least a portion of the major surface
and having an exposed, upper surface, at least one damascene-type,
unalloyed Cu metal feature in-laid in the exposed, upper surface of
the dielectric layer, the at least one Cu metal feature including
an exposed, upper surface substantially co-planar with the exposed,
upper surface of the dielectric layer;
[0040] (b) selectively depositing at least one layer comprising at
least one metallic passivant element for the Cu metal feature on
the upper surface of the at least one Cu metal feature, the at
least one metallic passivant element being capable of chemically
reducing any copper oxide present on the upper surface of the at
least one metal feature and selected from the group consisting of:
magnesium (Mg), titanium (Ti), tantalum (Ta), cobalt (Co), nickel
(Ni), palladium (Pd), and chromium (Cr); and
[0041] (c) effecting reaction between at least a portion of the at
least one layer comprising at least one metallic passivant element
and the upper surface of the at least one Cu metal feature to form
a passivating layer thereat, whereby electromigration of Cu atoms
and/or ions from the at least one Cu metal feature is minimized or
substantially prevented.
[0042] According to embodiments of the present invention:
[0043] step (a) comprises providing a semiconductor wafer having a
dielectric layer on a major surface thereof which comprises a
plurality of in-laid, unalloyed Cu metal features of different
widths and/or depths for providing vias, inter-level metallization,
and/or interconnection lines of at least one active device region
or component formed on or within the semiconductor wafer;
[0044] step (b) comprises selectively depositing the at least one
layer comprising at least one metallic passivant element by
electroless deposition or chemical vapor deposition (CVD); and
[0045] step (c) is performed substantially simultaneously with step
(b) at ambient temperature or subsequent to step (b) by annealing
at an elevated temperature in an inert atmosphere.
[0046] According to still further embodiments of the present
invention, the method comprises the further step of:
[0047] (d) selectively removing any elevated, remaining reacted
and/or unreacted portion(s) of the at least one layer comprising at
least one metallic passivating element which extend(s) above the
upper surface of the layer of dielectric material, thereby making
the upper surface of the at least one in-laid, Cu metal feature
substantially co-planar with the upper surface of the dielectric
layer.
[0048] Additional advantages of the present invention will readily
become apparent to those skilled in the art from the following
detailed description, wherein only the preferred embodiment of the
present invention is shown and described, simply by way of
illustration of the best mode contemplated for carrying out the
method of the present invention. As will be understood, the present
invention is capable of other and different embodiments, and its
several details are capable of modification in various obvious
respects, all without departing from the present invention.
Accordingly, the drawing and description are to be regarded as
illustrative in nature, and not as limitative.
BRIEF DESCRIPTION OF THE DRAWINGS
[0049] The following detailed description of an embodiment of the
present invention can best be understood when read in conjunction
with the following drawings, in which like reference numerals are
employed throughout to designate similar features, wherein:
[0050] FIG. 1 illustrates, in simplified, cross-sectional schematic
form, a sequence of processing steps for forming a pattern of
damascene-type, in-laid Cu metallization features according to
conventional practices for manufacture of semiconductor integrated
circuit devices; and
[0051] FIG. 2 illustrates, in simplified cross-sectional schematic
form, a sequence of processing steps for selectively passivating
the upper surfaces, i.e., the top interfaces of the pattern of Cu
in-laid metallization features of FIG. 1 according to the inventive
methodology.
DESCRIPTION OF THE INVENTION
[0052] The present invention addresses and solves problems arising
from manufacturing electrical devices comprising in-laid
metallization patterns, e.g., semiconductor integrated circuit
devices, wherein, as part of the fabrication methodology, a
plurality of recesses formed in the surface of a dielectric layer
overlying a semiconductor substrate comprising at least one active
device region or component are filled with a metal, illustratively
unalloyed Cu, which is subject to electromigration when the device
is in use. More specifically, the present invention enables the
formation of in-laid metallization patterns, e.g., of Cu-based
metallurgy, in which the tendency for electromigration of the
principal metallic element or component is minimized or
substantially prevented, and which provide improved adhesion to,
and low contact resistance with, adjacent (e.g., overlying)
metallization patterns and/or levels in contact therewith.
[0053] The present invention enables the formation of in-laid
metallization patterns having passivated upper surfaces (top
interfaces) which have little or substantially no tendency for
promoting electromigration of atoms and/or ions of the principal
underlying metal component and provide improved adhesion with
overlying metallization by means of techniques which are fully
compatible with the requirements of automated manufacturing
technology and product throughput. Briefly stated, according to the
present invention, conventional damascene-type methodology (such as
illustrated in FIG. 1) is employed for forming an in-laid
metallization pattern in a dielectric layer overlying a suitable
substrate, e.g., a semiconductor wafer comprising at least one
active device region or component, by which processing a metal
material, e.g., unalloyed Cu, is utilized for filling the pattern
of recesses in the dielectric layer. Subsequent to planarization
processing, as by chemical-mechanical polishing (CMP), at least one
thin layer comprising at least one passivant element for the metal
material, e.g., Cu, is selectively deposited on the exposed, upper
surface(s) of the feature(s) of the metallization pattern, and
reaction between the at least one passivant element and the upper
surface(s) of the metal of the in-laid metallization feature(s) is
effected for selectively forming a passivating layer thereat, the
passivation reaction including reduction of any deleterious oxide
of the metal of the metallization feature(s) present at the upper
surface(s) thereof. The passivation reaction may occur
simultaneously with the selective deposition of the at least one
thin layer comprising at least one passivant element, i.e., at
ambient temperature, or alternatively, may occur subsequent to the
selective deposition, as by annealing at an elevated temperature in
an inert atmosphere. Any elevated, remaining reacted and/or
unreacted portion(s) of the at least one thin layer comprising at
least one passivant element remaining after reaction/passivation of
the upper surface(s), or top interface(s), of the metallization
feature(s) is (are) selectively removed, as by CMP, thereby making
the exposed, passivated upper surface(s), or top interface(s) of
the metallization pattern substantially co-planar with the exposed,
upper surface of the dielectric layer. By way of example, but not
limitation, a thin layer comprising magnesium (Mg) as passivant
element can readily reduce CuO.sub.2 typically present on the upper
surfaces of unalloyed Cu metallization features. In such instance,
the remaining reacted and/or unreacted portions of the passivant
layer removed by CMP comprise Mg and MgO.
[0054] An embodiment of the present invention will now be described
with reference to FIG. 2, which shows, in simplified,
cross-sectional, schematic fashion, an illustrative, but not
limitative, embodiment of the present invention comprising a
sequence of processing steps performed on a semiconductor wafer
substrate-based workpiece produced according to the process
sequence illustrated in FIG. 1, wherein similar reference numerals
are used throughout to denote similar features. As will be apparent
to one of ordinary skill in the art, the inventive process is
readily adapted for use in the manufacture of a variety of
electrical and electronic devices utilizing in-laid metallization
patterns, e.g., printed circuit boards and integrated circuit
semiconductor devices. It should also be recognized that the
process steps and structures described below do not necessarily
form a complete process flow for manufacturing such devices.
However, the present invention can be used in conjunction with
conventional technology currently employed in the art, e.g.,
integrated circuit fabrication methodology, and, consequently, only
so much of the commonly practiced process steps are included here
as are necessary for an understanding of the present invention. As
employed throughout the present disclosure and claims, the terms
"substrate" and/or "semiconductor wafer substrate" include, e.g., a
semiconductor substrate per se or an epitaxial layer formed on a
suitable semiconductor substrate. The expressions "passivant" and
"passivating element", as employed herein, refer to elements which
are capable of reaction with at least the surface of a metal of an
in-laid metallization feature and any oxide(s) of the metal present
thereat, as to form a top surface or top interface "passivation
layer", which according to the context of the present invention,
refers to an uppermost layer or strata of the metallization feature
which effectively reduces electromigration of atoms and/or ions of
the principal metallic component of the feature and provides good
adhesion and low ohmic electrical resistance with an overlying
metallization layer in contact therewith. Finally, the drawing
figures representing cross-sections of portions of a semiconductor
device during fabrication processing are not drawn to scale, but
instead are drawn as to best illustrate the features of the present
invention.
[0055] Referring now to the first view shown in FIG. 2, in a
preliminary step according to the present invention, a
semiconductor wafer substrate-based workpiece similar to that shown
in the third view of FIG. 1 is provided, having a desired in-laid
metallization pattern, comprising a semiconductor wafer substrate
1, a dielectric layer 3 overlying substrate 1 and having a pattern
of recesses 2 of different widths and/or depths formed in the
exposed, upper surface 4 thereof, and a layer 5 of a metal subject
to electro-migration, illustratively Cu, filling the recesses 2,
the exposed, upper surfaces 6 of the metal layer 5 being
substantially co-planar with the exposed, upper surface 4 of the
dielectric layer 3.
[0056] In the illustrated structure, semiconductor substrate 1
typically comprises a wafer of monocrystalline Si or GaAs, layer 3
comprises an insulative material typically utilized as an
inter-layer dielectric ("ILD"), i.e., an inorganic material such as
a silicon oxide, nitride, or oxynitride, or an organic-based or
derived material, such as parylene, benzocyclobutene (BCB), etc.
Recesses 2 formed in the upper, exposed surface 4 of dielectric
layer 3 are utilized for forming vias, inter-level metallization,
and/or interconnection routing of at least one active device region
or component formed on or within semiconductor wafer substrate 1
and typically include openings having high aspect (i.e.,
depth-to-width) ratios greater than one, with sub-micron or
micron-sized dimensions, i.e., widths of from about 0.08 to about
3.0 .mu.m and depths of from about 0.4 to about 2.0 .mu.m.
[0057] Referring now to the second view shown in FIG. 2, in a first
step according to the inventive methodology, at least one thin
layer 7 comprising at least one passivant element (e.g., Ni) for
the metal 5 (e.g., unalloyed Cu) of the in-laid metal feature(s) of
the metallization pattern is selectively deposited on the exposed,
upper surface 6 thereof, as by a selective electroless deposition
or chemical vapor deposition (CVD) technique. Selectivity of the
deposition towards the metal 5 of the metal features may be
obtained by use of suitable deposition bath composition in the case
of electroless deposition and by appropriate selection of
organo-metallic precursor gas(es) in the case of CVD. For example,
selective electroless deposition of a layer 7 comprising at least
one passivant element, for reducing deleterious oxides and
electromigration tendency of unalloyed Cu, e.g., chosen from the
group consisting of magnesium (Mg), titanium (Ti), tantalum (Ta),
cobalt (Co), nickel (Ni), palladium (Pd), and chromium (Cr), may be
obtained by appropriate use of an electroless deposition solution
comprising a boride, phosphide, or boride/palladium compound of the
metal to be selectively plated on the metal feature(s), whereas
selective CVD of the above-enumerated passivant elements may be
obtained by use of appropriate organo-metallic precursor gas(es).
By way of illustration, but not limitation, Ni be selectively
electrolessly plated on unalloyed Cu metal features from deposition
solutions comprising NiB, NiP or NiBPd, or selectively CVD
deposited on unalloyed Cu metal features by use of a Ni-based
organo-metallic precursor gas. Given the present disclosure and
objectives of the invention, suitable electroless deposition bath
compositions and/or organo-metallic precursor gases for use with
the other enumerated passivant elements can be determined for use
in a particular application.
[0058] According to an essential feature of the present invention,
the at least one passivant element contained in the at least one
thin layer 7 must be capable of chemically reducing any oxide(s) of
the metal 5 of the metallization feature(s) which are
disadvantageously present at the upper surface(s) 6 thereof, e.g.,
as a result of oxidation by oxidants present in the abrasive slurry
employed for the CMP planarization processing, or as a result of
exposure to air of the freshly abraded surfaces produced during the
CMP. By way of illustration, but not limitation, in the illustrated
case where unalloyed Cu (e.g., electroplated) metal 5 is utilized
for forming the metallization pattern, such deleterious copper
oxides include Cu.sub.2O, CuO, and CuO.sub.2. As a consequence of
the above requirement, the at least one thin layer 7 comprising the
at least one passivant element (e.g., Ni or Mg) must be of
sufficient thickness to provide substantially complete reduction of
the oxide layer as well as diffusion of the at least one passivant
element into the metal 5 of the metallization feature to a
predetermined minimum distance d.sub.min. below surface 6, thereby
establishing thereat a passivated surface layer 8, as shown in the
third view of FIG. 2. Passivated top surface (or top interface)
layer 8, according to the invention, forms a new top surface or top
interface for subsequent adherent, low ohmic resistance contact
with an overlying metallization level, while providing minimal, or
substantially no tendency for electromigration of the principal
metal 5 (e.g., Cu) of the metallization feature. Given the present
disclosure and objectives of the invention, appropriate thicknesses
for the at least one alloying element layer 7, as well as minimum
diffusion depth d.sub.min., can be determined and optimized for use
in a particular application.
[0059] Layer 7 can, depending, inter alia, upon the particular
metal 5 of the metallization pattern and choice and number of
passivant element(s), comprise a single layer including one
passivant element or two or more elements. Alternatively, layer 7
can comprise two or more overlying layers, each including one
passivant element. The latter alternative may be preferred when
co-deposition of multiple passivant elements in single layer form
is impractical or results in poor control of the relative amounts
of each passivant element.
[0060] According to another feature of the present invention,
reaction between the at least one passivant element contained in
the at least one thin layer 7 to chemically reduce any oxide(s)
present at the upper surface 6 of the metal feature(s) can,
depending upon the chemical reactivity between the particular
passivant element(s) and the particular oxides, occur substantially
simultaneously with the deposition of layer 7, i.e., at the ambient
temperature during deposition, or alternatively, subsequently
thereto at an elevated temperature, e.g., by annealing in an inert
atmosphere. By way of illustration, but not limitation, in the case
of a layer 7 of Ni as passivant element and unalloyed Cu as metal 5
of the metallization feature(s), copper oxide reduction may be
achieved substantially simultaneously with Ni deposition at ambient
temperatures of from about 20 to about 300.degree. C., whereas with
a layer 7 of a less reactive passivant element, such as Co,
annealing (in an inert atmosphere) at a temperature of from about
200 to about 450.degree. C. for from about 30 sec. to about 60 min.
is necessary to effect copper oxide reduction. In the former case
of reaction at ambient temperature, however, a subsequent annealing
treatment, as indicated in the third view of FIG. 2, may be
required for formation of diffused layer 8, whereas, in the latter
case, where reaction requires elevated temperature, reduction of
the copper oxides and formation of diffused layer 8 can occur
substantially simultaneously with diffusion of the passivant
element.
[0061] Referring now to the final view illustrated in FIG. 2,
elevated layer portions 7' which extend above the level of upper
surface 4 of dielectric layer 3, and composed of reacted and/or
unreacted portions of layer(s) 7 (e.g., comprising Mg and/or MgO)
may remain on or over passivating surface layer 8 at the upper
surface(s) of the metal features after completion of the reaction
and diffusion treatment(s). In the next step according to the
inventive methodology, any such remaining layer portion(s) 7' is
(are) selectively removed, e.g., by etching using an etchant
selective against the material of the dielectric layer 3 or by
chemical-mechanical planarization (CMP), thereby re-establishing
co-planarity of the upper surface 6 of the in-laid metal feature(s)
and the upper surface 4 of the dielectric layer 3. The
thus-produced, planarized, in-laid metallization pattern having
passivating layer 8 at the upper surfaces (top interfaces) 6
thereof for minimizing or substantially preventing electromigration
therefrom and therealong may then be subjected to further
"back-end" metallization processing, as by damascene-type
techniques, for forming adherent, low ohmic resistance electrical
contact with at least one additional overlying layer of
metallization.
[0062] The present invention thus provides a simple, convenient,
and reliable method for reducing, or substantially preventing,
deleterious electromigration of metal from in-laid metallization
patterns as well as improved adhesion and lower resistance
electrical contact thereto, by selectively depositing at least one
thin layer comprising at least one passivant element for the metal
of the metallization pattern, which at least one passivant element
(1) chemically reduces any deleterious oxide layer present at the
upper-surfaces of the metallization feature and (2) diffuses into
the upper surface thereof to form a passivated top interface. The
present invention enables the formation of extremely reliable
interconnect members and patterns, illustratively of Cu, but not
limited thereto, by providing a method for reliably reducing, or
substantially preventing deleterious electromigration, particularly
suitable for use in semiconductor "back-end" damascene-type
processing, and equally applicable to "dual-damascene"-type
processing.
[0063] The inventive methodology enjoys particular utility in the
manufacture of semiconductor devices having sub-micron dimensioned
metallization features and high aspect ratio openings. Moreover,
the inventive method can be practiced at manufacturing rates
consistent with the requirements for economic competitiveness, and
is fully compatible with conventional process flow for automated
manufacture of high-density integration semiconductor devices. In
addition, the invention is particularly well suited to the
manufacture of circuit boards and other types of electrical and
electronic devices and/or components.
[0064] In the previous description, numerous specific details are
set forth, such as specific materials, structures, reactants,
processes, etc. in order to provide a better understanding of the
present invention. However, the present invention can be practiced
without resorting to the details specifically set forth. In other
instances, well known processing materials and techniques have not
been described in detail in order not to unnecessarily obscure the
present invention.
[0065] Only the preferred embodiment of the present invention and
but a few examples of its versatility are shown and described in
the present disclosure. It is to be understood that the present
invention is capable of use in various other combinations and
environments and is susceptible of changes or modifications within
the scope of the inventive concept as expressed herein.
* * * * *