U.S. patent application number 09/768288 was filed with the patent office on 2001-07-19 for semiconductor device and manufacturing method thereof.
Invention is credited to Akiyama, Yukiharu, Anjoh, Ichiro, Hasebe, Akio, Kimoto, Ryosuke, Kudaishi, Tomoaki, Miyazaki, Chuichi, Nishi, Kunihiko, Nishimura, Asao, Shibamoto, Masanori, Tanaka, Hideki, Tsubosaki, Kunihiro.
Application Number | 20010008304 09/768288 |
Document ID | / |
Family ID | 13321622 |
Filed Date | 2001-07-19 |
United States Patent
Application |
20010008304 |
Kind Code |
A1 |
Miyazaki, Chuichi ; et
al. |
July 19, 2001 |
Semiconductor device and manufacturing method thereof
Abstract
A ball grid array type semiconductor package includes a
semiconductor chip formed with bonding pads, an elastomer bonded to
the semiconductor chip, a flexible wiring substrate bonded to the
elastomer and formed with wirings connected at one end of the
bonding pads of the semiconductor chip, a solder resist formed on
the main surface of the flexible wiring substrate and solder bump
electrodes connected to the other ends of the wirings. The
elastomer is bonded to the flexible wiring substrate on the side of
the tape, the solder resist is formed on the side of the wirings,
and the solder bump electrodes are connected with the wirings by
way of through holes formed in the solder resist.
Inventors: |
Miyazaki, Chuichi; (Tokyo,
JP) ; Akiyama, Yukiharu; (Tokyo, JP) ;
Shibamoto, Masanori; (Urawa-shi, JP) ; Kudaishi,
Tomoaki; (Tokyo, JP) ; Anjoh, Ichiro; (Tokyo,
JP) ; Nishi, Kunihiko; (Tokyo, JP) ;
Nishimura, Asao; (Tokyo, JP) ; Tanaka, Hideki;
(Sagamihara-shi, JP) ; Kimoto, Ryosuke; (Tokyo,
JP) ; Tsubosaki, Kunihiro; (Tokyo, JP) ;
Hasebe, Akio; (Tokyo, JP) |
Correspondence
Address: |
ANTONELLI TERRY STOUT AND KRAUS
SUITE 1800
1300 NORTH SEVENTEENTH STREET
ARLINGTON
VA
22209
|
Family ID: |
13321622 |
Appl. No.: |
09/768288 |
Filed: |
January 25, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09768288 |
Jan 25, 2001 |
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|
09449834 |
Nov 26, 1999 |
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09449834 |
Nov 26, 1999 |
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08822833 |
Mar 24, 1997 |
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5979547 |
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Current U.S.
Class: |
257/678 ;
257/E23.065; 257/E23.067; 257/E23.069 |
Current CPC
Class: |
H01L 2224/05554
20130101; H01L 2924/01015 20130101; H01L 2924/01006 20130101; H01L
2924/01013 20130101; H01L 2924/01078 20130101; H01L 2224/48472
20130101; H01L 2924/01005 20130101; H01L 24/50 20130101; H01L
2924/01082 20130101; H01L 2924/01023 20130101; H01L 2224/06136
20130101; H01L 2924/01014 20130101; H01L 2224/50 20130101; H01L
2224/0401 20130101; H01L 23/49827 20130101; Y10T 29/4913 20150115;
H01L 2924/014 20130101; H01L 2924/00011 20130101; H01L 2224/73215
20130101; Y10T 29/49169 20150115; H01L 24/45 20130101; H01L
2224/45124 20130101; H01L 2924/15311 20130101; H01L 24/48 20130101;
H01L 2224/48465 20130101; H01L 2924/01079 20130101; H01L 23/49816
20130101; H01L 23/4985 20130101; H01L 2924/01057 20130101; H01L
2224/85951 20130101; H01L 2924/0105 20130101; H01L 2224/04042
20130101; H01L 2924/01033 20130101; H01L 24/86 20130101; H01L
2924/00014 20130101; H01L 2924/01029 20130101; H01L 24/06 20130101;
H01L 2224/45015 20130101; H01L 2924/14 20130101; H01L 2224/45144
20130101; H01L 2224/45144 20130101; H01L 2924/00014 20130101; H01L
2224/45124 20130101; H01L 2924/00014 20130101; H01L 2224/45015
20130101; H01L 2924/20753 20130101; H01L 2224/45015 20130101; H01L
2924/00014 20130101; H01L 2924/20753 20130101; H01L 2924/00014
20130101; H01L 2224/05599 20130101; H01L 2924/00011 20130101; H01L
2924/01005 20130101; H01L 2924/00011 20130101; H01L 2924/01033
20130101 |
Class at
Publication: |
257/678 |
International
Class: |
H01L 023/02 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 22, 1996 |
JP |
8-66637 |
Claims
What is claimed is:
1. A semiconductor device comprising: a semiconductor chip having a
plurality of semiconductor elements and a plurality of external
terminals formed in a main surface thereof; an elastic layer
provided on the main surface of the semiconductor chip in a manner
to expose the plurality of external terminals; an insulating tape
provided on the elastic layer and having an opening to expose the
plurality of external terminals, the opening being defined by an
edge of the insulating tape; a plurality of leads provided on a
surface of the insulating tape, wherein each of the plurality of
leads has a first portion disposed on the insulating tape and a
second portion which extends across the edge of the insulating tape
and is in the opening of the insulating tape, each of the second
portions being electrically connected with a corresponding one of
the external terminals; and a plurality of bump electrodes formed
on the first portions of the plurality of leads and being
electrically connected to the plurality of leads, respectively,
wherein each of the plurality of leads includes a copper lead as
core material thereof, wherein the copper lead of each of the
plurality of leads has gold-plating applied on its surface and
wherein a length of the second portion of each of the plurality of
leads is longer than a straight line distance from the edge of the
insulating tape to the corresponding one of the external
terminals.
2. A semiconductor device according to claim 1, wherein no other
metallic material exists between the copper lead and the
gold-plating.
3. A semiconductor device according to claim 1, wherein the
plurality of leads are disposed between the elastic layer and the
insulating tape, and wherein the plurality of bump electrodes are
contacting the corresponding ones of the plurality of leads via
through holes formed in the insulating tape, respectively.
4. A semiconductor device according to claim 1, wherein each of the
plurality of leads is disposed to form a substantially straight
line pattern in a plane view and to form a bended pattern in a
sectional view.
5. A semiconductor device according to claim 1, wherein the
plurality of leads are disposed between the elastic layer and the
insulating tape.
6. A semiconductor device according to claim 5, wherein each of the
plurality of leads is disposed to form a substantially straight
line pattern in a plane view and to form a bended pattern in a
sectional view.
7. A semiconductor device according to claim 6, wherein the
plurality of bump electrodes are contacting the corresponding ones
of the plurality of leads via through holes formed in the
insulating tape, respectively.
8. A semiconductor device according to claim 7, wherein no other
metallic material exists between the copper lead and the
gold-plating.
9. A semiconductor device according to claim 5, wherein no other
metallic material exists between the copper lead and the
gold-plating.
Description
[0001] This is a continuation of U.S. Ser. No. 09/449,834, filed
Nov. 26, 1999, which, in turn, is a continuation of U.S. Ser. No.
08/822,833, filed Mar. 21, 1997, and the disclosures of which are
incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] The present invention concerns a semiconductor integrated
circuit device technique and, more in particular, it relates to a
useful technique to be applied to portable equipment, such as
portable telephones and handy type personal computers, for which
there is a strong trend toward reducing the size, the weight and
the thickness of the product.
[0003] Recently, a trend toward reducing the size, the weight and
the thickness of the product has become vigorous for electronic
equipment along with an improved function and performance. This is
largely due to a rapid increase in the use of personal equipment,
such as personal telephones or handy type personal computers in
recent years. Further, man-machine interface functions have been
increased in personally manipulated equipment, for which easy
handlability and operability have been considered increasingly
important. It is considered that the trend will become more and
more conspicuous in expected regular multimedia areas.
[0004] Under such circumstances, development for increasing the
density and the degree of integration of semiconductor chips has
progressed continuously, however the size and the number of
electrodes of the semiconductor chips have increased, while the
size of the packages have also increased rapidly. Accordingly,
narrowing of the pitch of terminal leads has been promoted for
facilitating the size reduction of the packages, which makes
mounting of the package more difficult.
[0005] In view of the above, it has been proposed in recent years
to provide high density packages with super-multiple pins having
the same area as that of the semiconductor chips, and such
packaging techniques are mentioned, for example, in various
publications, such as "Nikkei Microdevice" p 98-p 102, issued on
May 1, 1994,"Nikkei Microdevice" p 96-p 97, issued on Feb. 1, 1995
by Nikkei BPCO and "Electronic Material", p 22-p 28, issued on Apr.
1, 1995 (Heisei 7) by Kogyo Chosakai. One example of the structures
produced such packaging techniques, for example, as described in
FIG. 6 of the "Electronic Material" publication, has a package
structure in which a flexible wiring substrate is disposed by way
of an elastomer (elastic material) on the surface of a
semiconductor chip, leads on one end of wirings of the flexible
wiring substrate are electrically connected with bonding pads on
the surface of the semiconductor chip, and bump lands on the other
end of the wirings of the flexible wiring substrate are
electrically connected with the solder bumps.
[0006] The package structure has an outer size about equal to or
greater than that of a semiconductor chip by the size of a
protection frame optionally attached to the periphery of the chip,
for which a flexible wiring substrate formed with solder bumps is
used. The wiring pattern of the wiring substrate is made of a Cu
foil having a Au plating on one side, the top ends of which to be
connected with the pad of the chip constitute a lead pattern which
is only composed of Au as a result of etching the Cu foil. In this
structure, the flexible wiring substrate is bonded by an elastomer
on the surface of the semiconductor chip and then the Au leads are
connected with the bonding pads of the semiconductor chip.
SUMMARY OF THE INVENTION
[0007] In a study made by the present inventor of the package
structure as described above, the following problems were
recognized. For example, since the flexible wiring substrate in the
package structure described above has a structure typically
represented by a TCP (Tape Carrier Package) in which a Cu wiring
pattern is formed on the surface of a polyimide tape, and an
elastomer is formed to the wiring substrate on the side of the
wiring surface, it is difficult to mount the elastomer uniformly
and stably because of unevenness of the wiring pattern on the
flexible wiring substrate. That is, there exist such problems that
voids not filled with the elastomer are formed near both sides of
the protrusions of the wiring pattern upon coating or appending the
elastomer on the flexible wiring substrate, and the step of bonding
the semiconductor chip can not be conducted stably since the size
and the shape of the elastomer are not stable.
[0008] Further, bump electrodes are formed on the wiring substrate
on the side of the tape. That is, a bump electrode is connected
with the wirings by way of a through hole formed in the tape. Since
the thickness of the tape is relatively large, for example, as much
as 50 .mu.m, if the pitch between the bump electrodes is smaller
than the thickness of the tape, the aspect ratio of the through
hole is increased to bring about a concern that the bump electrode
and the wiring will not be connected. Accordingly, there is a
concern that an increase in the number of pins of the package may
be restricted.
[0009] In view of the above, an object of the present invention is
to provide a semiconductor integrated circuit device capable of
mounting an elastic structural material to a wiring substrate
stably with a high accuracy and making the bonding step of a
semiconductor chip stable, thereby enabling assembling with a high
yield.
[0010] Another object of the present invention is to provide a
technique for promoting an increase in the number of pins in a
package.
[0011] An object of the present invention is to provide a
semiconductor integrated circuit device capable of obtaining
excellent electrical properties in view of noise resistance by the
adoption of a multiple wiring layer structure.
[0012] An object of the present invention is to prevent wiring from
becoming contaminated ingredients of an elastic structural
material.
[0013] An object of the present invention is to prevent a
semiconductor chip from being damaged, improve the reliability of
the semiconductor chip, as well as prevent connection failure
between an elastic structural material and the semiconductor chip,
worsening of the flatness of the wiring substrate and lowering of
reliability.
[0014] An object of the present invention is to eliminate a
requirement for a soft-modified special wire bonder and to effect a
shortening of the contact time upon bonding by further simplifying
the trace of the bonding tool.
[0015] An object of the present invention is to solve a problem
concerning disconnection of wirings.
[0016] An object of the present invention is to reduce any damage
to a passivation layer or a semiconductor chip therebelow and
further improve the bondability by preventing contamination of the
wirings.
[0017] An object of the present invention is to increase the
bonding strength between wirings and a substrate material and
obtain a stable notch cutting performance.
[0018] An object of the present invention is to suppress warp of a
wiring substrate and improve bondability with a bonding material,
so as to constitute a package of excellent moisture proofness and
reliability.
[0019] An object of the present invention is to improve the
groove-fillage capability of an elastic structural material,
capable of increasing the strength of a metal mask, by using a
plurality of one side bridging portions, and further improving the
groove-fillage capability by the formation of a stopping dam for
sealant flow.
[0020] An object of the present invention is to improve the
bondability and prevent damage to a semiconductor chip in an inner
lead bonding technique.
[0021] An object of the present invention is to form a suitable
S-shaped configuration with no return of a bonding tool but by
merely driving the bonding tool vertically using a wiring design
which takes into consideration a bending stress ratio.
[0022] An object of the present invention is to reduce the
occurrence of cracks in wirings per se and moderate bonding damage
to a semiconductor chip.
[0023] An object of the present invention is to suppress bleeding
of low molecular weight ingredients of an elastic structural
material and further avoid a disadvantage involving the creation of
voids upon forming the elastic structural material by surface
flattening.
[0024] An object of the present invention is to improve the
fabrication accuracy for hole diameter for connection of a bump
electrode in a method of manufacturing a semiconductor integrated
circuit.
[0025] An object of the present invention is to provide a technique
for forming a semiconductor package which is capable of bonding
bump electrodes more satisfactorily, reducing the pitch of the bump
electrodes and which provides output terminals at a higher density
in a method of manufacturing a semiconductor integrated circuit
device.
[0026] These and other objects, as well as novel features of the
present invention will become apparent by consideration of the
descriptions in the specification with reference to the
accompanying drawings.
[0027] Among the features disclosed in the present application, a
summary of typical examples will be explained simply as
follows.
[0028] That is, one of the semiconductor integrated circuit devices
according to the present invention provides a package structure
applied to a semiconductor integrated circuit device in which a
wiring substrate is disposed by way of an elastic structural
material on a main surface of a semiconductor chip, lead portions
on one end of the wirings of the wiring substrate are electrically
connected with external terminals on the main surface of the
semiconductor chip, and land portions on the other end of the
wirings of the wiring substrate are electrically connected with
bump electrodes, wherein the wiring substrate has wirings formed on
the main surface of a substrate base material (tape), and an
elastic structural material is disposed opposite to the main
surface of the substrate base material.
[0029] Further, the bump electrodes are formed on the side of the
wirings.
[0030] Further, the bump electrodes are connected with the wirings
each by way of a through hole disposed in an insulation film formed
on the wirings and having a thickness smaller than that of the
wiring base material.
[0031] Further, the external terminals of the semiconductor chip
are disposed at a central portion or at an outer circumferential
portion of the semiconductor chip, and the bump electrodes
connected to the external terminals of the semiconductor chip by
way of the wirings of the wiring substrate are disposed to the
inside, outside or in both regions inside and outside with respect
to the outer circumference of the semiconductor chip.
[0032] Further, in a semiconductor integrated circuit device of the
present invention, the size of the end of the elastic structural
member of the semiconductor chip on the side of the externals
terminal and the end of the substrate base material of the wiring
substrate is determined based on the ingredients of the elastic
structural material.
[0033] Further, in a semiconductor integrated circuit device of the
present invention, a distance M2 between the end of the substrate
base material of the wiring substrate and the end of the elastic
structural material on the outer circumferential side of the
semiconductor integrated circuit device, and a distance M1 between
the end of the semiconductor chip and the end of the substrate base
material are determined within a range capable of satisfying the
relationship:
M1>M2>0
[0034] Further, in a semiconductor integrated circuit device of the
present invention, the wirings of the wiring substrate are formed
to such a shape that a portion fixed with the substrate base
material of the wiring substrate and a top end portion connected to
the external terminals of the semiconductor chip are displaced at
least by more than the width of the wirings.
[0035] Further, in a semiconductor integrated circuit device of the
present invention, the wirings of the wiring substrate are formed
as a cantilever structure fixed at one side to the substrate base
material of the wiring substrate.
[0036] Further, in a semiconductor integrated circuit device of the
present invention, the size of the end of an opening in a surface
protection film on the semiconductor chip is determined within such
a range that the wirings do not interfere with the surface
protection film at least on the side thereof on which a bonding
tool is driven down.
[0037] Further, in a semiconductor integrated circuit device of the
present invention, the wirings of the wiring substrate are formed
such that an effective area of a wiring portion of the wiring on
the side of the notch terminal end is made larger. Particularly,
the wiring portion on the side of the notch terminal end is
connected with an opposed land portion of the wirings, or is
extended longitudinally or laterally in a vacant region of the
wirings, or adjacent wirings are connected with each other.
[0038] Further, in a semiconductor integrated circuit device of the
present invention, the elastic structural material is formed within
a range greater over the entire circumference at least by more than
the width of a protrusion at the outer circumferential portion
formed in the elastic structural material.
[0039] Further, in a semiconductor integrated circuit device of the
present invention, when the elastic structural material is formed
in two parts so as not to be bonded on the external terminals of
the semiconductor chip, each of the ends of spaces to which the
divided elastic structural materials are opposed is formed in a
groove-shape. Particularly, a plurality of grooves are formed at
each of the ends of the elastic structural material, or a stepping
dam for sealant flow is previously formed during a sealing
step.
[0040] Further, in a semiconductor integrated circuit device of the
present invention, the connection structure between the external
terminals of the semiconductor chip and the wirings of the wiring
substrate are formed by previously forming stud bumps on the
external terminals of the semiconductor chip, and the external
terminals of the semiconductor chip and the wirings of the wiring
substrate are connected by way of the stud bumps.
[0041] Further, in a semiconductor integrated circuit device of the
present invention, the connection structure between the external
terminals of the semiconductor chip and the wiring substrate is
formed by previously supplying solder so as to surround the wirings
of the wiring substrate and the external terminals of the
semiconductor chip, and the external terminals of the semiconductor
chip are connected by way of the solder.
[0042] Further, in a semiconductor integrated circuit device of the
present invention, the connection structure between the external
terminal of the semiconductor chip and the wirings of the
semiconductor substrate are formed by connecting the wirings of the
wiring substrate and the external terminals of the semiconductor
chip by way of stud bumps by using stud bumps of solder or Au ball
so as to surround the wirings of the wiring substrate from
above.
[0043] Further, in a semiconductor integrated circuit device of the
present invention, the connection structure between the external
terminals of the semiconductor chip and the wirings of the wiring
substrate are formed by connecting the wirings of the wiring
substrate and the external terminals of the semiconductor chip by
using Al, solder or Au wire.
[0044] Further, in a semiconductor integrated circuit device of the
present invention, the wiring structure of the wiring substrate is
formed by narrowing the lateral size of the wirings from the end of
the substrate base material of the wiring substrate to the top end
of the wirings, such that the bending stress ratio .alpha. is
represented by:
.alpha.=.sigma.1/.sigma.0
[0045] where .sigma.0 is bending strength caused at the end of the
substrate base material and .sigma.1 is maximum stress caused at an
intermediate portion between the end of the substrate base material
and the top end of the wirings, and wherein the lateral size is
made constant particularly from a predetermined position, and the
size and the shape of the wirings are determined such that the
bending stress ratio .alpha. is from 1.2 to 1.5 in a case where the
bending stress ratio .alpha. is represented by the following
formula:
.alpha.=b1.times.(L2-L1)/(b2.times.L2)
[0046] in which L1 is a taper length, L2 is a wiring length, b1 is
a taper width and b2 is a wiring width.
[0047] Further, in a semiconductor integrated circuit device of the
present invention, the wiring structure of the wiring substrate is
formed by using an electroconductive material as a core material
and applying Au plating on the surface.
[0048] Further, the wiring structure of the wiring substrate is
formed by using Cu as a core material, applying Au plating on the
surface and making at least one end connected with the external
electrodes of the chip into a S-shaped configuration.
[0049] Further, in a semiconductor integrated circuit device of the
present invention, a flattening insulation film is formed on the
wiring substrate on the side of the wirings and an elastic
structural material is disposed on the insulation film.
[0050] Further, a method of manufacturing a semiconductor
integrated circuit device according to the present invention
comprises a step of forming an elastic structural material on the
rear face of a wiring substrate (tape side) in which wirings are
formed on the substrate base material (tape), a step of bonding a
semiconductor chip to the surface of the elastic structural
material so as to oppose the wiring substrate, a step of connecting
one end of the wirings to the external terminals of the
semiconductor chip, a step of forming an insulation film thinner
than the substrate base material on a main surface of the wirings,
a step of forming openings to the insulation film each at a
position corresponding to the other end of the wirings to be Joined
with the bump electrodes, and a step of forming the bump electrodes
being joined to the other end of the wirings by way of the
wirings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0051] FIG. 1 is a plan view illustrating a semiconductor
integrated circuit device which represents an Embodiment 1 of the
present invention;
[0052] FIG. 2 is a cross sectional view taken along line A-A' in
FIG. 1 of the Embodiment 1 according to the present invention;
[0053] FIG. 3 is a plan view illustrating the state of mounting the
semiconductor integrated circuit device in the Embodiment 1
according to the present invention to a mounting substrate;
[0054] FIG. 4 is a cross sectional view illustrating the state of
mounting the semiconductor integrated circuit device in the
Embodiment 1 according to the present invention to a mounting
substrate;
[0055] FIG. 5 is a flow chart illustrating the steps of assembling
the semiconductor integrated circuit device in the Embodiment 1
according to the present invention;
[0056] FIG. 6 is a cross sectional view of a main portion of the
semiconductor integrated circuit device in the Embodiment 1
according to the present invention;
[0057] FIG. 7 is a cross sectional view of a main portion for
comparative explanation of the semiconductor integrated circuit
device of the Embodiment 1 according to the present invention and a
semiconductor integrated circuit device studied by the present
inventor;
[0058] FIG. 8 is a cross sectional view of a main portion
illustrating both face wirings as a modified embodiment of a
semiconductor integrated circuit device in the Embodiment 1
according to the present invention;
[0059] FIG. 9 is a plan view illustrating a window opening portion
of a semiconductor integrated circuit device in the Embodiment 1
according to the present invention;
[0060] FIG. 10 is a cross sectional view corresponding to the
window opening in FIG. 9;
[0061] FIG. 11 is a cross sectional view for explaining the size of
a window opening and an edge portion of the semiconductor chip in a
semiconductor integrated circuit device in the Embodiment 1
according to the present invention;
[0062] FIG. 12 is a cross sectional view illustrating a concave
shape of an elastomer after printing of a semiconductor integrated
circuit device in the Embodiment 1 according to the present
invention;
[0063] FIG. 13 is a cross sectional view illustrating a tape
warping after appending a semiconductor chip in a semiconductor
integrated circuit device of the Embodiment 1 according to the
present invention;
[0064] FIG. 14 is a plan view illustrating a planer S-shaped lead
of a semiconductor integrated circuit device in the Embodiment 1
according to the present invention;
[0065] FIG. 15 is a cross sectional view as seen in the direction
of arrow B in FIG. 14 of a semiconductor integrated circuit device
in the Embodiment 1 according to the present invention;
[0066] FIG. 16 is a cross sectional view as seen in the direction
of arrow A in FIG. 14 in a semiconductor integrated circuit device
in the Embodiment 1 according to the present invention;
[0067] FIG. 17 is a cross sectional view illustrating a trace of a
bonding tool upon forming a standard S-shaped lead in a
semiconductor integrated circuit device in the Embodiment 1
according to the present invention;
[0068] FIG. 18 is a cross sectional view illustrating a trace of a
bonding tool upon forming a planer S-shaped lead in a semiconductor
integrated circuit device in the Embodiment 1 according to the
present invention;
[0069] FIG. 19 is a plan view for explaining a notch lead and a
beam lead of a semiconductor integrated circuit device in the
Embodiment 1 according to the present invention;
[0070] FIG. 20 is a plan view illustrating a notch lead at the
portion A in FIG. 19 of a semiconductor integrated circuit device
in the Embodiment 1 according to the present invention;
[0071] FIG. 21 is a plan view illustrating a beam lead of a
semiconductor integrated circuit device in the Embodiment 1
according to the present invention;
[0072] FIG. 22 is a cross sectional view illustrating a lead
bonding portion of a semiconductor integrated circuit device in the
Embodiment 1 according to the present invention;
[0073] FIG. 23 is a plan view illustrating a lead bonding portion
of a semiconductor integrated circuit device in the Embodiment 1
according to the present invention;
[0074] FIG. 24 is a cross sectional view illustrating, in an
enlarged scale, a landing position of a tool in the portion A in
FIG. 22, of a semiconductor integrated circuit device in the
Embodiment 1 according to the present invention;
[0075] FIG. 25 is a cross sectional view illustrating a bonding
portion improved for the size of a passivation opening, of a
semiconductor integrated circuit device in the Embodiment 1
according to the present invention;
[0076] FIG. 26 is a plan view illustrating a bonding portion for
leads extending in both directions of a semiconductor integrated
circuit device in the Embodiment 1 according to the present
invention;
[0077] FIG. 27 is a plan view illustrating standard anchor wirings,
of a semiconductor integrated circuit device ln the Embodiment 1
according to the present invention;
[0078] FIG. 28 is a plan view illustrating improved anchor wirings,
of a semiconductor integrated circuit device in the Embodiment 1
according to the present invention;
[0079] FIG. 29 is a perspective view illustrating a structure of a
standard elastomer, of a semiconductor integrated circuit device in
the Embodiment 1 according to the present invention;
[0080] FIG. 30 is a perspective view illustrating a state of
appending a semiconductor chip at a standard elastomer, of a
semiconductor integrated circuit device in the Embodiment 1
according to the present invention;
[0081] FIG. 31 is a perspective view illustrating a structure of a
wide elastomer, of a semiconductor integrated circuit device in the
Embodiment 1 according to the present invention;
[0082] FIG. 32 is a perspective view illustrating a state of
appending a semiconductor chip at a wide elastomer, of a
semiconductor integrated circuit device in the Embodiment 1
according to the present invention;
[0083] FIG. 33 is a cross sectional view illustrating a state of
appending a semiconductor chip at a wide elastomer, of a
semiconductor integrated circuit device in the Embodiment 1
according to the present invention;
[0084] FIG. 34 is a perspective view illustrating a structure of
the standard elastomer after appending a semiconductor chip, of a
semiconductor integrated circuit device in the Embodiment 1
according to the present invention;
[0085] FIG. 35 is a cross sectional view illustrating a structure
of a standard elastomer after appending the semiconductor chip, of
a semiconductor integrated circuit device in the Embodiment 1
according to the present invention;
[0086] FIG. 36 is a perspective view illustrating a structure of a
wide elastomer after appending the semiconductor chip, of a
semiconductor integrated circuit device in the Embodiment 1
according to the present invention;
[0087] FIG. 37 is a cross sectional view illustrating a structure
of a wide elastomer after appending the semiconductor chip, of a
semiconductor integrated circuit device in the Embodiment 1
according to the present invention;
[0088] FIG. 38 is a cross sectional view illustrating a concept of
metal mask printing, of a semiconductor integrated circuit device
in the Embodiment 1 according to the present invention;
[0089] FIG. 39 is a plan view illustrating a metal mask of a
standard elastomer, of a semiconductor integrated circuit device in
the Embodiment 1 according to the present invention;
[0090] FIG. 40 is a plan view illustrating a metal mask of a wide
elastomer, of a semiconductor integrated circuit device in the
Embodiment 1 according to the present invention;
[0091] FIG. 41 is a plan view illustrating a printed shape for a
plurality of suspended wide elastomers, of a semiconductor
integrated circuit device in the Embodiment 1 according to the
present invention;
[0092] FIG. 42 is a plan view illustrating a potting position for
groove-fillage of a wide elastomer, of a semiconductor integrated
circuit device in the Embodiment 1 according to the present
invention;
[0093] FIG. 43 is a cross sectional view illustrating a bonding
portion by a standard lead bonding, of a semiconductor integrated
circuit device in the Embodiment 1 according to the present
invention;
[0094] FIG. 44 is a cross sectional view illustrating a bonding
portion by using stud bumps, of a semiconductor integrated circuit
device in the Embodiment 1 according to the present invention;
[0095] FIG. 45 is a cross sectional view illustrating a lead
connection by using solder, of a semiconductor integrated circuit
device in the Embodiment 1 according to the present invention;
[0096] FIG. 46 is a plan view illustrating a lead connection using
solder, of a semiconductor integrated circuit device in the
Embodiment 1 according to the present invention;
[0097] FIG. 47 is a cross sectional view illustrating a lead
connection by using solder or Au ball, of a semiconductor
integrated circuit device in the Embodiment 1 according to the
present invention;
[0098] FIG. 48 is a perspective view illustrating a lead connection
by using solder or Au ball, of a semiconductor integrated circuit
device in the Embodiment 1 according to the present invention;
[0099] FIG. 49 is a cross sectional view illustrating a lead
connection by using Al or soldering wire, of a semiconductor
integrated circuit device in the Embodiment 1 according to the
present invention;
[0100] FIG. 50 is a cross sectional view illustrating a lead
connection by using an Au wire, of a semiconductor integrated
circuit device in the Embodiment 1 according to the present
invention;
[0101] FIG. 51 is a perspective view for explaining a lead design,
of a semiconductor integrated circuit device in the Embodiment 1
according to the present invention;
[0102] FIG. 52 is a perspective view illustrating modification of a
lead after bonding, of a semiconductor integrated circuit device in
the Embodiment 1 according to the present invention;
[0103] FIG. 53 is chart illustrating a relationship between a lead
size and a bending stress ratio, of a semiconductor integrated
circuit device in the Embodiment 1 according to the present
invention;
[0104] FIG. 54 is a cross sectional view illustrating a connection
portion of lead connection, of a semiconductor integrated circuit
device in the Embodiment 1 according to the present invention;
[0105] FIG. 55 is an enlarged cross sectional view illustrating a
lead bent portion, of a semiconductor integrated circuit device in
the Embodiment 1 according to the present invention;
[0106] FIG. 56 is an enlarged cross sectional view illustrating a
Ni-platingless lead bent portion, of a semiconductor integrated
circuit device in the Embodiment 1 according to the present
invention;
[0107] FIG. 57 is an enlarged cross sectional view illustrating a
lead press contact portion, of a semiconductor integrated circuit
device in the Embodiment 1 according to the present invention;
[0108] FIG. 58 is an enlarged cross sectional view illustrating a
Ni-platingless lead press contact portion, of a semiconductor
integrated circuit device in the Embodiment 1 according to the
present invention;
[0109] FIG. 59 is a cross sectional view illustrating a structure
of a semiconductor integrated circuit device in an Embodiment 2
according to the present invention;
[0110] FIG. 60 is a perspective view illustrating a structure of a
semiconductor integrated circuit device in the Embodiment 2
according to the present invention;
[0111] FIG. 61 is a plan view, as viewed from the rear face of a
semiconductor chip, of a semiconductor integrated circuit device in
the Embodiment 3 according to the present invention;
[0112] FIG. 62 is a plan view illustrating a semiconductor
integrated circuit device in the Embodiment 3 according to the
present invention;
[0113] FIG. 63 is a cross sectional view illustrating a
semiconductor integrated circuit device in the Embodiment 3
according to the present invention;
[0114] FIG. 64 is an enlarged cross sectional view illustrating a
portion A in FIG. 63, of a semiconductor integrated circuit device
in the Embodiment 3 according to the present invention;
[0115] FIG. 65 is a plan view for explaining a wiring structure of
a wiring substrate, of a semiconductor integrated circuit device in
the Embodiment 3 according to the present invention;
[0116] FIG. 66 is a plan view, as viewed from the rear face of a
semiconductor chip, of a semiconductor integrated circuit device as
an Embodiment 4 according to the present invention;
[0117] FIG. 67 is a plan view illustrating a semiconductor
integrated circuit device in the Embodiment 4 according to the
present invention;
[0118] FIG. 68 is a cross sectional view illustrating a
semiconductor integrated circuit device in the Embodiment 4
according to the present invention;
[0119] FIG. 69 is an enlarged cross sectional view illustrating a
portion A in FIG. 68, of a semiconductor integrated circuit device
in the Embodiment 4 according to the present invention;
[0120] FIG. 70 is a plan view for explaining a wiring structure of
a wiring substrate, of a semiconductor integrated circuit device in
the Embodiment 4 according to the present invention;
[0121] FIG. 71 is a plan view, as viewed from the rear face of a
semiconductor chip, of a semiconductor integrated circuit device in
the Embodiment 5 according to the present invention;
[0122] FIG. 72 is a plan view illustrating a semiconductor
integrated circuit device in the Embodiment 5 according to the
present invention;
[0123] FIG. 73 is a cross sectional view illustrating a
semiconductor integrated circuit device in the Embodiment 5
according to the present invention;
[0124] FIG. 74 is an enlarged cross sectional view illustrating a
portion A in FIG. 73, of a semiconductor integrated circuit device
in the Embodiment 5 according to the present invention;
[0125] FIG. 75 is a plan view for explaining a wiring structure of
a wiring substrate, of a semiconductor integrated circuit device in
the Embodiment 5 according to the present invention;
[0126] FIG. 76 is a cross sectional view illustrating the modified
shape of the lead in accordance with the bending stress ratio in a
comparative explanation between the semiconductor integrated
circuit device in the Embodiment 1 according to the present
invention and the semiconductor circuit device studied by the
present inventors;
[0127] FIG. 77 is a cross sectional view illustrating the modified
shape of the lead in accordance with the bending stress ratio, of
the semiconductor integrated circuit device in the Embodiment 1
according to the present invention;
[0128] FIG. 78 is a cross sectional view illustrating the modified
shape of the lead in accordance with the bending stress ratio, of
the semiconductor integrated circuit device in the Embodiment 1
according to the present invention;
[0129] FIG. 79 is a cross sectional view illustrating the modified
shape of the lead in accordance with the bending stress ratio, of
the semiconductor integrated circuit device in the Embodiment 1
according to the present invention;
[0130] FIG. 80 is a cross sectional view illustrating the modified
shape of the lead in accordance with the bending stress ratio, of
the semiconductor integrated circuit device in the Embodiment 1
according to the present invention; and
[0131] FIG. 81 is a cross sectional view illustrating a modified
example of a package structure, of the semiconductor integrated
circuit device in the Embodiment 1 according to the present
invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0132] The present invention will be described more specifically by
way of preferred embodiments with reference to the drawings.
Embodiment 1
[0133] FIG. 1 is a plan view illustrating a semiconductor
integrated circuit device representing an Embodiment 1 according to
the present invention, FIG. 2 is a cross sectional view taken along
line A-A' in FIG. 1, FIG. 3 and FIG. 4 are a plan view and a cross
sectional view illustrating a state of mounting a semiconductor
integrated circuit device to a mounting substrate, FIG. 5 is a flow
chart illustrating a step of assembling a semiconductor integrated
circuit device, and FIG. 6 to FIG. 58 and FIG. 76 to FIG. 81 are
views for comparative explanation between the feature of the
semiconductor integrated circuit device representing the Embodiment
1 of the present invention and a semiconductor integrated circuit
device representing a comparative example studied by the present
inventor. At first, an explanation will be given as to the
constitution of a semiconductor integrated circuit device of an
Embodiment 1 with reference to FIG. 1 and FIG. 2.
[0134] The semiconductor integrated circuit device representing
Embodiment 1 of the present invention is in the form of a 40 pin
ball grid array type semiconductor package, comprising a
semiconductor chip 1 having a plurality of semiconductor elements
and a plurality of bonding pads formed on a main surface, and an
elastomer 2 (elastic structural material) bonded on the main
surface of the semiconductor chip excepting for the portions
forming the bonding pads, a flexible wiring substrate 3 (wiring
substrate) formed with wirings connected at one end to the bonding
pads of the semiconductor chip 1, a solder resist 4 (insulation
film) formed on a main surface of the flexible wiring substrate 3,
and bumps 5 (bump electrodes) formed on a main surface of the
solder resist 4 and connected to the other end of the wirings by
way of openings in the solder resist 4, to constitute a package
structure in which the bonding portion of the semiconductor chip 1
is covered by a sealant 6, such as a resin.
[0135] The semiconductor chip 1 has, for example, a center pad
structure as shown in FIG. 1 in which a plurality of bonding pads 7
(external terminals) are formed in one row at a central portion in
the longitudinal direction, and the bonding pads are arranged at
non-uniform intervals. Predetermined integrated circuits, such as
memory circuits and logic circuits, are formed in the semiconductor
chip 1, for example, on a semiconductor substrate, such as made of
silicon, and the bonding pads 7 made of a material such as Al are
disposed as the external terminals for such circuits.
[0136] The elastomer 2 is made of an elastic material, for example,
a silicone resin, which is formed on the main surface of the
semiconductor chip 1, being bisected longitudinally of the chip 1
to provide the portion formed with the bonding pads 7, and is
bonded to the main surface of the chip 1 by way of the adhesive 8.
The elastomer 2 is provided for moderating stress concentration on
the soldering bumps 5 mainly caused by the difference in the heat
expansion coefficients of the semiconductor chip 1 and the package
mounting substrate.
[0137] The flexible wiring substrate 3 comprises, for example, as
shown in FIG. 2, a tape 9 as a basic material of the flexible
wiring substrate 3 (substrate base material) and wirings 10 bonded
on the main surface of the tape 9 by an adhesive 9', in which leads
11 on one end of the wirings 10 are connected to the bonding pads 7
of the semiconductor chip 1, and bump lands 12 on the other end are
connected with the soldering bumps 5. In the flexible wiring
substrate 3, the rear face of the tape 9 (on the side opposite to
the surface formed with the wirings 10) is bonded to the elastomer
2, and the solder resist 4 is formed on the main surface of the
wirings 10.
[0138] The tape 9 constituting the flexible wiring substrate 3 is
made of a material, for example, a polyimide resin, and a material
such as Cu is used as the core material for the wiring 10. A
portion of the lead 11 serving as one end of the wiring 10 is
formed with an Ni plating layer so as to cover the surface of the
core material, and an Au plating layer is formed further so as to
cover the surface of the Ni plating layer.
[0139] The solder resist 4 is made of an insulation material, such
as a light sensitive epoxy resin, and the solder bumps 5 are formed
on the main surface of the wirings 10 of the flexible wiring
substrate 3 by way of the openings in the solder resist 4 for a
predetermined range of the wirings 10, except for the connection
portion connected to the bump lands.
[0140] The soldering bumps 5 are made of a material, for example, a
Pb(560%)-Sn(40%) solder or an alloyed solder mainly composed of
Pb--Sn, and is connected to the bump lands 12 of the wirings 10
constituting the flexible wiring substrate 3. The solder bumps 5
are arranged in two rows in the regions on both side of the bonding
pads 7 of the semiconductor chip 1.
[0141] The thus constituted semiconductor integrated circuit device
is mounted, for example, as shown in FIG. 3 and FIG. 4, as a
semiconductor integrated circuit device of a chip size package 13,
for example, a DRAM, together with a semiconductor integrated
circuit device of QFP type package 14, onto a mounting substrate
15, which is made, for example, of glass or epoxy, on a memory card
and can be retractably mounted with respect to portable equipment,
such as a portable telephone or a handy type personal computer by
way of external connection terminals 16.
[0142] For the function of the Embodiment 1 of the present
invention, an outline of the steps of assembling the semiconductor
package will be explained on the basis of the process flow shown in
FIG. 5.
[0143] At first, before assembling the semiconductor package,
wirings 10 are formed on the tape 9, the flexible wiring substrates
having the leads 11 formed by etching a portion of the wirings 10.
Further, the elastomer 2, the semiconductor chip 1 formed with
predetermined integrated circuits and provided with the bonding
pads 7 as external terminals, the sealant 6, and flux and solder
forming the solder balls 17 are provided.
[0144] The flexible wiring substrate 3 can be prepared, for
example, as typically represented by the technique of a TAB (Tape
Automatic Bonding) tape, by bonding a thin metal foil such as Cu on
a tape 9 made of a polyimide resin by means of an adhesive, forming
a required pattern by photoresist on the metal foil using a
photographic technique, then forming a desired wiring pattern 10 by
etching (including also leads 11) and, further, applying Ni--Au
plating treatment to the surface thereof, for example, by an
electric field plating method.
[0145] Then, for example, the elastomer 2 is formed by printing to
a thickness of 50 to 150 .mu.m on the tape 9 of the flexible wiring
substrate 3, and a silicone type adhesives 8 is coated and printed
on the surface of the elastomer 2 (steps 501, 509). The elastomer 2
is not always printed, but an elastomer previously formed into a
film-shape may be cut into a predetermined shape and bonded to the
rear face of the tape 9 by means of the adhesive 8.
[0146] Further, the leads 11 at one end of the wirings 10 of the
flexible wiring substrate 3 and the bonding pads 7 of the
semiconductor chip 1 are aligned such that their relative positions
coincide with each other, and the semiconductor chip 1 is appended
by adhesion to the elastomer 2 printed on the tape 19 of the
flexible wiring substrate 3 (step 503).
[0147] Then, they are turned upside down in a state where the
semiconductor chip 1 and the tape 9 of the wiring substrate 3 are
appended by way of the elastomer 2, the semiconductor chip 1 and
the tape 9 of the flexible wiring substrate 3 in a state appended
by way of the elastomer 2 are turned upside down in the lead
bonding step, the lead 11 is driven down on the bonding pad 7 of
the semiconductor chip 1 while being deformed into a S-shaped
configuration by a bonding tool 18, as shown by the cross section
in FIG. 2, and the lead 11 and the bonding pad 7 are connected, for
example, by a method of supersonic thermal press bonding (step
504).
[0148] Successively, in the sealing step, the lead bonding portion
of the bonding pad 7 of the semiconductor chip 1 and the lead 11 of
the flexible wiring substrate 3 are resin encapsulated, for
example, by coating a sealant 6, such as an epoxy resin, from a
dispenser 19 to thereby enhance the reliability at the junction
portion between the semiconductor chip 1 and the flexible wiring
substrate 3 (step 505).
[0149] Subsequently, in the cutting step for the flexible wiring
substrate 3, the outer edge portion of the tape 9 is cut along a
position somewhat outside the edge of the semiconductor chip 1, to
form a package outer shape of CSP (Chip Size Package or Chip Scale
Package) (step 506).
[0150] Then, in the bump attaching step of the solder bump 5, the
bump 5 is formed by joining a solder ball 17 to the corresponding
bump land 12 of the wirings 10 of the flexible wiring substrate 3
to form the bump 5 and, finally, by way of the selection and
marking, the step of assembling the semiconductor package in the
Embodiment 1 according to the present invention is finished (step
507, 508).
[0151] In the step of assembling the semiconductor package, the
order of the tape cutting step (step 506) and the bump attaching
step (step 507) may be reversed.
[0152] Thus, the Embodiment 1 has a semiconductor package structure
in which bonding pads 7 are arranged concentrically in one row
along a central portion of the semiconductor chip 1, and the solder
bumps 5 are disposed at the inside of the outer circumference of
the semiconductor chip 1 connected by way of the wirings 10 of the
flexible wiring substrate from the bonding pads 7.
[0153] Now, the feature of the package structure for the
semiconductor integrated circuit device of the Embodiment 1 will be
explained by comparison with a package structure formed by a
technique studied by the present inventor including the structure
and the process with reference to FIG. 6 to FIG. 58
successively.
[0154] 1. Surface Wiring Structure (a structure in which the
elastomer is formed on the wiring substrate on the side of the tape
and the bump electrodes are formed on the side of the wirings)
[0155] To assist in providing technical explanation of the surface
wiring structure, FIG. 6 is a cross sectional view of a main
portion illustrating the surface wiring structure, FIG. 7 is a
cross sectional view of a main portion illustrating the rear face
wiring structure (a structure in which bump electrodes are formed
to the wiring substrate on the side of the tape and the elastomer
is formed on the side of the wirings) and FIG. 8 is a cross
sectional view of a main portion illustrating wirings on both
surfaces.
[0156] The package structure of the Embodiment 1 is a so-called
"surface wiring structure" as shown in an enlarged scale in FIG. 6,
in which an elastomer 2 is bonded to a flexible wiring substrate 3
on one side of a tape 9 (on the side facing the semiconductor chip
1) and a solder resist 4 and a bump electrode 5 are formed on the
other side of the wirings 10. On the other hand, there is a
technique studied by the present inventor which may be referred to
as a so-called "rear face wiring structure", as shown in FIG. 7, in
which an elastomer 2 is bonded on one side of the wiring 10 and a
solder bump 5 is formed on the other side of the tape 9. In FIG. 6,
an Au plating 11a is formed, for example, by an electric field
plating on the surface of a lead 11 on one end and on the surface
of a land 12 on the other end of the wiring 10.
[0157] In the rear face wiring structure described above with
reference to FIG. 7, a through hole 12b for joining the bump 5 is
formed, for example, by punching out an opening in the tape 9,
which is made of a material such as a polyimide resin, whereas in
the surface wiring structure of the Embodiment 1, as seen in FIG.
6, a solder resist 4 made of a material such as a light sensitive
epoxy resin is coated on the main surface of the wiring 10, and a
connection hole 12a of a desired size is formed at a desired
position by a photographic process, such as exposure and
development, so that the following advantages can be expected.
[0158] (1) Since the opening for the solder bump 5 is formed by
exposure and development of the solder resist 4, the fabrication
accuracy for the hole diameter can be improved compared with a case
of puncturing an opening in the tape 9 of the flexible wiring
substrate 3 in the rear face wiring structure by machining.
[0159] (2) While the minimum thickness of the tape 9, in practice,
is about 50 .mu.m, the solder resist 4 can be coated to a thickness
of about 10 to 20 .mu.m stably depending on the coating condition,
so that a smaller solder ball 17 can be joined satisfactorily.
[0160] For example, in a case of forming a solder bump of about 30
.mu.m diameter, which is less than the thickness of the tape 9, the
aspect ratio of the through hole is excessively large in the rear
face wiring structure, thereby possibly resulting in a connection
failure. On the other hand, the aspect ratio can be lowered to cope
with such a problem in the surface wiring structure.
[0161] (3) Since the pitch of the solder bumps 5 can be made
smaller in the surface wiring structure as compared with the rear
face wiring structure, a semiconductor package having output
terminals for the solder bumps arranged with a higher density can
be obtained.
[0162] (4) Since an elastomer 2 is disposed on the flat surface at
the back of the tape 9, the elastomer 2 can be mounted (coated or
appended) in a voidless manner stably with a high accuracy.
Further, since the size and the shape of the elastomer 2 are
stabilized, the step of bonding the semiconductor chip 1 is also
stable, thereby making it possible to conduct assembling at a
higher yield.
[0163] As described above, the technique of forming the rear face
wiring structure results in problems, such as in the formation of
the opening in the tape 9 of the flexible wiring substrate 3 and in
the bondability between the wirings 10 of the flexible wiring
substrate 3 and the elastomer 2, whereas such problems can be
solved by adopting the surface wiring structure as provided in the
Embodiment 1.
[0164] Further, in the wiring structure of the flexible wiring
substrate 3, it is possible to use a flexible wiring substrate 3
having a double face wiring structure, for example, as shown in
FIG. 8, that is, having layered wirings on both surfaces of the
tape 9, in addition to the single face wiring structure as shown in
FIG. 6, and it can be applied further to three or more layered
wiring structures.
[0165] In the example of FIG. 8, a first wiring 20 is used as a
signal wiring while the second wiring 21 is used as a ground plane,
in which the second wiring 21 and the bump 5 or the first wiring 20
are electrically connected by way of a via hole 22. Such a
structure has the advantage of obtaining an excellent electric
characteristic, for example, from the point of view of noise
resistance.
[0166] 2. Optimization of Tape Edge Position Relative to
Elastomer
[0167] To assist in providing a technical explanation of the
optimization of tape edge position relative to the elastomer, FIG.
9 is a plane view illustrating window openings, FIG. 10 is a cross
sectional view illustrating a window opening in FIG. 9 and FIG. 11
is a cross sectional view for assisting in the explanation of the
size of the window opening portion and the edge portion of the
semiconductor chip.
[0168] The package structure of the Embodiment 1, as shown in FIG.
9, has a BGA (Ball Grid Array) structure in which the solder bumps
5 are arranged in a matrix on the main surface of the flexible
wiring substrate 3. In this example, as shown in FIG. 10, the
semiconductor 1 has a center pad arrangement in which a window
opening portion 23 is disposed longitudinally at a central portion,
and the portion and the peripheral edge of the semiconductor chip 1
are resin capsulated by the sealant 6 to attain a structure of high
moisture proofness and reliability in the final structure.
[0169] By the way, in the technique studied by the present
inventor, when the end of the elastomer 2 (on the side of the
window opening 23) is brought closer to the edge of the tape 9,
that is, if the length L1 between the end of the elastomer 2 of the
semiconductor chip 1 on the side of the bonding pad 7 and the end
of the tape 9 is reduced, contamination to the lead 11 results due
to a bleeding ingredient and volatile ingredient of the elastomer
2.
[0170] On the other hand, if the length L1 is made larger, that is,
if the elastomer is excessively retracted from the edge of the tape
9, the length L2 between the end of the elastomer 2 and the solder
bump 5 is reduced, and since the elastomer 2 is not present below
the innermost portion of the solder bump 5, this may possibly
increase the variation in the height of the solder bump 5 or widen
the encapsulation region for the window opening 23, making it
difficult to fill in the sealant 6.
[0171] On the other hand, in the Embodiment 1, these problems can
be solved simultaneously by selecting an appropriate length for L1
so as to set the end of the elastomer 2 at an optimal position
between the end of the tape 9 and the solder bump 5.
[0172] That is, in order to eliminate the foregoing problems
related to the window opening 23, the length L1 is defined as
indicated below. For example, in this embodiment, the printing
accuracy of the elastomer 2 is defined as about .+-.100 .mu.m.
Accordingly, if the length L1 is less than 100 .mu.m, since it may
extend outside of the tape 9 due to a printing deviation, it must
be greater than the printing accuracy (100 .mu.m) at the least.
[0173] Further, since there is no problem from contamination to the
lead 11 by a bleeding ingredient or volatile ingredient of the
elastomer 2 if it is actually spaced by about 300 .mu.m from the
actual edge, the length L2 is set, for example, at 300 .mu.m as a
minimum. However, a design with a minimum value of about 100 .mu.m
is possible if an elastomer 2 of less contamination and bleeding is
used or a countermeasure, for example, cleaning of the
contamination, is adopted.
[0174] As described above, contamination to the lead 11 caused by
bleeding ingredients or volatile ingredients of the elastomer 2 can
be prevented, the variation in the height of the solder bumps 5 can
be made stable and the sealing region of the window opening 23 can
be filled with ease by selecting an appropriate length L1 as
provided in the Embodiment 1.
[0175] 3. Optimization of the Outer Size of the Package
[0176] To assist in providing a technical explanation of the
optimization of the outer size of the package, FIG. 11 is a cross
sectional view for explaining the size of the window opening and
the edge portion of the semiconductor chip, FIG. 12 is a cross
sectional view illustrating a concave portion of the elastomer
after printing and FIG. 13 is a cross sectional view illustrating
warp in the tape after appending a semiconductor chip.
[0177] For example, in the technique studied by the present
inventor, looking to FIG. 11 and assuming that the distance between
the end of the semiconductor chip 1 on the outer circumference of
the package and the end of the tape 9 of the flexible wiring
substrate 3 is M1 and the distance between the end of the elastomer
2 and the end of the tape 9 is M2, the following problems are
present:
[0178] (1) If M1<0, since the outermost circumference of the
package is represented by the wall of the semiconductor chip 1.
There is a great possibility of inducing cracks in the
semiconductor chip 1 during the assembling step, particularly upon
insertion and withdrawal of the chip from a receptacle, during tray
transportation and the like.
[0179] (2) If M1<0, M2>0, since the circuit surface of the
semiconductor chip 1 will be exposed to the outside, a problem may
be caused which affects the reliability and the sealing for
preventing this, although this possibly leads to an increase of the
fabrication steps.
[0180] (3) If M1-M2<0, peripheral protrusions of the elastomer 2
after printing, as shown in FIG. 12, interferes with the bonding
portion of the semiconductor chip 1, as shown in FIG. 13, so as to
cause bonding failure upon appending, reducing the flatness of the
flexible wiring substrate 3 and causing a reduction of the
reliability.
[0181] (4) If M2=0, it is necessary to cut the elastomer 2, which
causes a problem due to the difficulty of the cutting.
[0182] On the other hand, in the Embodiment 1, the foregoing
problems can be overcome by determining the relationship for the
distance between the end of the semiconductor chip 1 or the end of
the elastomer 2 and end of the tape 9 as: M1>M2>0. That is,
in the explanatory view illustrating the edge portion of the
package in FIG. 11, since the cutting error in the tape cutting
step for determining the final outer shape is about 100 .mu.m, it
is desirable to ensure that M2 is more than 100 .mu.m in order that
the cutting jig does not reach the elastomer 2.
[0183] By the way, the cross sectional shape after forming the
elastomer 2 by printing and hardening the same by baking is as
shown in FIG. 12, which shows that a peripheral portion tends to be
higher as a result of being pulled by the mask upon leaving the
plate after printing in a case of a material having a thixotropic
property which is higher to some extent. For example, if the
semiconductor chip 1 is appended to the elastomer 2 under the
condition that M1<M2 so that the end of the semiconductor chip
extends past the end of the elastomer 2, a problem occurs in that
the surface of the tape 9 warps to conform to the cross sectional
shape of the elastomer 2, as shown in FIG. 13.
[0184] In order to prevent this, it is effective to eliminate the
high peripheral portion of the elastomer 2 at the outside of the
semiconductor chip 1 by setting M1>M2. For instance, since the
width of the protrusion is about 200 .mu.m, it is desirable for
(M1-M2) to be 240 .mu.m and the distance M1 to be about 360 .mu.m
in view of the distance M2=100 .mu.m being provided for the cutting
property.
[0185] Cutting the tape 9 at the outer circumference as described
above provides advantages in that the outer shape error is reduced,
and peripheral jigs such as a receptacle or a tray need not be
changed to change the size to some extent of the semiconductor chip
1.
[0186] As described above, in the Embodiment 1, it is possible to
avoid cracking and chipping of the semiconductor chip 1 to improve
the cutting margin during the cutting step. Further, the circuit
surface of the semiconductor chip 1 can be entirely disposed below
the elastomer 2 to provide the advantage of improving the moisture
proofness and eliminating the requirement for sealing the outer
circumferential portion.
[0187] 4. Planer S-Shaped Lead
[0188] To assist in providing a technical explanation of the planer
S-shaped lead, FIG. 14 is a plan view illustrating a planer
S-shaped lead, FIG. 15 is a cross sectional view as seen in the
direction of arrow B in FIG. 14, FIG. 16 is a cross sectional view
as seen in the direction of arrow A in FIG. 14, FIG. 17 is a cross
sectional view illustrating the trace of a bonding tool upon
forming a standard S-shaped lead and FIG. 18 is a cross sectional
view illustrating the trace of a bonding tool upon forming a planer
S-shaped lead.
[0189] The S-shaped configuration is such that the length of a lead
11 at one end of a wiring 10 is substantially longer than the
linear distance between a pad 7 of a chip 1 and the edge portion
11b of the tape 9, so that stresses on the lead 11 can be
reduced.
[0190] For example, in the technique of forming a standard S-shaped
lead 24 as studied by the present inventor, the lead which is
employed is a linear notch lead or a beam lead, as shown by the
dotted line in FIG. 14, and in order to form a sag (S-shaped
configuration) sufficient to withstand thermal deformation during
bonding, as shown by a fine line in FIG. 15, it is necessary to
employ a motion along a special bonding tool trace 25 which
involves first driving down the lead 11 just above the
semiconductor chip 1, then laterally displacing the lead and then
again driving it down onto the bonding pad 7, which operation may
require a special wire bonder.
[0191] On the other hand, in the Embodiment 1, the foregoing
problem can be solved by preparing the lead 11 of the wiring 10 so
that it does not have a linear shape, but is a planer lead 26 of a
S-shaped configuration in which the base portion of the wiring 10
and the bonding portion at the top end are previously displaced at
least by more than the width of the lead 11, as shown in FIG. 14,
upon forming the wiring 10 on the tape 9 of the flexible wiring
substrate 3.
[0192] As described above, by such forming of the planer S-shaped
lead 26, a lead having a stable and suitable S-shaped configuration
can be formed by a bonding tool trace 25 by simply driving down a
typical wire bonder, as shown in FIG. 18, since a sag due to the
original planer S-shaped configuration is formed as shown in FIG.
16, although a straightened shape as shown in FIG. 15 is
formed.
[0193] Thus, a planer S-shaped lead 26 of stable S-shaped
configuration can be found with no requirement for a soft-modified
special wire bonder and, further, an effect for shortening the
contact time upon bonding can also be expected since the bonding
tool trace 25 can also be simplified.
[0194] 5. Beam Lead
[0195] To assist in providing a technical explanation of the beam
lead, FIG. 19 is a plan view for explaining a notch lead and a beam
lead, FIG. 20 is a plan view illustrating a notch lead in a portion
A of FIG. 19 and FIG. 21 is a plan view illustrating a beam
lead.
[0196] For example, in the technique studied by the present
inventor, as shown in FIG. 20, which is an enlarged view of the
lead 11 in FIG. 19, the lead 11 is formed with a notch 27, for
example, of a V-shaped cut at a cutting portion. A portion slightly
inside of the notch 27 is driven downwardly by a bonding tool 18
upon bonding, to cut the lead 11 at the portion of the notch 27.
However, the width of the notch 27 changes due to varied etching
for the wiring 10 in the manufacturing step for producing the
flexible wiring substrate 3, leading to the possibility that the
lead will not be cut upon bonding.
[0197] Further, even if it is cut, there still may be a problem in
that the lead may be cut at a portion different from the desired
notch 27, or the notch may be too narrow resulting in the lead
being disconnected before the plating step of the flexible wiring
substrate 3, so that the plating can not be accomplished.
[0198] On the other hand, in the Embodiment 1, as shown in FIG. 21,
the problem upon cutting the lead 11 as described above can be
overcome by forming the lead with a cantilever beam structure,
namely, a so-called beam lead 28 in which one end is fixed to the
tape 9 of the flexible wiring substrate 3 and the other end as the
cutting side formed with the notch 27 is left open.
[0199] 6. Passivation Size for the Periphery of the Bonding Pad
[0200] To assist in providing a technical explanation of the size
of the passivation film at the periphery of the bonding pad, FIG.
22 is a cross sectional view illustrating a lead bonding portion,
FIG. 23 is a plan view illustrating a lead bonding portion, FIG. 24
is a cross sectional view illustrating a tool landing point at the
portion in FIG. 22 in an enlarged scale, FIG. 25 is a cross
sectional view illustrating a bonding portion improved for the size
of the passivation opening and FIG. 26 is a plan view illustrating
a bonding portion of a two way lead.
[0201] In a memory chip typically represented by a DRAM or the
like, a passivation film 29 made of a polyimide type resin is
formed on the chip for preventing soft errors caused by
.alpha.-rays.
[0202] For example, in the technique studied by the present
inventor, since the lead 11 is first driven downwardly just above
the semiconductor chip 1, then displaced laterally and again driven
downwardly on the bonding pad 7 of the semiconductor chip 1, as
shown by the bonding tool trace 25 in the bonding sequence in FIG.
22, FIG. 23 and FIG. 24, there is the possibility of a problem in
that the passivation film 29 on the semiconductor chip 1 or the
semiconductor chip 1 therebelow may undergo damage during the first
driving down operation, or ingredients of the passivation film 29
may be deposited to contaminate the bonding portion on the lower
surface of the lead 11 to degrade the bondability.
[0203] On the other hand, in the Embodiment 1, the foregoing
problems can be solved by setting the distance L3 from the edge of
the bonding pad 7 to the edge of the passivation film 29 on the
side of the bonding pad 7, as seen in FIG. 22, FIG. 23, and FIG.
24, such that the passivation opening 30 is extended and enlarged,
whereby the lead 11 does not interfere with the passivation film 29
at least on the side thereof where the bonding tool 18 is driven
down, resulting in an improvement, as shown in FIG. 25.
[0204] That is, in FIG. 24, the size L3 is about 25 .mu.m in an
example of a semiconductor chip 1, for example, a memory device. In
this regard, since the size of the bonding pad 7 is 100 .mu.m
square and the size of the top end of the bonding tool 18 is equal
to or less than that, the distance L3 of the passivation film 29
from the pad 7, as seen in FIG. 25, is desirably, for example, more
than 125 .mu.m.
[0205] As described above, a suitable bonding property can be
attained without the risk of damage to the passivation film 29 on
the semiconductor chip 1 or to the semiconductor chip 1 or without
deposition of ingredients of the passivation film 29 onto the
bonding portion at the lower surface of the lead 11 which could
result in contamination.
[0206] Further, in a case where the leads 11 extend in both
directions, the problem can also be coped with similarly by
enlarging the distance from the opening edge of the bonding pad 7
to the edge of the passivation film 29 on the side of the bonding
pad 7 at least on the side where the bonding tool is driven down.
Enlargement of the space between the edges causes no problem even
if applied to the opposite side to such an extent as to avoid
exposing the circuit surface of the semiconductor chip 1.
[0207] 7. Improvement of the Anchor Wiring
[0208] To assist in providing a technical explanation of the
improvement of the anchor wiring, FIG. 27 is a plan view
illustrating a standard anchor wiring and FIG. 28 is a plan view
illustrating an improved anchor wiring.
[0209] For example, in the-technique studied by the present
inventors, in a pattern of a standard anchor wiring 31 on the
terminal end of a notch, as shown in FIG. 27, if the notch 27 is
formed to be smaller than a designed value, there is a possibility
that the lead will not be cut at the portion of the notch 27, but
the bonding strength between the wiring 10 and the tape 9 ahead of
the notch in the standard anchor wiring 31 may not be sufficient to
prevent a portion of the standard anchor wiring 31 to be peeled
from the tape 9.
[0210] On the other hand, in this Embodiment 1, the bonding
strength between the wiring 10 and the tape 9 can be increased to
obtain a stable cutting performance of the notch 27 by providing an
enlarged anchor wiring 32 for enlarging the effective area in the
portion for the anchor wiring at the terminal end as shown in FIG.
28.
[0211] That is, the following improved examples of enlarged anchor
wirings 32 are shown in FIG. 28.
[0212] (1) An enlarged anchor wiring 32 is connected to a bump land
12 to an opposing wiring 11.
[0213] (2) Enlarged anchor wiring 32 is extended longitudinally in
a vacant space in the wirings 11.
[0214] (3) Enlarged anchor wiring 32 is extended laterally in a
vacant space in the wirings 11.
[0215] (4) Adjacent extended anchor wirings 32 are connected with
each other. In each of the examples, the cutting performance of the
notch 27 can be stabilized by the increase of the adhesion strength
between the wiring 10 and the tape 9 by increasing the effective
area of the portion of the enlarged anchor wirings 32.
[0216] 8. Wide Elastomer Structure
[0217] To assist in providing technical explanation of the wide
elastomer structure, FIG. 29 is a perspective vie's illustrating a
structure of a standard elastomer, FIG. 30 is a perspective view
illustrating the state of appending a semiconductor chip to a
standard elastomer, FIG. 31 is a perspective view illustrating the
structure of a wide elastomer, FIG. 32 is a perspective view
illustrating the state of appending a semiconductor chip to the
wide elastomer and FIG. 33 is a cross sectional view illustrating
the state of appending a semiconductor chip to the wide
elastomer.
[0218] In the technique studied by the present inventor, the
elastomer is bonded on both sides of a bonding pad 7 of a
semiconductor chip 1 and, in a structure using a standard elastomer
33, as shown in FIG. 29 and FIG. 30, there is a possibility that
warping will occur in the flexible wiring substrate due to the
effect of peripheral protrusions in a structure in which the
surface of the elastomer 2 is smaller than that of the
semiconductor chip 1, as shown in FIG. 13, and that the warping
brings about a problem, for example, during the forming of the
solder bumps 5 and the mounting of the substrate.
[0219] On the other hand, in the structure of a wide elastomer 34
which is larger than the outer size of the semiconductor chip 1 in
the embodiment as shown in FIG. 31, the peripheral protrusions of
the wide elastomer 34 are outside of the edges of the semiconductor
chip, as shown in FIG. 32 and FIG. 33, after appending the
semiconductor chip 1, and since the semiconductor chip 1 is bonded
substantially to a flat portion of the wide elastomer 34, warping
of the flexible wiring substrate 3 can be avoided.
[0220] Further, as shown in FIG. 33, since a wide coating area of
an adhesive 8 can be employed, the portion in which the adhesive 8
is not provided and which is left unbonded is reduced in size, and
since the adhesive will extrude uniformly at the periphery of the
semiconductor chip 1 to form an adhesive bead 35, it is possible to
constitute a package of excellent moisture proofness and
reliability without applying peripheral sealing.
[0221] More particularly, the width of the protrusions at the
periphery of the wide elastomer 34 is, for example, about 200 to
300 .mu.m depending on the physical property of the material and,
accordingly, the wide elastomer 34 extends over a larger range at
the entire circumference at least by more than the protrusion width
afforded by the chip size of the semiconductor chip 1, as shown in
FIG. 33 in the Embodiment 1.
[0222] Further, while the flatness is improved by forming the wide
elastomer 34 sufficiently large, if the tape 9 is to be cut just at
the outer circumference of the semiconductor chip 1, the tape 9
will be cut together with the wide elastomer 34 along a cutting
line 36, which is necessary to define the package outer shape.
[0223] As described above, by using the wide elastomer 34 which is
larger than the outer size of the semiconductor chip 1, warping of
the flexible wiring substrate 3 can be suppressed, and the
bondability of the semiconductor chip 1 can be made stable to
improve the moisture proofness and the reliability of the
package.
[0224] 9. Groove-Filling Technique of the Elastomer
[0225] To assist in providing a technical explanation of the
groove-filling technique of the elastomer, FIG. 31 and FIG. 32 are
perspective views illustrating the structure of the wide elastomer
and the state of appending the semiconductor chip as described
above, FIG. 34 is a perspective view illustrating the structure
after appending a semiconductor chip to a standard elastomer, FIG.
35 is a cross sectional view thereof, FIG. 36 is a perspective view
illustrating a structure after appending a semiconductor chip to a
wide elastomer, FIG. 37 is a cross sectional view thereof, FIG. 38
is a cross sectional view illustrating the concept of metal mask
printing, FIG. 39 is a plan view illustrating a metal mask of a
standard elastomer, FIG. 40 is a plan view illustrating a metal
mask of a wide elastomer, FIG. 41 is a plan view illustrating a
printed shape of an wide elastomer having plural bridge portions
and FIG. 42 is a plan view illustrating a potting position for
groove-filling of the wide elastomer.
[0226] For example, in the structure of a standard elastomer 33 as
shown in FIG. 34 and FIG. 35, in the technique studied by the
present inventor, when an elastomer is formed by printing using a
metal mask 37, as shown in FIG. 39, in the structure of the
standard elastomer 33 shown in FIG. 34 and FIG. 35, since a bridge
portion 39 is always present across the printing area opening 38 of
the metal mask 37 shown in FIG. 39, a groove 40 (space) surrounded
by walls of the semiconductor chip 1 and the elastomer is present
below the tape suspended portion.
[0227] Accordingly, when the window opening 23 (FIG. 9) is
resin-encapsulated in a structure in which the groove 40 remains at
the ends of the space defined by the semiconductor chip 1 and the
elastomer, the sealant 6 will leak through the groove 40, and so it
is necessary to previously seal the open end portions by a method
such as separate potting and then seal the window opening 23.
[0228] As described above, the concept of printing by use of a
metal mask 37 is designed to form the elastomer for a desired range
to a desired thickness, by positioning and disposing a metal mask
37 having a printing area opening 38 at a predetermined position
with respect to a flexible wiring substrate 3, only for the printed
portion as shown in FIG. 39 in the case of the standard elastomer
33 and as shown in FIG. 40 in the case of the wide elastomer
34.
[0229] Accordingly, in the Embodiment 1, the wide elastomer 34
described above and shown in FIG. 31 is printed by a metal mask 37
as shown in FIG. 40, in which a groove 40 surrounded by the walls
of the semiconductor chip 1 and the elastomer 2 can be narrowed by
printing the elastomer having a restricted bridge portion 39 for
the printing area opening 38 of the metal mask 37. For example, the
minimum value for the width of the groove 40 determined by the
strength of the bridge portion 39 of the metal mask 37 is about 200
.mu.m.
[0230] Further, in a case of a structure in which the semiconductor
chip is appended to the elastomer by coating the adhesive 8 on the
main surface of the elastomer 2, if the adhesive 8 is coated in a
sufficient amount, excessive adhesive 8 will fill the groove 40 in
response to the pressure created upon appending to make the window
opening 23 a closed space, so that the window opening 23 can be
sealed without applying sealing.
[0231] Further, the groove-fillage can be improved by restricting
the bridge portion 39 of the metal mask 37 thereby narrowing the
groove 40, but this results in a side effect of lowering the
strength of the metal mask 37. However, by providing a plurality of
bridge positions on one side to produce the construction as shown
in FIG. 41, the strength of the metal mask 37 can be improved
without changing the width of the groove 40 although the number of
the grooves 40 is increased.
[0232] Further, with an aim toward improving the groove-fillage, as
shown in FIG. 42, when resin, adhesive or the like is potted, for
example, at the potting position 42 of the groove 40 of the
elastomer to form a stopping dam for the sealant flow just before
appending the semiconductor chip 1 the groove-fillage can be
improved still further.
[0233] Further, in a case of filling by potting before sealing the
window opening 23 after appending and bonding of the semiconductor
chip as in the technique studied above, the sealing performance can
be improved outstandingly by restricting the width of the groove
40.
[0234] As described above, the groove-fillage can be improved,
particularly, by restricting the bridge portion 39 of the metal
mask 37 thereby narrowing the groove 40 of the elastomer and,
further, the groove-fillage can be improved even more by previously
forming a stopping dam for the sealant flow to the potting position
42.
[0235] 10. Inner Lead Bonding Technique
[0236] To assist in providing an explanation of the inner lead
bonding technique, FIG. 43 is a cross sectional view illustrating a
bonding portion produced by a standard lead bonding, FIG. 44 is a
cross sectional view illustrating a bonding portion produced by
using a stud bump, FIG. 45 and FIG. 46 are a cross sectional view
and a plan view, respectively, illustrating a lead connection using
soldering, FIG. 47 and FIG. 48 are a cross sectional view and a
perspective view, respectively, illustrating a lead connection
using a solder or Au ball, FIG. 49 is a cross sectional view
illustrating a connection using an Al or solder wire and FIG. 50 is
a cross sectional view illustrating a connection using an Au
wire.
[0237] For example, in the technique studied by the present
inventor, a lead 11 on which Au plating is provided is directly
driven onto a bonding pad 7 and thermally press bonded using
supersonic waves. In this case, if the bonding condition is poor or
the shape of the bonding tool 18 is inadequate, there is the
possibility of a problem in that the bonding strength is low or the
bonding pad for a portion therebelow is subject to damage.
[0238] On the contrary, in the Embodiment 1, the problems, for
example, of bondability or damage caused by the bonding condition
and the shape of the bonding tool 18 as described above can be
overcome by adopting the following feature for the bonding
state.
[0239] That is, FIG. 44 shows an example of using a stud bump 43.
This example has a feature of using a semiconductor chip 1 having
the stud bump 43 formed previously by a plating method or a ball
bonding method onto a bonding pad 7 of the semiconductor chip 1,
causing the bondability to be improved and, further, preventing
damage to the bonding pad.
[0240] Further, FIG. 45 and FIG. 46 are examples of a connection
for the lead 11 using solder and showing a connection state in
which the lead 11 is surrounded with solder 44. This example
concerns a technique for connecting a bonding pad 7 comprising Al
or the like of the semiconductor chip 1 and an electrode of the
tape 9 such as TAB as a CSP substrate. A method of feeding the
solder in this example includes a method of connecting the solder
44 with the bonding pad 7 of the semiconductor chip 1 using the
tape 9 on which the solder 44 is already present so as to surround
the lead 11.
[0241] For the connection method, it is desirable for the shape of
the solder 44 provided on the tape 9, such as a TAB, to be made as
flat as possible at the surface in contact with the bonding pad 7
of the semiconductor chip 1 in the connection method by
pressurizing and heating using a bonder. Further, in a connection
method using a reflow furnace, solder paste or flux is provided at
the surface of the bonding pad 7 of the semiconductor chip 1 so as
to be in contact with the solder 44 of the tape 9, such as a
TAB.
[0242] Then, in the case of feeding the solder 44 using solder
paste, the solder paste may be provided at the surface of the
bonding pad 7 of the semiconductor chip 1 by printing or by using a
syringe. In this case, the tape 9, such as a TAB, may be bonded
previously or subsequently providing that the lead 11 of the tape 9
is in contact with the solder 44 when the tape 9 is bonded to the
semiconductor chip 1.
[0243] Further, FIG. 47, FIG. 48 show a connection technique having
a feature of connecting a lead 11 of a tape 9, such as a TAB, onto
a bonding pad 7 of a semiconductor chip 1 by using a stud bump,
such as a solder or Au ball 45.
[0244] Further, FIG. 49 shows an example of connecting a wiring 10
of a flexible wiring substrate 3 and a bonding pad 7 of a
semiconductor chip 1 by using an Al or solder wire 46. Further,
FIG. 50 shows an example of connecting a wiring 10 of a flexible
wiring substrate 3 and a bonding pad 7 of a semiconductor chip 1 by
using an Au wire 47. In the connection examples, the connection is
enabled not by way of the inner lead bonding, such as a TAB, but
under the concept of a typical wire bonding.
[0245] 11. Lead Design Technique Capable of Forming an S-Shape with
No Tool Return
[0246] To assist in providing an explanation of the lead design
technique capable of forming an S-shape with no tool return, FIG.
17 is a cross sectional view illustrating a trace of a bonding tool
upon forming a standard S-shaped lead as explained previously, FIG.
51 is a perspective view for explaining the lead design, FIG. 52 is
a perspective view illustrating deformation of a lead after
bonding, FIG. 53 is a chart illustrating a relationship between a
lead size and a bending stress ratio and FIG. 76 to Fig. SO are
cross sectional views illustrating the deformed shape of a lead in
accordance with the bending stress ratio.
[0247] More particularly, as explained also in connection with the
technique for the planer S-shaped lead 26 in the technique studied
by the present inventor, it is necessary for forming the S-shaped
configuration of the lead 11 shown in FIG. 17, to laterally
displace the bonding tool 18, namely, a special bonding tool trace
25 including a tool return is required.
[0248] On the contrary, in the Embodiment 1, if the size of a lead
11 shown in FIG. 51 is defined, for example, as shown in FIG. 53,
the bending stress ratio .alpha. will fall within a desired range
of from 1.2 to 1.5 and a suitable S-shaped configuration for the
lead 11 as shown in FIG. 52 can be formed by merely driving down
the bonding tool 18 vertically with no tool return. In FIG. 52,
there are shown a tape end 48, an end 49 on the side of the tape
and an end 50 on the side of the chip.
[0249] For example, in the example of embodiment (1), the bending
stress ratio .alpha.=1.26 at the size: taper length L1=100 .mu.m,
wiring length L2=380 .mu.m, taper width b1=65 .mu.m, lead width
b2=38 .mu.m and lead thickness h=18 .mu.m. In the same manner, the
ratio is 1.25 in the embodiment (2), 1.26 in the embodiment (3),
1.31 in the embodiment (4) and 1.46 in the embodiment (5).
[0250] On the contrary, in the studied technique, at the size:
taper length L1=100 .mu.m, wiring length L2=280 .mu.m, taper width
b1=60 .mu.m, lead width b2=38 .mu.m and lead thickness h=18 .mu.m,
the bending stress ratio .alpha. is 1.02, for example, in the
example (1) and 1.13 in the example (2) which is out of the range
of 1.2 to 1.5.
[0251] As described above, since the bending stress is concentrated
to an intermediate portion of the lead 11 in the wiring operation
within the range of the bending stress ratio .alpha. from 1.2 to
1.5, a moderately distorted satisfactory wiring state is attained.
On the other hand, if the bending stress ratio .alpha. is less than
1.2 as in the studied technique, since the bending stress is
concentrated at the tape end 48 of the lead 11, it results in a
stiffened state. Further, if the ratio exceeds 1.5, the bending
stress is concentrated only at the intermediate portion of the lead
11 resulting in a state of a small radius of curvature which can
not be said to be a satisfactory wiring state.
[0252] FIG. 76 to FIG. 80 show the deformed shape of the lead in
accordance with the bending stress ratio .alpha. concretely. At
first, when the bonding tool 18 is merely driven down vertically to
contact the lead of initial shape before wiring shown in FIG. 76,
since the bending stress is concentrated on the tape end 48 of the
lead 11, for example, in the wiring operation at .alpha.<0.9, an
extremely stiffened wiring state is formed as shown in FIG. 77.
Accordingly, since high repeating stresses are exerted on the lead
11 during the temperature cycle after wiring, the fatigue life is
extremely shortened.
[0253] Further, since the bending stress is concentrated at the
tape end 48 of the lead 11 in the wiring operation at
0.9.ltoreq..alpha.<1.2 as in the technique studied by the
present inventor, a somewhat stiffened wiring state is formed as
shown in FIG. 78. Accordingly, since high repeating stresses are
exerted on the lead 11 during the temperature cycle after the
wiring, fatigue life is shortened.
[0254] On the contrary, since the bending stress is concentrated at
an intermediate portion of the lead 11 during the wiring operation
at 1.2.ltoreq..alpha.<1.5 as in the Embodiment 1, a moderately
distorted wiring state as shown in FIG. 79 is formed. Accordingly,
since no high repeating stresses are exerted on the lead 11 during
the temperature cycle after the wiring, the fatigue life is
increased.
[0255] Further, during wiring operation at 1.5<.alpha. with an
increased bending stress ratio, since the bending ratio is
concentrated only at the intermediate portion of the lead 11, a
wiring state with a small radius of curvature as shown in FIG. 80
is formed. AccordinglY, since the initial strength of the bent
portion is lowered, the fatigue life during the temperature cycle
after wiring is shortened.
[0256] As a result, an optimal wiring state with only a moderately
distorted wiring shape is formed when the bending stress ratio is
set within a range: 1.2.ltoreq..alpha..ltoreq.1.5 as in the
Embodiment 1, and the temperature cycle life of the lead 11 can be
increased.
[0257] The bending stress ratio .alpha. is defined as a value
formed by dividing the stress .sigma.1 generated at the end 49 of
the lead 11 on the side of the tape by a stress .sigma.0 generated
at the tape end 48 of the lead 11 upon conducting the operation of
raising the lead 11 just above the bonding pad 7 with the bonding
tool 18. That is, the bending stress ratio .alpha. can be
represented by the following formula based on the size of the lead
11 having a feature in the tapered shape:
.alpha.=.sigma.1/.sigma.0=b1.times.(L2-L1)/(b2.times.L2)
[0258] As described above, when the size and the shape of the lead
11 are designed such that the bending stress ratio .alpha. is from
1.2 to 1.5, a stable and suitable S-shaped wiring state can be
formed by a simple driving down movement of a wire bonder like that
in the technique for the planer S-shaped lead 26 described
previously. Accordingly, since no special soft-modified wire bonder
is required and the bonding tool trace 25 can also be simplified,
an effect of shortening the contact time upon bonding can also be
expected.
[0259] 12. Ni-Platingless Lead
[0260] To assist in providing a technical explanation of the
Ni-platingless lead, FIG. 54 is a cross sectional view illustrating
a connection portion of the lead, FIG. 55 is an enlarged cross
sectional view illustrating a bent portion of a lead, FIG. 56 is an
enlarged cross sectional view illustrating a bent portion of an
Ni-platingless lead, FIG. 57 is an enlarged cross sectional view
illustrating a press contact portion of a lead and FIG. 58 is an
enlarged cross sectional view illustrating a press-contact portion
of the Ni-platingless lead.
[0261] As an example, in the technique studied by the present
inventor, in the case of a cross sectional structure of a lead 11
in which Ni-plating is applied to a surface of a Cu core and an Au
plating is applied thereon, wherein a Cu core lead is employed
instead of a pure Au lead, since the Ni-plating layer is hard and
brittle, if it is intended to produce an S-shaped lead
configuration, there is the possibility of causing a crack 51 to
occur at the bent portion of the lead 11 as shown in FIG. 55, or
the bonding pad 7 or a portion therebelow may be subjected to
damage 52 as shown in FIG. 57. The Ni-plating is formed as a
barrier layer for preventing Cu atoms from diffusing to the Au
plating surface.
[0262] On the contrary, in the Embodiment 1, since both the
hardness and the brittleness are reduced by using an Ni-platingless
lead 11 in order to obtain the S-shaped configuration, the crack 51
is less likely to form the lead per se and, in addition, the damage
52 to the semiconductor chip 1 at the counter-bonding face can also
be moderated.
[0263] That is, in the connection state of the lead 11 as shown in
FIG. 54, in the lead having the constitution of a Cu core 53+Ni
plating 54+Au plating 55, as shown in FIG. 55 as an enlargement of
the portion A in FIG. 54, the crack 51 is liable to be caused as
the radius of curvature in the bent portion is smaller. On the
other hand, if the surface of the lead 11 is free from the Ni
plating 54 and, for example, is formed only with the Au plating 55
as shown in FIG. 56, the crack 51 is less likely to form at the
bent portion of the lead 11 even if the radius of curvature is
identical with that in FIG. 55.
[0264] Further, also in a press-contact portion of the lead 11 in
FIG. 57, illustrating an enlargement of the portion B in FIG. 54,
the lead 11 has a constitution comprising: Cu core 53+Ni plating
54+Au plating 55, and so damage 52 is liable to be caused at the
periphery of a bonding pad 7. On the other hand, if the surface of
the lead 11 is free from the Ni plating 54 and, for example, is
formed only with the Au plating 55 as shown in FIG. 58, the damage
52 is less likely even in a case of bonding under the same lead
bonding condition.
[0265] As described above, it is possible to suppress the
occurrence of a crack 51 in the lead 11 and moderate the damage 52
to the semiconductor chip 1 while obtaining the S-shaped
configuration, by constituting the lead 11 such that only one
plating layer, for example, an Au plating is formed on the core
material of the Cu core 53.
[0266] Therefore, according to the semiconductor integrated circuit
device in the Embodiment 1, excellent effects can be obtained as
already explained by comparison with the package structure studied
by the present inventor, in the CSP package technique of
substantially the identical size with that of the semiconductor
chip, in each of the technical items, namely: 1. Surface wiring
structure, 2. Optimization of the tape edge position relative to
the elastomer, 3. Optimization of outer size of the package, 4.
Planer S-shaped lead, 5. Beam lead, 6. Peripheral PIQ size of
bonding pad, 7. Improvement of anchor wiring, 8. Wide elastomer
structure, 9. Elastomer groove-fillage technique, 10. Inner lead
bonding technique, 11. Lead design technique capable of forming
S-shaped configuration with no tool return and 12. NI-platingless
lead.
[0267] In the Embodiment 1, although various explanations have been
made with reference to the drawings and the contents of various
techniques on the premise of a particular surface wiring structure,
the technical items 2 to 12 are not limited to the described
surface wiring structure, but the technique of this invention is
applicable also to general package structures, such as a rear face
wiring structure. Accordingly, it can be expected that the same
effect as explained with reference to all of the items can be
obtained when the invention is applied to a general package
structure.
[0268] The package structure of the Embodiment 1 (FIG. 1, FIG. 2)
is shown for a case in which the elastomer 2 is larger than the
outer shape of the semiconductor chip 1. In a case where the
elastomer 2 is smaller than the outer shape of the semiconductor
chip 1, as shown in FIG. 81, an improvement of the moisture
proofness or the like can be obtained by forming a package
structure in which the lateral sides of the semiconductor chip 1
and the elastomer 2 are covered with a sealant 6.
Embodiment 2
[0269] FIG. 59 and FIG. 60 are a cross sectional view and a
perspective view, respectively, illustrating a rear face wiring
solder resist structure in the semiconductor integrated circuit
device of Embodiment 2 according to the present invention.
[0270] The semiconductor integrated circuit device of the
Embodiment 2 is a ball grid array type semiconductor package like
that of the Embodiment 1, but it is different from the Embodiment 1
in that it is not based on the surface wiring technique, but is
based on and provided for improving a rear face wiring structure.
For instance, as shown in FIG. 59 and FIG. 60, in a structure
comprising an elastomer 2 (elastic structural material) bonded on a
main surface of a semiconductor chip (not shown) and a flexible
wiring substrate 3 (wiring substrate) bonded to a main surface of
the elastomer 2, a solder resist 56 (insulation film) is formed on
the rear face of the flexible wiring substrate 3.
[0271] That is, the flexible wiring substrate 3 comprises a tape 9
(substrate base material) serving as a base material for the
flexible wiring substrate 3 and wirings 10 bonded to the rear face
of the tape 9, in which the rear face of the wiring 10 is bonded by
way of the solder resist 56 to the elastomer 2. The solder resist
56 is composed of an insulation material, such as a light sensitive
epoxy resin like that in the Embodiment 1.
[0272] The feature of the package structure of the semiconductor
integrated circuit device in the Embodiment 2 will be explained,
including the structure and the process of manufacture in
comparison with a package structure employing a technique studied
by the present inventor.
[0273] For instance, in the rear face wiring structure shown in
FIG. 7, in the Embodiment 1 as the technique studied by the present
inventor, since the elastomer 2 is formed directly on the main
surface of the wirings 10 of the flexible wiring substrate 3, low
molecular weight ingredients of the elastomer 3 bleed directly to
the lead 11 and if they bleed as far as the bonding point of the
lead 11, there is a likelihood of extremely deteriorating the
bondability (wire bonding stress) due to the contamination.
[0274] Further, compared with the direct plating surface of the
lead 11, the surface of the tape 9 in which the wirings 10 are
etched out between the leads 11 suffers from violent bleeding since
the surface of the tape 9 is roughened also with an aim of
improving the bondability between the tape 9 and the wirings 10,
and bleeding tends to be most violent at the edge portion of the
lead 1 together with the effect of the surface tension.
[0275] Further, in the rear face wiring structure in which the
elastomer 2 is formed on an uneven surface of the wirings 10 caused
by different levels between the portions with or without the
wirings 10, voids are liable to be left, for example, in the gap
between the wirings, which may cause a degrading of the
reliability.
[0276] On the contrary, in the Embodiment 2, since the solder
resist 56 is formed on the wirings 10 after forming the wirings 10
in the manufacturing step for the flexible wiring substrate 3,
direct contact of the elastomer 2 with the wirings 10 can be
prevented. In the same manner, contact of the elastomer 2 to the
roughened surface of the tape 9 can also be prevented. This can
suppress bleeding of the low molecular weight ingredients of the
elastomer 2.
[0277] Further, by coating the solder resist 56 on the uneven
surface of the wirings 10 of the flexible wiring substrate. The
surface of the wirings 10 is flattened to avoid a disadvantage,
such as the creation of voids upon forming the elastomer 2.
[0278] Accordingly, in the semiconductor integrated circuit device
of the Embodiment 2, since the solder resist 56 is formed on the
wirings 10 of the flexible wiring substrate 3 in the CSP
semiconductor package technique based on the rear face wiring
structure, it is possible to prevent the lowering of the
bondability while preventing contamination to the lead 11, thereby
providing a package structure of high reliability with no
voids.
Embodiment 3
[0279] FIG. 61 is a plan view of a semiconductor integrated circuit
device forming an Embodiment 3 according to the present invention,
as viewed from the rear face of a semiconductor chip, FIG. 62 is a
plan view thereof, FIG. 63 is a cross sectional view thereof, FIG.
63 is an enlarged cross sectional view of a portion A in FIG. 63
and FIG. 65 is a plan view for explaining the wiring structure of
the wiring substrate.
[0280] A semiconductor integrated circuit device in the Embodiment
3 adopts, instead of a semiconductor package having a structure in
which the bonding pad is formed approximately at the center of the
chip, as in the Embodiments 1 and 2 described above, a packaging
structure using a semiconductor chip 1a in which a pad is formed to
the periphery of the chip, as shown in FIG. 61 to FIG. 65, and in
which bumps 5a connected to the bonding pads to the semiconductor
chip 1a are disposed in a region inward of the outer circumference
of the semiconductor chip 1a. The Embodiment 3 also has a structure
which adopts the techniques from "1. Surface wiring structure" to
"12. Ni-platingless lead" of Embodiment 1, as well as the technical
features of each of the technical items for the rear face wiring
solder resist structure as explained with reference to the
Embodiment 2.
[0281] That is, the semiconductor integrated circuit device in the
Embodiment 3 is, for example, a 24 pin ball grid array type
semiconductor package structure, in which an elastomer 2a (elastic
structural material), a flexible wiring substrate 3a (wiring
substrate) having wirings 10a formed on a tape 9a and a solder
resist 4a (insulation film) are disposed on a main surface of a
semiconductor chip 1a formed with a plurality of bonding pads 7a
(external terminals), solder bumps 5a (bump electrodes) are formed
to an opening of the solder resist 4a, and a portion for forming
the bonding pads 7a and lateral sides of the elastomer 2a and the
flexible wiring substrate 3a are covered with a sealant 6a.
[0282] The semiconductor chip 1a has a peripheral pad structure,
for example, as shown in FIG. 65, in which a plurality of bonding
pads 7a are arranged in a square pattern along the outer
circumference of the semiconductor chip 1a. Each bonding pad 7a of
the semiconductor chip 1a is connected electrically with a solder
bump 5a by way of the wiring 10a of the flexible wiring substrate
3a, which is connected at one end of the lead 11a to the pad 7a and
joined at the bump land 12a at the other end of the wiring 10a to
the bump 5a. The solder bumps 5a are arranged as a 6 row.times.4
column matrix in a region inward of the arrangement for the bonding
pads 7a.
[0283] Accordingly, in the semiconductor integrated circuit device
of the Embodiment 3, excellent effects can be obtained for each of
the technical items as explained for the Embodiments 1 and 2,
although there is a difference in the semiconductor package
structure relating to the fan-in peripheral pads. Particularly, in
the fan-in package structure, a CSP structure package about the
same size as the semiconductor chin 1a can be attained similar to
that in the Embodiments 1 and 2.
Embodiment 4
[0284] FIG. 66 is a plan view of a semiconductor integrated circuit
device forming an Embodiment 4 of the present invention as viewed
from the rear face of the semiconductor chip, FIG. 67 is a plan
view thereof, FIG. 68 is a cross sectional view thereof, FIG. 69 is
an enlarged cross sectional view illustrating a portion A in FIG.
68 and FIG. 70 is a plan view for explaining the wiring structure
of a wiring substrate.
[0285] The semiconductor integrated circuit device of the
Embodiment 4 adopts, instead of a semiconductor package having a
structure in which the bump electrodes are disposed in the chip
area as in the Embodiments 1 and 2, a package structure using a
semiconductor chip 1b of a peripheral pad structure as shown in
FIG. 66 to FIG. 70, in which bumps 5b connected to the bonding pads
of the semiconductor chip 1b are disposed to a region outward of
the outer circumference of the semiconductor chip 1b. This
Embodiment 4 also has a structure for adopting the technique from
"1. Surface wiring structure" to "12. Ni-platingless lead", as
explained for the Embodiment 1, as well as the features for each of
the technical items of the rear face wiring solder resist structure
explained for the Embodiment 2, respectively.
[0286] That is, the semiconductor integrated circuit device of the
Embodiment 4 has, for example, a 80 pin ball grid array type
semiconductor type package structure in which an elastomer 2b
(elastic structural material), a flexible wiring substrate 3b
(wiring substrate) having wirings 10b formed on a tape 9b, and a
solder resist 4b (insulation film) are disposed on a main surface
of a semiconductor chip 1b formed with a plurality of bonding pads
7b (external terminals), solder bumps 5b (bump electrodes) are
formed to an opening portion of the solder resist 4b, portions for
forming bonding pads 7b are covered with the sealant 6b, and a
support ring 57b is disposed to the lateral side of the
semiconductor chip 1b to constitute a package structure.
[0287] The semiconductor chip 1b has a peripheral pad structure,
for example, as shown in FIG. 70, and a plurality of bonding pads
7b are arranged in a square pattern along the outer circumference
of the semiconductor chip 1b. Each bonding pad 7b of the
semiconductor chip 1b is connected electrically with a solder bump
5b by way of the wiring 10b of the flexible wiring substrate 3b,
which is connected at one end of the lead 11b with the pad 7b and
joined at the bump land 12b at the other end with the bump 5b. The
solder bumps 5b are arranged in two rows in a square pattern
concentric to the arrangement of the bonding pads 7b of the
semiconductor chip 1b.
[0288] Accordingly, the semiconductor integrated circuit device of
the embodiment 4 can also provide excellent effects for each of the
technical items as explained for the Embodiments 1 and 2, although
having a different semiconductor package structure of fan-out
peripheral pad configuration. Particularly, the fan-out package
structure can provide a package structure corresponding to
multi-pin arrangements, although the size of the semiconductor
package is increased compared with the Embodiments 1 and 2.
Embodiment 5
[0289] FIG. 71 is a plan view of a semiconductor integrated circuit
device forming an Embodiment 5 of the present invention as viewed
from the rear face of the semiconductor chip, FIG. 72 is a plan
view thereof, FIG. 73 is a cross sectional view thereof, FIG. 74 is
an enlarged cross sectional view illustrating a portion A in FIG.
73 and FIG. 75 is a plan view for explaining the wiring structure
of a wiring substrate. In FIG. 75, a portion, such as a number of
the bonding pads and solder bumps, is omitted for simplification in
order to make the arrangement of the wirings clearer.
[0290] The semiconductor integrated circuit device of the
Embodiment 5 adopts, instead of a semiconductor package having a
structure in which bump electrodes are disposed in the area of the
chip as in the Embodiments 1 and 2, a package structure using a
peripheral pad structure semiconductor chip 1c as shown in FIG. 71
to FIG. 75, in which solder bumps 5c connected to the bonding pads
of the semiconductor chip 1c are disposed both in inner and outer
regions of the semiconductor chip 1c. This Embodiment 5 also has a
structure adopting the technique from "1. Surface wiring" to "12.
Ni-platingless lead" as explained for the Embodiment 1, as well as
features for each of the technical items of the rear face wiring
solder resist structure, as explained for the Embodiment 2.
[0291] That is, the semiconductor integrated circuit device in the
Embodiment 5 is, for example, a 110 pin ball grid array type
semiconductor package structure in which an elastomer 2c (elastic
structural material), a flexible wiring substrate 3c (wiring
substrate) having wirings 10c formed on a tape 9c, and a solder
resist 4c (insulation film) on a main surface of a semiconductor
chip 1c formed with a plurality of bonding pads 7c (external
terminals), solder bumps 5c (bump electrodes) are formed to an
opening portion of the solder resist 4c, a portion of forming the
bonding pads 7c is covered with a sealant 6c and a support ring 57c
is disposed to the lateral sides of the semiconductor chip 1c.
[0292] The semiconductor chip 1c has a peripheral pad structure,
for example, as shown in FIG. 75 (actual arrangement in FIG. 72) in
which a plurality of bonding pads 7c are arranged in a square
pattern along the outer circumference of the semiconductor chip 1c.
Each bonding pad 7c of the semiconductor chip 1c is electrically
connected to a solder bump 5c by way of the wiring 10c of the
flexible wiring substrate 3c that is connected by a lead 11c at one
end to the pad 7c and joined to the bump 5c at the bump land 12c at
the other end of the wiring 10c. The solder bumps 5c are arranged
as 6 row.times.5 column array in a region inward of the arrangement
of the bonding pads 7c of the semiconductor chip 1c, and is
arranged in two rows in a square pattern also in the outer
region.
[0293] Accordingly, the semiconductor integrated circuit device of
the Embodiment 5 can also obtain the same excellent effect in each
of the technical items as explained for the Embodiments 1 and 2,
although there is a difference in the semiconductor package
structure. Particularly, in the fan-in/out package structure, a
package structure capable of coping with multi-pin arrangements can
be adopted, although the size of the semiconductor package is
enlarged compared with the Embodiments 1 and 2.
[0294] While the invention made by the present inventor has been
explained with reference to the Embodiments 1-5 of the invention,
the present invention is not restricted only to those embodiments,
but it will be apparent that various modifications are possible
within a range not departing from the gist thereof.
[0295] For example, the techniques in the Embodiments 1-5 can be
combined as required.
[0296] The number of the solder bumps serving as external
connection terminals of the semiconductor package and the bonding
pads serving as external terminals of the semiconductor chip
electrically connected with the solder bumps are not restricted
only to those described in connection with the embodiments, but
they may be properly modified depending on or in accordance with
the specification of the packages, such as the integrated circuits
formed on the semiconductor chip.
[0297] Further, regarding the materials, for example, for the
elastomer forming the elastic structural material, the tape for the
flexible wiring substrate, the wiring and lead plating, the solder
resist serving as the insulation film and the solder bump serving
as a bump electrode, the invention is also applicable in a case of
using other materials having respective properties.
[0298] For example, as the solder resist, there can be mentioned a
resin mixture comprising an acrylic resin and an epoxy resin, the
resin mixture described above with addition of a filler, melamine,
acryl, polystyrol and polyimide, as well as polyurethane and
silicone; although, it is necessary that they have a property of
withstanding the soldering temperature and have a resistance to the
exposure of a flux and a cleaning solvent.
[0299] Advantageous effects obtained by typical examples among
those disclosed in accordance with the present invention are
briefly explained below.
[0300] (1) Since the elastic structural material is disposed on the
flat surface on the rear face of the substrate base material by
adopting a surface wiring structure in which the elastic structural
material is disposed on the rear face of the substrate base
material of the wiring substrate, and the insulation film is formed
on the main surface of the wirings formed on the main surface of
the substrate base material, the elastic structural material can be
mounted with a higher accuracy and stably to the substrate base
material in a voidless manner and, since the size and the shape of
the elastic structural material are made stable, the bonding step
for the semiconductor chip is also stable, thereby enabling
assembling at a higher yield.
[0301] (2) Since the signal wiring layer and the power source
ground wiring layer can be separated into different layers by
making the wirings of the wiring substrate into a multi-wiring
layer structure, an excellent electric characteristic in view of
noise resistance can be attained.
[0302] (3) Since external terminals of the semiconductor chip can
be disposed at the central portion or the peripheral portion, and
the bump electrodes connected to the external terminals can be
disposed to the inside, outside or both of the regions outward of
the outer circumference of the semiconductor chip, the invention is
applicable to package structures of various types and
variations.
[0303] (4) Since the edge position of the substrate base material
can be optimized relative to the elastic structural material by
setting the distance between the end of the elastic structural
material of the semiconductor chip on the side of the external
terminals and the end of the substrate base material of the wirings
substrate based on the ingredients of the elastic structural
material, a variation in the height of the bump electrodes is not
caused, thereby avoiding any difficulty in filling the sealant
caused by an enlarged sealing region for the opening of the elastic
structural material and it is possible to prevent contamination of
wirings caused by the bleeding of ingredients or evaporative
ingredients of the elastic structural material.
[0304] (5) Since the outer size of the package can be optimized by
setting the relation for the distance M2 between the end of the
substrate base material of the wiring substrate and the end of the
elastic structural material and for the distance M1 between the end
of the semiconductor chip and the end of the substrate base
material at the outer circumference of the semiconductor integrated
circuit device within a range: M1>M2>0, the outermost
circumference of the package is not formed by the semiconductor
chip, so that a possibility of inducing chip cracks is reduced
during the assembling step, as well as during withdrawal and
insertion of receptacles and tray transportation, and the circuit
surface of the semiconductor chip is not exposed to the outside,
thereby making it possible to improve the reliability. Further,
since the peripheral protrusions of the elastic structural material
after printing do not interfere with the bonding portion of the
semiconductor chip, it is possible to prevent bonding failure upon
appending the chip, worsening of the flatness of the wiring
substrate and lowering of the reliability.
[0305] (6) Since the planer S-shaped wiring can be obtained by
forming the wiring of the wiring substrate such that the fixed
portion with the substrate base material and top end portion
connected to the external terminal of the semiconductor chip are
displaced at least by more than the width of the wiring, a stable
and suitable S-shaped lead can be formed because a sag due to the
original planer S-shaped configuration can be obtained by a simple
driving down movement of a typical wire bonder, so that a stable
S-shaped configuration can be formed for the lead with no
requirement of a soft-modified special wire bonder, and further,
the contact time upon bonding can also be shortened since the
bonding tool trace can also be simplified.
[0306] (7) Since the beam wiring can be attained by forming the
wiring of the wiring substrate as a cantilever structure which is
fixed at one end to the substrate base material, it is possible to
overcome such problems as occur in notched wirings wherein cutting
is often impossible during bonding due to the variation of the size
of the notches and, even if the wiring can be cut, it may be cut at
a portion different from the desired notch, or it may be cut before
the plating step for the wiring substrate because of the
excessively narrowed portion, thereby failing to deposit
plating.
[0307] (8) Since the end of the opening of the surface protection
film on the semiconductor chip is set to a size within a range
wherein the wiring does not interfere with the surface protection
film when the bonding tool is driven down, it is possible to
overcome the problem that the surface protection film or the
semiconductor chip suffers from damages (on the semiconductor chip)
by the driving down pressure of the tool, and the ingredients of
the surface protection film are prevented from being deposited on
the bonding portion at the lower surface of the lead to cause
contamination and to worsen the bondability.
[0308] (9) Since the effective area of the wired portion can be
enlarged by connecting the wiring on the notch terminal end of the
wiring substrate to an opposing land portion of the wiring,
longitudinally or laterally extending the wiring in the vacant
regions of the wirings or connecting the adjacent wirings to each
other, it is possible to increase the bonding strength between the
wiring and the substrate base material and obtain a stable notch
cutting performance.
[0309] (10) Since a wide elastic material structure can be attained
by forming the elastic structural material in a larger range over
the entire circumference at least by more than the width of the
protrusions on the outer circumference formed in the elastic
structural material as compared with the outer size of the
semiconductor chip, protrusions on the periphery of the elastic
structural member are located outside of the semiconductor chip
after the appending of the semiconductor chip, and it can be bonded
substantially on the flat portion of the elastic structural
material, whereby the warping of the wiring substrate is
suppressed. Further, since a large coating area of adhesive can be
provided, a not bonded portion caused by insufficient adhesive is
less likely to occur, and the adhesive tends to extrude out
uniformly around the periphery of the semiconductor chip, so that a
package of excellent moisture proofness and reliability can be
constituted with out applying an additional peripheral sealing.
[0310] (11) In a case of forming the elastic structural material as
divided portions which are spaced so as to be not bonded on the
external terminals of the semiconductor chip, when each end of the
spaces at which the divided elastic structural materials are
opposed is formed as a grooved shape, the metal mask bridge portion
can be restricted to narrow the groove of the elastic structural
material in the groove-fillage technique of the elastic structural
material, so that the groove-fillage of the elastic structural
material can be improved.
[0311] (12) If a plurality of grooves are formed at each of the
ends of the elastic structural material, the strength of the
groove-forming metal mask can be improved.
[0312] (13) When a stopping dam for sealant flow is previously
formed at the grooves at each of the ends of the spaces at which
the divided structural materials are opposed, the groove-fillage in
the sealing step can further be improved.
[0313] (14) By previously forming stud bumps on the external
terminals of the semiconductor chip and connecting the external
terminals of the semiconductor chip and the wirings of the wiring
substrate by way of the stud bumps, problems for in the bondability
and the possibility of damage can be solved in the inner lead
bonding technique, whereby the bondability is improved by the stud
bumps and, further, the possibility of damage can be prevented.
[0314] (15) By supplying the solder so as to previously surround
the wirings of the wiring substrate and connecting the external
terminals of the semiconductor chip and the external terminals of
the wiring substrate by way of the solder, bondability can be
improved and damage can be suppressed in the bonding technique.
[0315] (16) By using the stud bumps, for example, made of solder or
Au so as to surround the wirings of the wiring substrate, and by
connecting the wirings of the wiring substrate and the external
terminals of the semiconductor chip by way of the stud bumps, the
bondability can be improved and the possibility of damage can be
suppressed in the bonding technique.
[0316] (17) By connecting the wirings of the wiring substrate and
the external terminals of the semiconductor chip by using an Al,
solder or Au wire, the problem, for example, of bondability or
damage can be solved, and it is possible to attain connection by
the concept of a typical wire bonding, not by the inner lead
bonding, such as a TAB.
[0317] (18) By forming the lateral size of the wiring of the wiring
substrate such that the size is gradually narrowed from the end of
the substrate base material of the wiring substrate to the top end
of the wiring and the lateral size is made constant from a
predetermined position, and setting the size and the shape of the
wiring such that the bending stress ratio .alpha. is from 1.2 to
1.5, since a suitable S-shaped configuration can be formed by
merely driving down the bonding tool vertically with no return of
the bonding tool, a lead of a stably shaped configuration can be
formed without requiring a special soft-modified wire bonder; and,
further, the contact time upon bonding can also be shortened since
the trace of the bonding tool can be simplified.
[0318] (19) By using the electroconductive material as a core
material for the wiring structure of the wiring substrate and
applying only Au plating to the surface, since both the hardness
and the brittleness of the lead are lowered as compared with a case
of applying Ni-plating between the core material of the conductive
material, such as Cu and Au plating, cracks are less likely in the
lead itself, and damage to the semiconductor chip at the counter
bonding face can also be moderated.
[0319] (20) By forming the wirings on the rear face of the
substrate base material of the wiring substrate, forming the
insulation film on the rear face of the wirings and disposing the
elastic structure material on the rear face of the insulation film,
since a rear face wiring insulation film structure can be obtained,
direct contact of the elastic structural material with the wiring
can be prevented and contact of the elastic structural material to
the roughened surface of the substrate base material can also be
prevented, so that bleeding of the low molecular weight ingredients
of the elastic structure material can be suppressed and, further,
the uneven wiring surface can be flattened by coating the
insulation film making it possible to avoid disadvantages, such as
the creation of voids upon forming the elastic structural
material.
[0320] (21) In the surface wiring structure, since the opening of
the insulation film is formed by defining the coating range of the
insulation film material, the fabrication accuracy for the hole
diameter can further be improved as compared with a case of forming
the opening by machining the substrate base material of the wiring
substrate of the rear face wiring structure.
[0321] (22) By setting the thickness of the insulation film by
determining the coating condition for the insulation film material
in the surface wiring structure, since the film can be coated
stably at a further reduced thickness and the bump land disposed at
a higher density with a small diameter can be formed as compared
with the substrate base material, a smaller bump electrode can be
joined more satisfactorily.
[0322] (23) In the surface wiring structure, since the pitch for
the arrangement of the bump electrodes can be reduced as compared
with the rear face wiring structure, it is possible lo constitute a
semiconductor package having output terminals at higher
density.
* * * * *