Substrate for an electronic circuit

Description

FIG. 1 is a front, bottom and right side perspective view of a substrate for an electronic circuit, showing our new design;

FIG. 2 is a rear, bottom and left side perspective view thereof;

FIG. 3 is a front view thereof;

FIG. 4 is a rear view thereof;

FIG. 5 is a top view thereof;

FIG. 6 is bottom view thereof;

FIG. 7 is a right side view thereof, the left side being symmetrical;

FIG. 8 is a cross sectional view thereof, taken along line 8-8 in FIG. 3; and,

FIG. 9 is a cross sectional view thereof, taken along line 9-9 in FIG. 3.

The broken line portion of the figure drawings is included to show portions of the article that form no part of the claimed design.

Claims

CLAIM The ornamental design for a substrate for an electronic circuit, as shown and described.

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Inventors:	Matsumoto; Manabu (Yokohama, JP), Toyoda; Yasumasa (Yokohama, JP)
Applicant:	Name City State Country Type Kabushiki Kaisha Toshiba Minato-ku, Tokyo N/A JP
Assignee:	Kabushiki Kaisha Toshiba (Tokyo, JP)
Appl. No.:	D/533,041
Filed:	July 14, 2015

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Foreign Application Priority Data

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Jan 14, 2015 [JP]			2015-000436

Current U.S. Class:	D13/182
Current International Class:	1303
Field of Search:	;D13/110,118,123,133,146,147,173,182,184,199 ;D14/436

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References Cited [Referenced By]

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U.S. Patent Documents

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Foreign Patent Documents

	1104233		Mar 2001		JP
	1152236		Sep 2002		JP
	1287854		Dec 2006		JP
	1426166		Oct 2011		JP
	1436226		Mar 2012		JP
	1479369		Sep 2013		JP
	1479370		Sep 2013		JP
	1486344		Dec 2013		JP

Primary Examiner: Johannes; Thomas
Assistant Examiner: Gingrich; Shawn T
Attorney, Agent or Firm: Banner & Witcoff, Ltd.