Substrate for an electronic circuit

Description

FIG. 1 is a perspective view of a substrate for an electronic circuit showing our new design;

FIG. 2 is a rear perspective view thereof;

FIG. 3 is a front elevational view thereof;

FIG. 4 is a rear elevational view thereof;

FIG. 5 is a right side elevational view, a left side elevational view being a mirror image thereof;

FIG. 6 is a top plan view thereof; and,

FIG. 7 is a bottom plan view thereof.

The broken lines shown in the drawings represent portions of the substrate for an electronic circuit that form no part of the claimed design.

Claims

CLAIM The ornamental design for a substrate for an electronic circuit, as shown and described.

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Inventors:	Matsumoto; Manabu (Yokohama, JP), Ozawa; Isao (Chigasaki, JP)
Applicant:	Name City State Country Type Kabushiki Kaisha Toshiba Minato-ku, Tokyo N/A JP
Assignee:	Kabushiki Kaisha Toshiba (Minato-ku, Tokyo, JP)
Appl. No.:	D/564,531
Filed:	May 13, 2016

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Related U.S. Patent Documents

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	Application Number	Filing Date	Patent Number	Issue Date
	29500896	Aug 29, 2014	D764424

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Foreign Application Priority Data

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May 15, 2014 [JP]			2014-010418
May 15, 2014 [JP]			2014-010419
May 15, 2014 [JP]			2014-010420
May 15, 2014 [JP]			2014-010421

Current U.S. Class:	D13/182
Current International Class:	1303
Field of Search:	;D13/182,123,133,110,184,199 ;257/177,666,684,689,775 ;361/600,601,820 ;29/825,829,830,831,832 ;174/68.1,250,253,254,260,261,268 ;216/13 ;428/901 ;D5/4,61

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References Cited [Referenced By]

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Foreign Patent Documents

	488834		May 2002		CN
	1104233		Mar 2001		JP
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	1479370		Sep 2013		JP
	30-0470075		Nov 2007		KR

Primary Examiner: Oswecki; Elizabeth J
Attorney, Agent or Firm: Banner & Witcoff, Ltd.