U.S. patent application number 16/903458 was filed with the patent office on 2020-10-01 for chip scale package structure and method of forming the same.
The applicant listed for this patent is MEDIATEK INC.. Invention is credited to Yen-Yao CHI, Wen-Sung HSU, Shih-Chin LIN, Tzu-Hung LIN, Nai-Wei LIU, Ta-Jen YU.
Application Number | 20200312732 16/903458 |
Document ID | / |
Family ID | 1000004930579 |
Filed Date | 2020-10-01 |
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United States Patent
Application |
20200312732 |
Kind Code |
A1 |
CHI; Yen-Yao ; et
al. |
October 1, 2020 |
CHIP SCALE PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME
Abstract
A semiconductor package structure includes a semiconductor die,
a redistribution layer (RDL) structure, a protective insulating
layer, and a conductive structure. The semiconductor die has a
first surface, a second surface opposite the first surface, and a
third surface adjoined between the first surface and the second
surface. The RDL structure is on the first surface of the
semiconductor die and is electrically coupled to the semiconductor
die. The protective insulating layer covers the RDL structure, the
second surface and the third surface of the semiconductor die. The
conductive structure passes through the protective insulating layer
and is electrically coupled to the RDL structure.
Inventors: |
CHI; Yen-Yao; (Hsinchu City,
TW) ; LIU; Nai-Wei; (Hsinchu City, TW) ; YU;
Ta-Jen; (Hsinchu City, TW) ; LIN; Tzu-Hung;
(Hsinchu City, TW) ; HSU; Wen-Sung; (Hsinchu City,
TW) ; LIN; Shih-Chin; (Hsinchu City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
MEDIATEK INC. |
Hsinchu City |
|
TW |
|
|
Family ID: |
1000004930579 |
Appl. No.: |
16/903458 |
Filed: |
June 17, 2020 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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16430076 |
Jun 3, 2019 |
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16903458 |
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62731128 |
Sep 14, 2018 |
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62881441 |
Aug 1, 2019 |
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62881434 |
Aug 1, 2019 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 23/293 20130101;
H01L 23/3135 20130101; H01L 21/561 20130101; H01L 2224/02379
20130101; H01L 2224/02381 20130101; H01L 2224/05569 20130101; H01L
21/568 20130101; H01L 23/3185 20130101; H01L 2224/024 20130101;
H01L 2224/0401 20130101; H01L 2224/12105 20130101; H01L 23/3171
20130101; H01L 24/13 20130101; H01L 2224/02377 20130101; H01L
23/3114 20130101; H01L 2224/02331 20130101; H01L 23/3192 20130101;
H01L 2224/13024 20130101; H01L 24/05 20130101 |
International
Class: |
H01L 23/31 20060101
H01L023/31; H01L 23/29 20060101 H01L023/29; H01L 23/00 20060101
H01L023/00; H01L 21/56 20060101 H01L021/56 |
Claims
1. A semiconductor package structure, comprising: a semiconductor
die having a first surface, a second surface opposite the first
surface, and a third surface adjoined between the first surface and
the second surface; a redistribution layer (RDL) structure on the
first surface of the semiconductor die and electrically coupled to
the semiconductor die; a protective insulating layer covering the
RDL structure, the second surface and the third surface of the
semiconductor die; and a conductive structure passing through the
protective insulating layer and electrically coupled to the RDL
structure.
2. The semiconductor package structure as claimed in claim 1,
further comprising a passivation layer between the RDL structure
and the protective insulating layer and covered by the protective
insulating layer, wherein the conductive structure passes through
the passivation layer.
3. The semiconductor package structure as claimed in claim 1,
further comprising a passivation layer between the first surface of
the semiconductor die and the RDL structure, wherein the RDL
structure passes through the passivation layer.
4. The semiconductor package structure as claimed in claim 1,
further comprising: a first passivation layer between the first
surface of the semiconductor die and the RDL structure, wherein the
RDL structure passes through the first passivation layer; and a
second passivation layer between the RDL structure and the
protective insulating layer and covered by the protective
insulating layer, wherein the conductive structure passes through
the second passivation layer.
5. The semiconductor package structure as claimed in claim 4,
wherein the first passivation layer comprises a material that is
the same as a material of the second passivation layer and
different from a material of the protective insulating layer.
6. The semiconductor package structure as claimed in claim 4,
wherein the first passivation layer and the second passivation
layer respectively comprise polyimide or polybenzoxazole (PBO).
7. The semiconductor package structure as claimed in claim 1,
wherein the protective insulating layer comprises an epoxy molding
compound (EMC), an Ajinomoto.TM. Build-up Film (ABF), or an
acrylic-based material.
8. The semiconductor package structure as claimed in claim 1,
wherein the conductive structure comprises an under-bump metallurgy
(UBM) layer and a solder bump on the UBM layer, or a solder bump on
the first passivation layer.
9. A semiconductor package structure, comprising: a semiconductor
die having a first surface, a second surface opposite the first
surface, and a third surface adjoined between the first surface and
the second surface; a first protective insulating layer covering
the first surface and the third surface of the semiconductor die; a
first redistribution layer (RDL) structure over the first surface
of the semiconductor die and electrically coupled to the
semiconductor die and extending to directly above the first
protective insulating layer; a first passivation layer covering the
first protective insulating layer and the first RDL structure; and
a plurality of conductive structures passing through the first
passivation layer and electrically coupled to the first RDL
structure.
10. The semiconductor package structure as claimed in claim 9,
further comprising a second RDL structure between the first RDL
structure and the first surface of the semiconductor die and
electrically coupled to the semiconductor die.
11. The semiconductor package structure as claimed in claim 10,
wherein the second RDL structure is surrounded by the first
protective insulating layer on the first surface of the
semiconductor die.
12. The semiconductor package structure as claimed in claim 10,
wherein the first RDL structure is electrically coupled to the
semiconductor die through the second RDL structure.
13. The semiconductor package structure as claimed in claim 10,
further comprising a second passivation layer between the second
RDL structure and the first surface of the semiconductor die,
wherein the second RDL structure passes through the second
passivation layer.
14. The semiconductor package structure as claimed in claim 13,
wherein the second passivation layer is surrounded by the first
protective insulating layer on the first surface of the
semiconductor die.
15. The semiconductor package structure as claimed in claim 13,
wherein the second passivation layer comprises a material that is
the same as a material of the first passivation layer and different
from a material of the first protective insulating layer.
16. The semiconductor package structure as claimed in claim 9,
further comprising a second passivation layer between the first RDL
structure and the first protective insulating layer, wherein the
first RDL structure passes through the second passivation
layer.
17. The semiconductor package structure as claimed in claim 16,
wherein the second passivation layer comprises a material that is
the same as a material of the first passivation layer and different
from a material of the first protective insulating layer.
18. The semiconductor package structure as claimed in claim 9,
further comprising a second protective insulating layer covering
the second surface of the semiconductor die.
19. The semiconductor package structure as claimed in claim 18,
wherein the first protective insulating layer and the second
protective insulating layer comprise the same material.
20. The semiconductor package structure as claimed in claim 18,
wherein the first protective insulating layer and the second
protective insulating layer respectively comprise an epoxy molding
compound (EMC), an Ajinomoto.TM. Build-up Film (ABF), or an
acrylic-based material.
21. The semiconductor package structure as claimed in claim 9,
wherein the conductive structure comprises an under-bump metallurgy
(UBM) layer and a solder bump on the UBM layer, or a solder bump on
the first passivation layer.
22. A semiconductor package structure, comprising: a semiconductor
die having a first surface, a second surface opposite the first
surface, and a third surface adjoined between the first surface and
the second surface; a first redistribution layer (RDL) structure on
the first surface of the semiconductor die and electrically coupled
to the semiconductor die; a first protective insulating layer
covering the first surface and the third surface of the
semiconductor die and surrounding the first RDL structure; a first
passivation layer covering the first protective insulating layer
and the first RDL structure; a second RDL structure electrically
coupled to the semiconductor die through the first RDL structure,
wherein the second RDL structure extends from the first RDL
structure to above the first protective insulating layer; a second
passivation layer covering the second RDL structure; and a
plurality of conductive structures passing through the second
passivation layer and electrically coupled to the second RDL
structure.
23. The semiconductor package structure as claimed in claim 22,
further comprising a second protective insulating layer covering
the second surface of the semiconductor die.
24. The semiconductor package structure as claimed in claim 22,
further comprising a third passivation layer between the first
surface of the semiconductor die and the first RDL structure,
wherein the first RDL structure passes through the third
passivation layer.
25. The semiconductor package structure as claimed in claim 24,
wherein the third passivation layer is surrounded and covered by
the first protective insulating layer.
26. The semiconductor package structure as claimed in claim 24,
wherein the first passivation layer, the second passivation layer
and the third passivation layer comprise a material that is
different from a material of the first protective insulating
layer.
27. The semiconductor package structure as claimed in claim 24,
wherein the first passivation layer, the second passivation layer
and the third passivation layer respectively comprise polyimide or
polybenzoxazole (PBO).
28. The semiconductor package structure as claimed in claim 22,
wherein the conductive structure comprises an under-bump metallurgy
(UBM) layer and a solder bump on the UBM layer, or a solder bump on
the second passivation layer.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a Continuation-In-Part of application
Ser. No. 16/430,076 filed on Jun. 3, 2019, which claims the benefit
of U.S. Provisional Application No. 62/731,128 filed on Sep. 14,
2018, the entirety of which is incorporated by reference herein.
This application also claims the benefit of U.S. Provisional
Application No. 62/881,434 filed on Aug. 1, 2019, the entirety of
which is incorporated by reference herein. This application also
claims the benefit of U.S. Provisional Application No. 62/881,441
filed on Aug. 1, 2019, the entirety of which is incorporated by
reference herein.
BACKGROUND OF THE INVENTION
Field of the Invention
[0002] The present invention relates to semiconductor package
technology, and in particular to a wafer level chip scale package
(WLCSP) structure.
Description of the Related Art
[0003] Integrated circuit (IC) devices are fabricated in a
semiconductor wafer and divided into individual chips. Afterwards,
those chips are assembled in package form to be used in electronic
products. The package provides a structure to support the chip and
protect the chip from the environment. The package also provides
electrical connections to and from the chip.
[0004] In recent years, as electronic products have become
increasingly multifunctional and have been scaled down in size,
there is a desire for manufacturers of semiconductor devices to
make more devices formed on a single semiconductor wafer, so that
the electronic products that include these devices can be made more
compact. This results in many new challenges to the structural and
electrical design of the package.
[0005] Accordingly, a chip scale package (CSP) technology has been
developed to satisfy the industry's demands (e.g., the smaller chip
size and form factor). Moreover, a wafer level package (WLP)
technology has also been introduced for the cost-effective
fabrication of packages. Such a technology is referred to as
wafer-level chip scale package (WLCSP).
[0006] However, in the use of the WLCSP process, the surface of
each chip in the respective package is exposed to the environment
after the packages are separated from the package wafer. As a
result, damage to the chip may occur, thereby reducing the
reliability of the semiconductor packages. Thus, a novel
semiconductor package structure and a fabrication method thereof
are desirable.
BRIEF SUMMARY OF THE INVENTION
[0007] Semiconductor package structures are provided. An exemplary
embodiment of a semiconductor package structure includes a
semiconductor die, a redistribution layer (RDL) structure, a
protective insulating layer, and a conductive structure. The
semiconductor die has a first surface, a second surface opposite
the first surface, and a third surface adjoined between the first
surface and the second surface. The RDL structure is on the first
surface of the semiconductor die and is electrically coupled to the
semiconductor die. The protective insulating layer covers the RDL
structure, the second surface and the third surface of the
semiconductor die. The conductive structure passes through the
protective insulating layer and is electrically coupled to the RDL
structure.
[0008] Another exemplary embodiment of a semiconductor package
structure includes a semiconductor die, a first protective
insulating layer, a first redistribution layer (RDL) structure, a
first passivation layer, and a plurality of conductive structures.
The semiconductor die has a first surface, a second surface
opposite the first surface, and a third surface adjoined between
the first surface and the second surface. The first protective
insulating layer covers the first surface and the third surface of
the semiconductor die. The first RDL structure is over the first
surface of the semiconductor die and is electrically coupled to the
semiconductor die and extends to directly above the first
protective insulating layer. The first passivation layer covers the
first protective insulating layer and the first RDL structure. The
plurality of conductive structures passes through the first
passivation layer and is electrically coupled to the first RDL
structure.
[0009] Yet another exemplary embodiment of a semiconductor package
structure includes a semiconductor die, a first redistribution
layer (RDL) structure, a first protective insulating layer, a first
passivation layer, a second RDL structure, a second passivation
layer, and a plurality of conductive structures. The semiconductor
die has a first surface, a second surface opposite the first
surface, and a third surface adjoined between the first surface and
the second surface. The first RDL structure is on the first surface
of the semiconductor die and is electrically coupled to the
semiconductor die. The first protective insulating layer covers the
first surface and the third surface of the semiconductor die and
surrounds the first RDL structure. The first passivation layer
covers the first protective insulating layer and the first RDL
structure. The second RDL structure is electrically coupled to the
semiconductor die through the first RDL structure, wherein the
second RDL structure extends from the first RDL structure to above
the first protective insulating layer. The second passivation layer
covers the second RDL structure. The plurality of conductive
structures passes through the second passivation layer and is
electrically coupled to the second RDL structure.
[0010] A detailed description is given in the following embodiments
with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The present invention can be more fully understood by
reading the subsequent detailed description and examples with
references made to the accompanying drawings, wherein:
[0012] FIGS. 1A to 1F are cross-sectional views of an exemplary
method of forming a semiconductor package structure in accordance
with some embodiments.
[0013] FIG. 2A is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments.
[0014] FIG. 2B is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments.
[0015] FIG. 3A is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments.
[0016] FIG. 3B is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments.
[0017] FIGS. 4A to 4E are cross-sectional views of an exemplary
method of forming a semiconductor package structure in accordance
with some embodiments.
[0018] FIG. 5A is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments.
[0019] FIG. 5B is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments.
[0020] FIGS. 6A to 6E are cross-sectional views of an exemplary
method of forming a semiconductor package structure in accordance
with some embodiments.
[0021] FIG. 7A is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments.
[0022] FIG. 7B is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments.
[0023] FIG. 8A is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments.
[0024] FIG. 8B is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments.
[0025] FIG. 9A is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments.
[0026] FIG. 9B is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments.
[0027] FIGS. 10A to 10E are cross-sectional views of an exemplary
method of forming a semiconductor package structure in accordance
with some embodiments.
[0028] FIG. 10F is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments.
[0029] FIG. 11A is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments.
[0030] FIG. 11B is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments.
[0031] FIG. 12A is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments.
[0032] FIG. 12B is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments.
[0033] FIG. 13A is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments.
[0034] FIG. 13B is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments.
DETAILED DESCRIPTION OF THE INVENTION
[0035] The following description is of the best-contemplated mode
of carrying out the invention. This description is made for the
purpose of illustrating the general principles of the invention and
should not be taken in a limiting sense. The scope of the invention
is determined by reference to the appended claims.
[0036] The present invention will be described with respect to
particular embodiments and with reference to certain drawings, but
the invention is not limited thereto and is only limited by the
claims. The drawings described are only schematic and are
non-limiting. In the drawings, the size of some of the elements may
be exaggerated for illustrative purposes and not drawn to scale.
The dimensions and the relative dimensions do not correspond to
actual dimensions in the practice of the invention.
[0037] FIGS. 1A to 1F are cross-sectional views of an exemplary
method of forming a semiconductor package structure in accordance
with some embodiments of the disclosure. As shown in FIG. 1A, a
substrate 100 is provided. In some embodiments, the substrate 100
may include a plurality of chip regions and a scribe line region
that surrounds the plurality of chip regions and separates the
adjacent chip regions from each other. To simplify the diagram,
only two complete and adjacent chip regions C and a scribe line
region S separating these chip regions C are depicted herein. The
substrate 100 may be a silicon wafer so as to facilitate the
wafer-level packaging process. For example, the substrate 100 may
be a silicon substrate or another semiconductor substrate.
[0038] In some embodiments, the chip regions C of the substrate 100
include integrated circuits (not shown) therein. In some
embodiments, an insulating layer 104 is formed on the substrate
100. The insulating layer 104 may serve as an inter-dielectric
(ILD) layer, an inter-metal dielectric (IMD) layer, a passivation
layer or a combination thereof. To simplify the diagram, only a
flat layer is depicted herein. In some embodiments, the insulating
layer 104 is made of an inorganic material, such as silicon oxide
(SiO.sub.x), silicon nitride (SiN.sub.x), silicon oxynitride
(SiON), or a combination thereof, or another suitable insulating
material.
[0039] Moreover, the insulating layer 104 includes one or more
conductive pads 102 therein. The conductive pads 102 correspond to
the chip regions C of the substrate 100 and are adjacent to the
upper surface of the substrate 100. The conductive pad 102 may be
formed of metal, such as copper, aluminum, or another suitable
metal material. To simplify the diagram, only one conductive pad
102 formed on the substrate 100 in each chip region C and exposed
from the insulating layer 104 is depicted herein as an example. In
some embodiments, the ICs in the chip region C is electrically
connected to the corresponding conductive pad 102. The
aforementioned structure define a number of semiconductor
dies/chips after the chip regions C are separated from each other
by dicing the scribe line region S of the substrate 100.
[0040] In some embodiments, a conductive layer (not shown), such as
a metal layer, is formed on the insulating layer 104 and passing
through the insulating layer 104 to electrically couple to the
exposed pads 102 in the chip regions C. Afterwards, the conductive
layer is patterned to form a redistribution layer (RDL) structure
106 in each of the chip regions C, so that the RDL structure 106 is
electrically coupled to the subsequent formed semiconductor die, as
shown in FIG. 1A.
[0041] As shown in FIG. 1B, in some embodiments, the chip regions C
are separated from each other by dicing the scribe line region S of
the substrate 100 to form semiconductor dies with the RDL
structures 106 thereon. The formed semiconductor die may be a
system on chip (SOC) integrated circuit die. The SOC integrated
circuit die, for example, may include a logic die including a
central processing unit (CPU), a graphics processing unit (GPU), a
dynamic random access memory (DRAM) controller or any combination
thereof. Each of semiconductor dies includes a substrate 100, at
least one conductive pad 102 formed on the substrate 100, and an
insulating layer 104 formed over the substrate 100 and having an
opening to expose the conductive pad 102. Moreover, the
semiconductor die has a first surface 101a (e.g., an active surface
of the semiconductor die), a second surface 101b (e.g., a
non-active surface of the semiconductor die) opposite the first
surface 101a, and a third surface 101c (e.g., a sidewall surface of
the semiconductor die) adjoined between the first surface 101a and
the second surface 101b.
[0042] As shown in FIG. 1B, in some embodiments, a carrier
substrate 200 with an adhesive layer 202 formed thereon is
provided. The carrier substrate 200 may be made of silicon, glass,
ceramic or the like, and may have a shape that is the same or
similar to the semiconductor wafer, and therefore the carrier
substrate 200 is sometimes referred to as a carrier wafer. The
adhesive layer 202 may be made of a light-to-heat conversion (LTHC)
material or another suitable material. Afterwards, in some
embodiments, the second surface 101b of each semiconductor die that
has an RDL structure 106 formed on the first surface 101a of the
semiconductor die is mounted onto the carrier substrate 200 via the
adhesive layer 202 using a pick-and-place process.
[0043] Next, in some embodiments, a protective insulating layer 110
is formed to cover the first surface 101a and the third surface
101c of the semiconductor dies and to surround the RDL structures
106, so that each of the formed semiconductor dies with an RDL
structure 106 thereon is encapsulated by the protective insulating
layer 110. In some embodiments, the protective insulating layer 110
protects the semiconductor dies from the environment, thereby
preventing the semiconductor die in the subsequently formed
semiconductor package structure from damage due to, for example,
the stress, the chemicals and/or the moisture.
[0044] In some embodiments, the protective insulating layer 110 is
made of an epoxy molding compound (EMC), an Ajinomoto.TM. Build-up
Film (ABF), or an acrylic-based material. In some embodiments, the
protective insulating layer 110 is made of an epoxy molding
compound (EMC) and formed by a molding process. For example, the
protective insulating layer 110 (such as in an epoxy or resin) may
be applied while substantially liquid, and then may be cured
through a chemical reaction. The protective insulating layer 110
may be an ultraviolet (UV) or thermally cured polymer applied as a
gel or malleable solid capable of being formed around the
semiconductor dies, and then may be cured through a UV or thermal
curing process. The protective insulating layer 110 may be cured
with a mold (not shown).
[0045] After the protective insulating layer 110 is formed, the
semiconductor dies with RDL structures 106 encapsulated by the
protective insulating layer 110 are de-bonded from the carrier
substrate 200, as shown in FIG. 1C. In some embodiments, a
de-bonding process is performed by exposing the adhesive layer 202
(shown in FIG. 1B) using a laser or UV light when the adhesive
layer 202 is made of an LTHC material. The LTHC material may be
decomposed due to generated heat from the laser or UV light, and
hence the carrier substrate 200 is removed from the structure
including the semiconductor dies, the RDL structures 106, and the
protective insulating layer 110. As a result, the second surface
101b of each semiconductor die is exposed from the protective
insulating layer 110. The resulting structure is shown in FIG.
1C.
[0046] In some embodiments, after the carrier substrate 200 is
removed by the de-bonding process, a grinding process is performed
on the top surface of the protective insulating layer 110 until the
RDL structures 106 are exposed from the protective insulating layer
110, as shown in FIG. 1D. For example, the top surface of the
protective insulating layer 110 may be grinded by a chemical
mechanical polishing (CMP) process or another suitable grinding
process.
[0047] Afterwards, the protective insulating layer 110 and the RDL
structures 106 are covered with a passivation layer 112, as shown
in FIG. 1E. In some embodiments, the passivation layer 112 is
formed on the protective insulating layer 110 and the RDL
structures 106 by a coating process or another suitable deposition
process. Afterwards, the passivation layer 112 is patterned by
lithography or a combination of lithograph and etching to form
openings that expose the RDL structures 106. In some embodiments,
the passivation layer 112 is made of a material that is different
from the material of the protective insulating layer 110. In some
embodiments, the passivation layer 112 is made of polyimide or
polybenzoxazole (PBO).
[0048] In some embodiments, during patterning the passivation layer
112, the passivation layer 112 is also divided into several
portions, so that each of the semiconductor dies is covered by a
respective portion of passivation layer 112. In some other
embodiments, the passivation layer 112 is divided into several
portions by the subsequent dicing process.
[0049] After openings are formed in the passivation layer 112,
conductive structures 120 respectively pass through the passivation
layer 112 via those openings formed in the passivation layer 112,
as shown in FIG. 1E. In some embodiments, the conductive structures
120 fill into the openings formed in the passivation layer 112, so
that each of the conductive structures 120 is electrically coupled
to the respective exposed RDL structure 106 under the opening in
the passivation layer 112.
[0050] In some embodiments, the conductive structure 120 includes
an optional under-bump metallurgy (UBM) layer 122 and a solder bump
124 on the UBM layer 122. In some other embodiments, the conductive
structure 120 includes a conductive bump structure such as a copper
bump, a conductive pillar structure, a conductive wire structure,
or a conductive paste structure.
[0051] After the conductive structures 120 are formed, an optional
protective insulating layer 130 is formed to cover the exposed
second surfaces 101b of the semiconductor dies, as shown in FIG.
1F. The protective insulating layer 130 is sometimes referred to as
a die backside film (DBF) that is made of a thermoset material,
such as an epoxy resin material. In some other embodiments, the
protective insulating layer 130 is made of a material that is the
same as the material of the protective insulating layer 110. For
example, the protective insulating layer 130 is made of an epoxy
molding compound (EMC), an Ajinomoto.TM. Build-up Film (ABF), or an
acrylic-based material.
[0052] In some embodiments, after the protective insulating layer
130 is formed, a singulation is carried out to saw through the
formed structure shown in FIG. 1F. For example, a dicing process
may be performed on the formed structure shown in FIG. 1F. As a
result, multiple separate semiconductor package structures are
formed.
[0053] FIG. 2A is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments. In FIG. 2A, one of the semiconductor package
structures 10a that is formed by dicing the formed structure shown
in FIG. 1F is shown. Descriptions of elements of the embodiments
hereinafter that are the same as or similar to those previously
described with reference to FIGS. 1A to 1F may be omitted for
brevity. In some embodiments, the semiconductor package structure
10a includes a semiconductor die that includes a substrate 100, at
least one conductive pad 102 formed on the substrate 100, and an
insulating layer 104 formed over the substrate 100 and having an
opening to expose the conductive pad 102, as shown in FIG. 2A. The
semiconductor die has a first surface 101a (e.g., an active surface
of the semiconductor die), a second surface 101b (e.g., a
non-active surface of the semiconductor die) opposite the first
surface 101a, and a third surface 101c (e.g., a sidewall surface of
the semiconductor die) adjoined between the first surface 101a and
the second surface 101b.
[0054] In some embodiments, the semiconductor package structure 10a
further includes a protective insulating layer 110 that covers the
first surface 101a and the third surface 101c of the semiconductor
die, and a protective insulating layer 130 that covers the second
surface 101b of the semiconductor die. The thickness of the portion
of the protective insulating layer 110 covering the first surface
101a and the thickness of the of the portion of the protective
insulating layer 110 covering the third surface 101c of the
semiconductor die can be adjusted, so as to fine-tune the
protection ability of the semiconductor package structure 10a.
[0055] In some embodiments, the protective insulating layer 110 and
the protective insulating layer 130 are made of the same material
or different materials. For example, such a material may include an
epoxy molding compound (EMC), an Ajinomoto.TM. Build-up Film (ABF),
or an acrylic-based material. Alternatively, the protective
insulating layer 110 is made of an epoxy molding compound (EMC), an
Ajinomoto.TM. Build-up Film (ABF), or an acrylic-based material,
and the protective insulating layer 130 is made of a DBF material
that includes a thermoset material, such as an epoxy resin
material.
[0056] In some embodiments, the semiconductor package structure 10a
further includes an RDL structure 106 electrically coupled to the
semiconductor die via the conductive pad 102 and surrounded by the
protective insulating layer 110 on the first surface 101a of the
semiconductor die.
[0057] In some embodiments, the semiconductor package structure 10a
further includes a passivation layer 112 covering the RDL structure
106 and a portion of the protective insulating layer 110
surrounding the RDL structure 106. The passivation layer 112 may be
made of polyimide or polybenzoxazole (PBO).
[0058] In some embodiments, the semiconductor package structure 10a
further includes at least one conductive structure 120 that
includes an optional UBM layer 122 and a solder bump 124 and passes
through the passivation layer 112, so as to be electrically coupled
to the semiconductor die through the RDL structure 106.
[0059] In some embodiments, the semiconductor package structure 10a
shown in FIG. 2A is a CSP structure. The CSP structure may include
an SOC package. Moreover, the semiconductor package structure 10a
may be mounted on a base (not shown). The base may include a
printed circuit board (PCB) and may be formed of polypropylene
(PP). Alternatively, the base may include a package substrate. The
semiconductor package structure 10a may be mounted on the base by a
bonding process. For example, the semiconductor package structure
10a may be mounted on the base by the bonding process and
electrically coupled to the base using the conductive structures
120 as connectors.
[0060] FIG. 2B is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments. Descriptions of elements of the embodiments
hereinafter that are the same as or similar to those previously
described with reference to FIG. 2A may be omitted for brevity. In
some embodiments, the semiconductor package structure 10b is
similar to the semiconductor package structure 10a shown in FIG.
2A. Compared to the semiconductor package structure 10a, there is
no protective insulating layer 130 formed in the package structure
10b, and hence the second surface 101b of the semiconductor die is
exposed to the environment. In some embodiments, the semiconductor
package structure 10b is formed by a method that is similar to the
method shown in FIGS. 1A to 1F, except that the formation of the
protective insulating layer 130, as shown in FIG. 1F, is omitted.
Namely, after the structure shown in FIG. 1E is formed, a
singulation is carried out to saw through the formed structure
shown in FIG. 1E.
[0061] FIG. 3A is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments. Descriptions of elements of the embodiments
hereinafter that are the same as or similar to those previously
described with reference to FIG. 2A may be omitted for brevity. In
some embodiments, the semiconductor package structure 10c is
similar to the semiconductor package structure 10a shown in FIG.
2A. Compared to the semiconductor package structure 10a, the
semiconductor package structure 10c further includes a passivation
layer 105 formed between the first surface 101a of the
semiconductor die and the RDL structure 106 and covered by the
protective insulating layer 110. In some embodiments, the material
and the method used for the passivation layer 105 are the same as
or similar to those used for the passivation layer 112. For
example, the passivation layer 105 is made of polyimide or
polybenzoxazole (PBO). In some embodiments, the semiconductor
package structure 10c is formed by a method that is similar to the
method shown in FIGS. 1A to 1F, except that an additional
passivation layer 105 is formed prior to the formation of the RDL
structure 106. Prior to the formation of the RDL structure 106, at
least one opening is formed in the passivation layer 105, so that
the passivation layer 105 exposes the conductive pad 102 and
surrounds the opening formed in the insulating layer 104.
[0062] FIG. 3B is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments. Descriptions of elements of the embodiments
hereinafter that are the same as or similar to those previously
described with reference to FIGS. 2A and 3A may be omitted for
brevity. In some embodiments, the semiconductor package structure
10d is similar to the semiconductor package structure 10c shown in
FIG. 3A. Compared to the semiconductor package structure 10c, there
is no protective insulating layer 130 formed in the package
structure 10d, and hence the second surface 101b of the
semiconductor die is exposed to the environment. In some
embodiments, the semiconductor package structure 10d is formed by a
method that is similar to the method used for forming the
semiconductor package structure 10c, except that the formation of
the protective insulating layer 130 is omitted.
[0063] FIGS. 4A to 4E are cross-sectional views of an exemplary
method of forming a semiconductor package structure in accordance
with some embodiments of the disclosure. Descriptions of elements
of the embodiments hereinafter that are the same as or similar to
those previously described with reference to FIGS. 1A to 1F may be
omitted for brevity. As shown in FIG. 4A, a structure as shown in
FIG. 1A is provided. Afterwards, a protective insulating layer 110a
is formed to cover the first surface 101a of each semiconductor die
and surround each RDL structure 106, so that the top surfaces and
sidewalls of the RDL structures 106 are covered or encapsulated by
the protective insulating layer 110a. In some embodiments, the
protective insulating layer 110a is made of an epoxy molding
compound (EMC), an Ajinomoto.TM. Build-up Film (ABF), or an
acrylic-based material. In some embodiments, the protective
insulating layer 110a is formed by a coating process, a molding
process, or another suitable process.
[0064] As shown in FIG. 4B, in some embodiments, after the
protective insulating layer 110a is formed, the chip regions C are
separated from each other by dicing the scribe line region S of the
substrate 100 to form semiconductor dies with the RDL structures
106 thereon. The formed semiconductor die has a first surface 101a
(e.g., an active surface of the semiconductor die), a second
surface 101b (e.g., a non-active surface of the semiconductor die)
opposite the first surface 101a, and a third surface 101c (e.g., a
sidewall surface of the semiconductor die) adjoined between the
first surface 101a and the second surface 101b. Moreover, the
protective insulating layer 110a has a sidewall 109 that is
substantially aligned with the third surface 101c of the
semiconductor die.
[0065] Still referring to FIG. 4B, in some embodiments, a carrier
substrate 200 with an adhesive layer 202 formed thereon is
provided. Afterwards, in some embodiments, each of the formed
semiconductor dies with an RDL structure 106 formed on the first
surface 101a of the semiconductor die is mounted onto the carrier
substrate 200 by attaching the top surface of the protective
insulating layer 110a to the adhesive layer 202 using a
pick-and-place process. As a result, the second surface 101b of
each semiconductor die is opposite the carrier substrate 200.
[0066] Next, in some embodiments, a protective insulating layer 110
is formed using a molding process to cover the second surface 101b
and the third surface 101c of the semiconductor dies and surround
the protective insulating layer 110a, so that the protective
insulating layer 110 extends from the third surface 101c of each
semiconductor die to the sidewall 109 of the respective protective
insulating layer. As a result, each of the formed semiconductor
dies with an RDL structure 106 thereon is encapsulated by a
protective structure including the protective insulating layer 110a
and the protective insulating layer 110.
[0067] In some embodiments, the protective structure protects the
semiconductor dies from the environment, thereby preventing the
semiconductor die in the subsequently formed semiconductor package
structure from damage due to, for example, the stress, the
chemicals and/or the moisture. In some embodiments, the protective
insulating layer 110 of the protective structure is formed by a
molding process while the protective insulating layer 110a of the
protective structure is formed by a coating process.
[0068] After the protective structure is formed, the semiconductor
dies with RDL structures 106 encapsulated by the protective
structure are de-bonded from the carrier substrate 200 by a
de-bonding process as shown in FIG. 1C. The resulting structure is
shown in FIG. 4C.
[0069] In some embodiments, after the carrier substrate 200 is
removed by the de-bonding process, a grinding process is performed
on the protective insulating layer 110a above the RDL structures
106 and a portion of the protective insulating layer 110
surrounding the protective insulating layer 110a until the RDL
structures 106 are exposed from the protective insulating layer
110a, as shown in FIG. 4D. For example, the protective insulating
layer 110a and the protective insulating layer 110 may be grinded
by a CMP process or another suitable grinding process.
[0070] Afterwards, the protective insulating layer 110a and the RDL
structures 106 are covered with a patterned passivation layer 112,
as shown in FIG. 4E. In some embodiments, the passivation layer 112
is made of a material that is different from the material of the
protective insulating layer 110a and the material of the protective
insulating layer 110. In some embodiments, during patterning the
passivation layer 112, the passivation layer 112 is also divided
into several portions, so that each of the semiconductor dies is
covered by a respective portion of passivation layer 112. In some
other embodiments, the passivation layer 112 is divided into
several portions by the subsequent dicing process.
[0071] After openings are formed in the passivation layer 112,
conductive structures 120 including an optional UBM layer 122 and a
solder bump 124 respectively pass through the passivation layer 112
via those openings, as shown in FIG. 4E. As a result, each of the
conductive structures 120 is electrically coupled to the respective
exposed RDL structure 106.
[0072] In some embodiments, after the conductive structures 120 is
formed, a singulation (e.g., a dicing process) is carried out to
saw through the formed structure shown in FIG. 4E. As a result,
multiple separate semiconductor package structures are formed.
[0073] FIG. 5A is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments. In FIG. 5A, one of the semiconductor package
structures 20a that is formed by dicing the formed structure shown
in FIG. 4E is shown. Descriptions of elements of the embodiments
hereinafter that are the same as or similar to those previously
described with reference to FIGS. 4A to 4E may be omitted for
brevity. In some embodiments, the semiconductor package structure
20a includes a semiconductor die that includes a substrate 100, at
least one conductive pad 102 formed on the substrate 100, and an
insulating layer 104 formed over the substrate 100 and having an
opening to expose the conductive pad 102, as shown in FIG. 5A. The
semiconductor die has a first surface 101a (e.g., an active surface
of the semiconductor die), a second surface 101b (e.g., a
non-active surface of the semiconductor die) opposite the first
surface 101a, and a third surface 101c (e.g., a sidewall surface of
the semiconductor die) adjoined between the first surface 101a and
the second surface 101b.
[0074] In some embodiments, the semiconductor package structure 20a
further includes a protective insulating layer 110a that covers the
first surface 101a of the semiconductor die, and a protective
insulating layer 110 that covers the second surface 101b and the
third surface 101c of the semiconductor die and that surrounds the
protective insulating layer 110a. The protective insulating layer
110a has a sidewall 109 that is substantially aligned with the
third surface 101c of the semiconductor die. The protective
insulating layer 110 extends from the third surface 101c of the
semiconductor die to the sidewall 109 of the protective insulating
layer 110a. The thickness of the protective insulating layer 110a
covering the first surface 101a and the thickness of the protective
insulating layer 110 covering the second surface 101b and the third
surface 101c of the semiconductor die can be adjusted, so as to
fine-tune the protection ability of the semiconductor package
structure 20a.
[0075] In some embodiments, the protective insulating layer 110a
and the protective insulating layer 110 are made of the same
material or different materials. For example, such a material may
include an epoxy molding compound (EMC), an Ajinomoto.TM. Build-up
Film (ABF), or an acrylic-based material.
[0076] In some embodiments, the semiconductor package structure 20a
further includes an RDL structure 106 electrically coupled to the
semiconductor die via the conductive pad 102 and surrounded by the
protective insulating layer 110a.
[0077] In some embodiments, the semiconductor package structure 20a
further includes a passivation layer 112 covering the RDL structure
106 and a portion of the protective insulating layer 110a
surrounding the RDL structure 106. Moreover, the passivation layer
112 is made of for example, polyimide or polybenzoxazole (PBO).
[0078] In some embodiments, the semiconductor package structure 20a
further includes at least one conductive structure 120 that
includes an optional UBM layer 122 and a solder bump 124 and passes
through the passivation layer 112, so as to be electrically coupled
to the semiconductor die through the RDL structure 106.
[0079] In some embodiments, the semiconductor package structure 20a
shown in FIG. 5A is a CSP structure. The CSP structure may include
an SOC package. Moreover, the semiconductor package structure 20a
may be mounted on a base (not shown). The base may include a
printed circuit board (PCB) and may be formed of polypropylene
(PP). Alternatively, the base may include a package substrate.
Similar to the semiconductor package structure 10a, the
semiconductor package structure 20a may be mounted on the base by a
bonding process and electrically coupled to the base using the
conductive structures 120 as connectors.
[0080] FIG. 5B is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments. Descriptions of elements of the embodiments
hereinafter that are the same as or similar to those previously
described with reference to FIG. 5A may be omitted for brevity. In
some embodiments, the semiconductor package structure 20b is
similar to the semiconductor package structure 20a shown in FIG.
5A. Compared to the semiconductor package structure 20a, the
semiconductor package structure 20b further includes a passivation
layer 105 formed between the first surface 101a of the
semiconductor die and the RDL structure 106 and covered by the
protective insulating layer 110a. In some embodiments, the material
and the method used for the passivation layer 105 are the same as
or similar to those used for the passivation layer 112 and
different from those used for the protective insulating layer 110a
and those used for the protective insulating layer 110. In some
embodiments, the semiconductor package structure 20b is formed by a
method that is similar to the method shown in FIGS. 4A to 4E,
except that an additional passivation layer 105 is formed prior to
the formation of the RDL structure 106. Prior to the formation of
the RDL structure 106, at least one opening is formed in the
passivation layer 105, so that the passivation layer 105 exposes
the conductive pad 102 and surrounds the opening formed in the
insulating layer 104.
[0081] FIGS. 6A to 6E are cross-sectional views of an exemplary
method of forming a semiconductor package structure in accordance
with some embodiments of the disclosure. Descriptions of elements
of the embodiments hereinafter that are the same as or similar to
those previously described with reference to FIGS. 1A to 1F or 4A
to 4E may be omitted for brevity. As shown in FIG. 6A, a structure
as shown in FIG. 1A is provided. Afterwards, the chip regions C are
separated from each other by dicing the scribe line region S of the
substrate 100 to form semiconductor dies with the RDL structures
106 thereon. The formed semiconductor die has a first surface 101a
(e.g., an active surface of the semiconductor die), a second
surface 101b (e.g., a non-active surface of the semiconductor die)
opposite the first surface 101a, and a third surface 101c (e.g., a
sidewall surface of the semiconductor die) adjoined between the
first surface 101a and the second surface 101b.
[0082] As shown in FIG. 6A, in some embodiments, a carrier
substrate 200 with an adhesive layer 202 formed thereon is
provided. Afterwards, in some embodiments, each of the formed
semiconductor dies with an RDL structure 106 formed on the first
surface 101a of the semiconductor die is mounted onto the carrier
substrate 200 by attaching the top surface and sidewall surface of
the RDL structure 106 to the adhesive layer 202 using a
pick-and-place process. As a result, the second surface 101b of
each semiconductor die is opposite the carrier substrate 200.
[0083] Next, in some embodiments, a protective insulating layer 110
is formed using a molding process to cover the second surface 101b
and the third surface 101c of the semiconductor dies and surround
the protective insulating layer 110a, so that the protective
insulating layer 110 extends from the third surface 101c of each
semiconductor die to the sidewall 109 of the respective protective
insulating layer.
[0084] In some embodiments, after the protective insulating layer
110 is formed, the semiconductor dies with RDL structures 106 are
de-bonded from the carrier substrate 200 by a de-bonding process
(as shown in FIG. 1C). The resulting structure is shown in FIG.
6B.
[0085] In some embodiments, after the de-bonding process, a
protective insulating layer 110a is formed by a coating process to
cover the first surface 101a of each semiconductor die and surround
each RDL structure 106, as shown in FIG. 6C. As a result, the top
surfaces and sidewalls of the RDL structures 106 are covered or
encapsulated by the protective insulating layer 110a. Moreover, a
portion of the protective insulating layer 110 covering the third
surface 101c of the semiconductor die is capped by the protective
insulating layer 110a. In some other embodiments, the protective
insulating layer 110a is formed by a molding process or another
suitable process.
[0086] Due to the formation of a protective structure including the
protective insulating layer 110a and the protective insulating
layer 110, each of the formed semiconductor dies with an RDL
structure 106 thereon is encapsulated. The protective structure
protects the semiconductor dies from the environment, thereby
preventing the semiconductor die in the subsequently formed
semiconductor package structure from damage due to, for example,
the stress, the chemicals and/or the moisture.
[0087] In some embodiments, after the protective structure is
formed, a grinding process is performed on the protective
insulating layer 110a above the RDL structures 106 until the RDL
structures 106 are exposed from the protective insulating layer
110a, as shown in FIG. 6D. For example, the protective insulating
layer 110a may be grinded by a CMP process or another suitable
grinding process.
[0088] Afterwards, the protective insulating layer 110a and the RDL
structures 106 are covered with a patterned passivation layer 112,
as shown in FIG. 6E. In some embodiments, the passivation layer 112
is made of a material that is different from the material of the
protective insulating layer 110a and the material of the protective
insulating layer 110. In some embodiments, during patterning the
passivation layer 112, the passivation layer 112 is also divided
into several portions, so that each of the semiconductor dies is
covered by a respective portion of passivation layer 112. In some
other embodiments, the passivation layer 112 is divided into
several portions by the subsequent dicing process.
[0089] After openings are formed in the passivation layer 112,
conductive structures 120 including an optional UBM layer 122 and a
solder bump 124 respectively pass through the passivation layer 112
via those openings, as shown in FIG. 6E. As a result, each of the
conductive structures 120 is electrically coupled to the respective
exposed RDL structure 106.
[0090] In some embodiments, after the conductive structures 120 is
formed, a singulation (e.g., a dicing process) is carried out to
saw through the formed structure shown in FIG. 6E. As a result,
multiple separate semiconductor package structures are formed. In
some embodiments, in the semiconductor package structure, the
protective insulating layer 110a has a sidewall and a portion of
the protective insulating layer covering the third surface 101c of
the semiconductor die has a sidewall, and those sidewalls are
substantially aligned with each other.
[0091] FIG. 7A is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments. In FIG. 7A, one of the semiconductor package
structures 30a that is formed by dicing the formed structure shown
in FIG. 6E is shown. Descriptions of elements of the embodiments
hereinafter that are the same as or similar to those previously
described with reference to FIGS. 1A to 1F or 4A to 4E may be
omitted for brevity. In some embodiments, the semiconductor package
structure 30a includes a semiconductor die that includes a
substrate 100, at least one conductive pad 102 formed on the
substrate 100, and an insulating layer 104 formed over the
substrate 100 and having an opening to expose the conductive pad
102, as shown in FIG. 7A. The semiconductor die has a first surface
101a (e.g., an active surface of the semiconductor die), a second
surface 101b (e.g., a non-active surface of the semiconductor die)
opposite the first surface 101a, and a third surface 101c (e.g., a
sidewall surface of the semiconductor die) adjoined between the
first surface 101a and the second surface 101b.
[0092] In some embodiments, the semiconductor package structure 30a
further includes a protective insulating layer 110a that covers the
first surface 101a of the semiconductor die, and a protective
insulating layer 110 that covers the second surface 101b and the
third surface 101c of the semiconductor die and that surrounds the
protective insulating layer 110a. The protective insulating layer
110a has a sidewall 109 and a portion of the protective insulating
layer 110a covering the third surface 101c of the semiconductor die
has a sidewall 113. In some embodiments, the sidewall 109 is
substantially aligned with the sidewall 113. Moreover, the portion
of the protective insulating layer 110 covering the third surface
101c of the semiconductor die is capped by the protective
insulating layer 110a. The thickness of the protective insulating
layer 110a covering the first surface 101a and the thickness of the
protective insulating layer 110 covering the second surface 101b
and the third surface 101c of the semiconductor die can be
adjusted, so as to fine-tune the protection ability of the
semiconductor package structure 30a.
[0093] In some embodiments, the protective insulating layer 110a
and the protective insulating layer 110 are made of the same
material or different materials. For example, such a material may
include an epoxy molding compound (EMC), an Ajinomoto.TM. Build-up
Film (ABF), or an acrylic-based material.
[0094] In some embodiments, the semiconductor package structure 30a
further includes an RDL structure 106 electrically coupled to the
semiconductor die via the conductive pad 102 and surrounded by the
protective insulating layer 110a.
[0095] In some embodiments, the semiconductor package structure 30a
further includes a passivation layer 112 covering the RDL structure
106 and a portion of the protective insulating layer 110a
surrounding the RDL structure 106. Moreover, the passivation layer
112 is made of for example, polyimide or polybenzoxazole (PBO).
[0096] In some embodiments, the semiconductor package structure 30a
further includes at least one conductive structure 120 that
includes an optional UBM layer 122 and a solder bump 124 and passes
through the passivation layer 112, so as to be electrically coupled
to the semiconductor die through the RDL structure 106.
[0097] In some embodiments, the semiconductor package structure 30a
shown in FIG. 7A is a CSP structure. The CSP structure may include
an SOC package. Moreover, the semiconductor package structure 30a
may be mounted on a base (not shown). The base may include a
printed circuit board (PCB) and may be formed of polypropylene
(PP). Alternatively, the base may include a package substrate.
Similar to the semiconductor package structure 10a or 20a, the
semiconductor package structure 30a may be mounted on the base by a
bonding process and electrically coupled to the base using the
conductive structures 120 as connectors.
[0098] FIG. 7B is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments. Descriptions of elements of the embodiments
hereinafter that are the same as or similar to those previously
described with reference to FIG. 7A may be omitted for brevity. In
some embodiments, the semiconductor package structure 30b is
similar to the semiconductor package structure 30a shown in FIG.
7A. Compared to the semiconductor package structure 30a, the
semiconductor package structure 30b further includes a passivation
layer 105 formed between the first surface 101a of the
semiconductor die and the RDL structure 106 and covered by the
protective insulating layer 110a. In some embodiments, the material
and the method used for the passivation layer 105 are the same as
or similar to those used for the passivation layer 112 and
different from those used for the protective insulating layer 110a
and those used for the protective insulating layer 110. In some
embodiments, the semiconductor package structure 30b is formed by a
method that is similar to the method shown in FIGS. 6A to 6E,
except that an additional passivation layer 105 is formed prior to
the formation of the RDL structure 106. Prior to the formation of
the RDL structure 106, at least one opening is formed in the
passivation layer 105, so that the passivation layer 105 exposes
the conductive pad 102 and surrounds the opening formed in the
insulating layer 104.
[0099] FIG. 8A is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments. Descriptions of elements of the embodiments
hereinafter that are the same as or similar to those previously
described with reference to FIG. 7A may be omitted for brevity. In
some embodiments, the semiconductor package structure 40a is
similar to the semiconductor package structure 30a shown in FIG.
7A. Compared to the semiconductor package structure 30a, the
passivation layer 112 is formed on the RDL structure 106 and the
protective insulating layer 110 without forming the protective
insulating layer 110a in the semiconductor package structure 40a.
In some embodiments, the semiconductor package structure 40a is
formed by a method that is similar to the method illustrated in
FIG. 7A, except that the protective insulating layer 110a is not
formed. The passivation layer 112 may be formed after the formation
of the RDL structure 106. As shown in FIG. 8A, the passivation
layer 112 covers the sidewall of the RDL structure 106.
[0100] FIG. 8B is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments. Descriptions of elements of the embodiments
hereinafter that are the same as or similar to those previously
described with reference to FIG. 8A may be omitted for brevity. In
some embodiments, the semiconductor package structure 40b is
similar to the semiconductor package structure 40a shown in FIG.
8A. Compared to the semiconductor package structure 40a, the
semiconductor package structure 40b further includes a passivation
layer 105 formed between the first surface 101a of the
semiconductor die and the RDL structure 106 and covered by the
passivation layer 112. In some embodiments, the material and the
method used for the passivation layer 105 are the same as or
similar to those used for the passivation layer 112 and different
from those used for the protective insulating layer 110. As shown
in FIG. 8B, the passivation layer 112 covers the sidewall of the
RDL structure 106 and the sidewall of the passivation layer
105.
[0101] In some embodiments, the semiconductor package structure 40b
is formed by a method that is similar to the method illustrated in
FIG. 8A, except that an additional passivation layer 105 is formed
prior to the formation of the RDL structure 106. Prior to the
formation of the RDL structure 106, at least one opening is formed
in the passivation layer 105, so that the passivation layer 105
exposes the conductive pad 102 and surrounds the opening formed in
the insulating layer 104.
[0102] FIG. 9A is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments. Descriptions of elements of the embodiments
hereinafter that are the same as or similar to those previously
described with reference to FIG. 8A may be omitted for brevity. In
some embodiments, the semiconductor package structure 50a is
similar to the semiconductor package structure 40a shown in FIG.
8A. Compared to the semiconductor package structure 40a, the
protective insulating layer 110 further covers the RDL structure
106 and the passivation layer 112 in the semiconductor package
structure 50a.
[0103] In some embodiments, the semiconductor package structure 50a
is formed by a method that is similar to the method illustrated in
FIG. 8A, except that the protective insulating layer 110 is formed
before the formation of the conductive structure 120 and after the
formation of the passivation layer 112. In some embodiments, after
the formation of the passivation layer 112, the protective
insulating layer 110 is formed to cover the second surface 101b and
the third surface 101c of the semiconductor die, the RDL structure
106, and the passivation layer 112. In other words, the embodiments
according to FIGS. 1A-8B may be referred to as recon first, and the
embodiments according to FIG. 9A may be referred to as recon
last.
[0104] Next, at least one opening may be formed in the protective
insulating layer 110 and passing through the passivation layer 112,
so that the passivation layer 112 and the protective insulating
layer 110 expose the RDL structure 106. Next, the conductive
structure 120 is formed in the openings. In some embodiments, the
conductive structure 120 includes an optional UBM layer 122 and a
solder bump 124 on the UBM layer 122. In some other embodiments,
the UBM layer 122 is not formed, and the conductive structure 120
includes a solder bump 124 on the passivation layer 112.
[0105] Various steps may be added, removed, rearranged and
repeated. For example, in the embodiment where the conductive
structure 120 including the UBM layer 122 and the solder bump 124,
the protective insulating layer 110 may be formed after the
formation of the UBM layer 122 and before the formation of the
solder bump 124. In these embodiments, after the protective
insulating layer 110 is formed, a grinding process is performed on
the top surface of the protective insulating layer 110 until the
UBM layer 122 is exposed from the protective insulating layer 110.
For example, the top surface of the protective insulating layer 110
may be grinded by a chemical mechanical polishing (CMP) process or
another suitable grinding process. Next, the solder bump 124 is
formed on the exposed UBM layer 122.
[0106] In some embodiments, the edge of the passivation layer 112
is aligned with the third surface 101c of the semiconductor die as
shown in FIG. 9A, but the present disclosure is not limit thereto.
For example, the edge of the passivation layer 112 may be disposed
inside the first surface 101a of the semiconductor die in some
other embodiments. In these embodiments, a portion of the first
surface 101a of the semiconductor die exposed by the passivation
layer 112 is in contact with the protective insulating layer
110.
[0107] In some embodiments, the RDL structure 106 is in contact
with the passivation layer 112 as shown in FIG. 9A, but the present
disclosure is not limit thereto. For example, the passivation layer
112 may not be formed, and the RDL structure 106 may be in contact
with the protective insulating layer 110 in some other embodiments.
In these embodiments, the protective insulating layer 110 is formed
after the formation of the RDL structure 106. Alternatively, a
portion of the top surface of the RDL structure 106 may be in
contact with the passivation layer 112, and another portion of the
top surface of the RDL structure 106 may be in contact with the
protective insulating layer 110.
[0108] According to some embodiments, in addition to the second
surface 101b and the third surface 101c of the semiconductor die,
the protective insulating layer 110 further covers the RDL
structure 106 and the passivation layer 112 can provide an better
protection ability of the semiconductor package structure 50a.
Furthermore, the semiconductor die shift for the RDL structure
alignment can be reduced or avoided. Therefore, reliability of the
semiconductor package structure 50b can be improved.
[0109] FIG. 9B is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments. Descriptions of elements of the embodiments
hereinafter that are the same as or similar to those previously
described with reference to FIG. 9A may be omitted for brevity. In
some embodiments, the semiconductor package structure 50b is
similar to the semiconductor package structure 50a shown in FIG.
9A. Compared to the semiconductor package structure 50a, the
semiconductor package structure 50b further includes a passivation
layer 105 formed between the first surface 101a of the
semiconductor die and the RDL structure 106 and covered by the
protective insulating layer 110. In some embodiments, the material
and the method used for the passivation layer 105 are the same as
or similar to those used for the passivation layer 112 and
different from those used for the protective insulating layer
110.
[0110] In some embodiments, the semiconductor package structure 50b
is formed by a method that is similar to the method described in
FIG. 9A, except that an additional passivation layer 105 is formed
prior to the formation of the RDL structure 106. Prior to the
formation of the RDL structure 106, at least one opening is formed
in the passivation layer 105, so that the passivation layer 105
exposes the conductive pad 102 and surrounds the opening formed in
the insulating layer 104.
[0111] FIGS. 10A to 10E are cross-sectional views of an exemplary
method of forming a semiconductor package structure in accordance
with some embodiments of the disclosure. Descriptions of elements
of the embodiments hereinafter that are the same as or similar to
those previously described with reference to FIGS. 1A to 1F, 4A to
4E or 6A to 6E may be omitted for brevity. Compared to the
semiconductor package structure 10a-50b as shown in FIGS. 1A-9B,
the following embodiment provides a semiconductor package structure
with a fan-out structure.
[0112] As shown in FIG. 10A, in some embodiments, a substrate 100
is provided. The substrate 100 may be a silicon wafer. For example,
the substrate 100 may be a silicon substrate or another
semiconductor substrate. In some embodiments, the substrate 100
include integrated circuits (not shown) therein.
[0113] In some embodiments, an insulating layer 104 is formed on
the substrate 100. The insulating layer 104 may serve as an ILD
layer, an IMD layer, a passivation layer or a combination thereof.
To simplify the diagram, only a flat layer is depicted herein. In
some embodiments, the insulating layer 104 is made of an inorganic
material, such as silicon oxide (SiO.sub.x), silicon nitride
(SiN.sub.x), silicon oxynitride (SiON), a combination thereof, or
another suitable insulating material.
[0114] Moreover, the insulating layer 104 includes one or more
conductive pads 102 therein. The conductive pads 102 are adjacent
to the upper surface of the substrate 100. The conductive pad 102
may be formed of metal, such as copper, aluminum, or another
suitable metal material. Two conductive pads 102 formed on the
substrate 100 and exposed from the insulating layer 104 are
depicted herein as an example, but the present disclosure is not
limit thereto. For example, one or more than two conductive pads
102 may be formed on the substrate 100.
[0115] In some embodiments, a conductive layer (not shown), such as
a metal layer, is formed on the insulating layer 104 and passing
through the insulating layer 104 to electrically couple to the
exposed conductive pads 102. Afterwards, the conductive layer is
patterned to form a RDL structure 106, so that the RDL structure
106 is electrically coupled to the subsequent formed semiconductor
die, as shown in FIG. 10A.
[0116] In some embodiments, the substrate 100 is diced to form
semiconductor dies with the RDL structure 106 thereon, as shown in
FIG. 10A. Each of the formed semiconductor dies may be a SOC
integrated circuit die. The SOC integrated circuit die, for
example, may include a logic die including a CPU, a GPU, a DRAM
controller, or any combination thereof. Each of the semiconductor
dies includes a substrate 100, one or more conductive pads 102
formed on the substrate 100, and an insulating layer 104 formed
over the substrate 100 and having an opening to expose the
conductive pads 102. Moreover, the semiconductor die has a first
surface 101a (e.g., an active surface of the semiconductor die), a
second surface 101b (e.g., a non-active surface of the
semiconductor die) opposite the first surface 101a, and a third
surface 101c (e.g., a sidewall surface of the semiconductor die)
adjoined between the first surface 101a and the second surface
101b.
[0117] In some embodiments, the second surface 101b of each
semiconductor die may be mounted onto a carrier substrate (not
shown) via an adhesive layer (not shown) using a pick-and-place
process. Next, in some embodiments, a protective insulating layer
110 is formed to cover the first surface 101a and the third surface
101c of the semiconductor dies and to surround the RDL structure
106, so that each of the formed semiconductor dies with an RDL
structure 106 thereon is encapsulated by the protective insulating
layer 110. In some embodiments, the protective insulating layer 110
protects the semiconductor dies from the environment, thereby
preventing the semiconductor die in the subsequently formed
semiconductor package structure from damage due to, for example,
the stress, the chemicals and/or the moisture.
[0118] In some embodiments, the protective insulating layer 110 is
made of an epoxy molding compound (EMC), an Ajinomoto.TM. Build-up
Film (ABF), or an acrylic-based material. In some embodiments, the
protective insulating layer 110 is made of an epoxy molding
compound (EMC) and formed by a molding process. The exemplary
formation of the protective insulating layer 110 is described
above, and will not be repeated again.
[0119] After the protective insulating layer 110 is formed, the
semiconductor die with the RDL structure 106 encapsulated by the
protective insulating layer 110 is de-bonded from the carrier
substrate. The exemplary method of de-bonding is described above,
and will not be repeated again. As a result, the second surface
101b of each semiconductor die is exposed from the protective
insulating layer 110.
[0120] In some embodiments, after the carrier substrate is removed
by the de-bonding process, a grinding process is performed on the
top surface of the protective insulating layer 110 until the RDL
structure 106 is exposed from the protective insulating layer 110,
as shown in FIG. 10C. For example, the top surface of the
protective insulating layer 110 may be grinded by a CMP process or
another suitable grinding process.
[0121] Afterwards, the protective insulating layer 110 and the RDL
structure 106 are covered with a passivation layer 112, as shown in
FIG. 10D. In some embodiments, the passivation layer 112 is formed
on the protective insulating layer 110 and the RDL structure 106 by
a coating process or another suitable deposition process.
Afterwards, the passivation layer 112 is patterned by lithography
or a combination of lithograph and etching to form openings that
expose the RDL structure 106. In some embodiments, the passivation
layer 112 is made of a material that is different from the material
of the protective insulating layer 110. In some embodiments, the
passivation layer 112 is made of polyimide or polybenzoxazole
(PBO).
[0122] After openings are formed in the passivation layer 112, a
RDL structure 114 passes through the passivation layer 112 via
those openings formed in the passivation layer 112, as shown in
FIG. 10D. The formation and the material of the RDL structure 114
may include the formation and the material as described above with
respect to the RDL structure 106, and will not be repeated again.
In some embodiments, the RDL structure 114 fills into the openings
formed in the passivation layer 112, so that each of the RDL
structure 114 is electrically coupled to the respective exposed RDL
structure 106 under the opening in the passivation layer 112.
[0123] As shown in FIG. 10D, the RDL structure 114 extends from the
RDL structure 106 to above the protective insulating layer 110,
according to some embodiments. In particular, the RDL structure 114
may extend from directly above the first surface 101a of the
semiconductor die to directly above the protective insulating layer
110. Accordingly, the RDL structure 114 enables the fan-out
connection.
[0124] Afterwards, the protective insulating layer 110, the
passivation layer 112, and the RDL structure 114 are covered with a
patterned passivation layer 116, as shown in FIG. 10D. In some
embodiments, the passivation layer 116 is made of a material that
is different from the material of the protective insulating layer
110. The formation and the material of the passivation layer 116
may include the formation and the material as described above with
respect to the passivation layer 112 or the passivation layer 105,
and will not be repeated again. Afterwards, the passivation layer
116 is patterned by lithography or a combination of lithograph and
etching to form openings that expose the RDL structure 114.
[0125] After openings are formed in the passivation layer 116, an
UBM layer 122 passes through the passivation layer 116 via those
openings formed in the passivation layer 116, as shown in FIG. 10D.
In some embodiments, the UBM layer 122 fills into the openings
formed in the passivation layer 116, so that each of the conductive
structures 120 is electrically coupled to the respective exposed
RDL structure 114 under the opening in the passivation layer
116.
[0126] As shown in FIG. 10E, a solder bump 124 is formed on the UBM
layer 122, according to some embodiments. In some embodiments, a
conductive structure 120 includes the UBM layer 122 and the solder
bump 124. In some other embodiments, the conductive structure 120
includes a conductive bump structure such as a copper bump, a
conductive pillar structure, a conductive wire structure, or a
conductive paste structure. In some embodiments, more than one
conductive structures 120 are formed. As shown in FIG. 10E, the gap
G1 between the conductive structures 120 may be greater than the
gap G2 between the RDL structures 106 to achieve the fan-out
structure.
[0127] After the conductive structures 120 are formed, an optional
protective insulating layer 130 is formed to cover the exposed
second surface 101b of the semiconductor dies, as shown in FIG.
10E. The protective insulating layer 130 is sometimes referred to
as a DBF that is made of a thermoset material, such as an epoxy
resin material. In some other embodiments, the protective
insulating layer 130 is made of a material that is the same as the
material of the protective insulating layer 110. For example, the
protective insulating layer 130 is made of an epoxy molding
compound (EMC), an Ajinomoto.TM. Build-up Film (ABF), or an
acrylic-based material.
[0128] FIG. 10F is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments. Descriptions of elements of the embodiments
hereinafter that are the same as or similar to those previously
described with reference to FIG. 10E may be omitted for brevity. In
some embodiments, the semiconductor package structure 60b is
similar to the semiconductor package structure 60a shown in FIG.
10E. Compared to the semiconductor package structure 60a, there is
no protective insulating layer 130 formed in the package structure
60b, and hence the second surface 101b of the semiconductor die is
exposed to the environment. In some embodiments, the semiconductor
package structure 60b is formed by a method that is similar to the
method shown in FIGS. 10A to 10E, except that the formation of the
protective insulating layer 130, as shown in FIG. 10E, is
omitted.
[0129] FIG. 11A is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments. Descriptions of elements of the embodiments
hereinafter that are the same as or similar to those previously
described with reference to FIG. 10E may be omitted for brevity. In
some embodiments, the semiconductor package structure 70a is
similar to the semiconductor package structure 60a shown in FIG.
10E. Compared to the semiconductor package structure 60a, there is
no UBM layer 122 formed in the package structure 70a, and hence the
solder bump 124 is formed directly on the passivation layer 116. In
some embodiments, the semiconductor package structure 70a is formed
by a method that is similar to the method shown in FIGS. 10A to
10E, except that the formation of the UBM layer 122, as shown in
FIG. 10E, is omitted.
[0130] As shown in FIG. 11A, the solder bump 124 may pass through
the passivation layer 116 via openings formed in the passivation
layer 116. In some embodiments, the solder bump 124 fills into the
openings formed in the passivation layer 116, so that each of the
conductive structures 120 is electrically coupled to the respective
exposed RDL structure 114 under the opening in the passivation
layer 116.
[0131] FIG. 11B is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments. Descriptions of elements of the embodiments
hereinafter that are the same as or similar to those previously
described with reference to FIG. 11A may be omitted for brevity. In
some embodiments, the semiconductor package structure 70b is
similar to the semiconductor package structure 70a shown in FIG.
11A. Compared to the semiconductor package structure 70a, there is
no protective insulating layer 130 formed in the package structure
70b, and hence the second surface 101b of the semiconductor die is
exposed to the environment.
[0132] FIG. 12A is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments. Descriptions of elements of the embodiments
hereinafter that are the same as or similar to those previously
described with reference to FIG. 10E may be omitted for brevity. In
some embodiments, the semiconductor package structure 80a is
similar to the semiconductor package structure 60a shown in FIG.
10E. Compared to the semiconductor package structure 60a, there is
no passivation layer 105 formed in the package structure 80b, and
hence the RDL structure 106 is formed directly on the insulating
layer 104. In some embodiments, the semiconductor package structure
80a is formed by a method that is similar to the method shown in
FIGS. 10A to 10E, except that the formation of the passivation
layer 105, as shown in FIG. 10A, is omitted.
[0133] FIG. 12B is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments. Descriptions of elements of the embodiments
hereinafter that are the same as or similar to those previously
described with reference to FIG. 12A may be omitted for brevity. In
some embodiments, the semiconductor package structure 80b is
similar to the semiconductor package structure 80a shown in FIG.
12A. Compared to the semiconductor package structure 80a, there is
no protective insulating layer 130 formed in the package structure
80b, and hence the second surface 101b of the semiconductor die is
exposed to the environment.
[0134] FIG. 13A is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments. Descriptions of elements of the embodiments
hereinafter that are the same as or similar to those previously
described with reference to FIG. 10E may be omitted for brevity. In
some embodiments, the semiconductor package structure 90a is
similar to the semiconductor package structure 60a shown in FIG.
10E. Compared to the semiconductor package structure 60a, there is
no passivation layer 105 and no UBM layer 122 formed in the package
structure 90a, and hence the RDL structure 106 is formed directly
on the insulating layer 104 and the solder bump 124 is formed
directly on the passivation layer 116. In some embodiments, the
semiconductor package structure 80a is formed by a method that is
similar to the method shown in FIGS. 10A to 10E, except that the
formation of the passivation layer 105 and the UBM layer 122, is
omitted.
[0135] FIG. 13B is a cross-sectional view of an exemplary
semiconductor package structure in accordance with some
embodiments. Descriptions of elements of the embodiments
hereinafter that are the same as or similar to those previously
described with reference to FIG. 13A may be omitted for brevity. In
some embodiments, the semiconductor package structure 90b is
similar to the semiconductor package structure 90a shown in FIG.
13A. Compared to the semiconductor package structure 90a, there is
no protective insulating layer 130 formed in the package structure
90b, and hence the second surface 101b of the semiconductor die is
exposed to the environment.
[0136] According to the foregoing embodiments, the semiconductor
package structure is designed to fabricate a protective structure
in the semiconductor package structure to cover or encapsulate the
semiconductor die in the semiconductor package structure. The
protective structure includes one or more protective insulating
layers to protect the semiconductor die from the environment,
thereby preventing the semiconductor die in the semiconductor
package structure from damage due to, for example, the stress, the
chemicals and/or the moisture.
[0137] Due to the topside protection of semiconductor die, the
reliability of the semiconductor package structure can be
maintained during the subsequent thermal process (such as a surface
mount technology (SMT) process or a bonding process). Moreover, the
RDL structure formed on the semiconductor die is also protected by
the protective structure, so as to keep its electrical and thermal
performance. In addition, due to the sidewall protection of
semiconductor die, the semiconductor die in the semiconductor
package structure can be prevented from chipping when the CSP
structure is placed in a test socket for performing a test
process.
[0138] Furthermore, the protective insulating layer covers the RDL
structure and the passivation layer, the second surface and the
third surface of the semiconductor die can provide a better
protection ability of the semiconductor package structure,
according to some embodiments. In addition, the semiconductor die
shift for the RDL structure alignment can be reduced or avoided.
Therefore, reliability of the semiconductor package structure can
be improved.
[0139] While the invention has been described by way of example and
in terms of the preferred embodiments, it should be understood that
the invention is not limited to the disclosed embodiments. On the
contrary, it is intended to cover various modifications and similar
arrangements (as would be apparent to those skilled in the art).
Therefore, the scope of the appended claims should be accorded the
broadest interpretation so as to encompass all such modifications
and similar arrangements.
* * * * *