U.S. patent application number 16/003654 was filed with the patent office on 2019-05-30 for seal ring for hybrid-bond.
The applicant listed for this patent is Taiwan Semiconductor Manufacturing Company, Ltd.. Invention is credited to Hsien-Wei Chen, Ming-Fa Chen, Chih-Chia Hu, Sen-Bor Jan, Chun-Chiang Kuo.
Application Number | 20190164914 16/003654 |
Document ID | / |
Family ID | 66633562 |
Filed Date | 2019-05-30 |
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United States Patent
Application |
20190164914 |
Kind Code |
A1 |
Hu; Chih-Chia ; et
al. |
May 30, 2019 |
Seal Ring for Hybrid-Bond
Abstract
A structure includes a first die and a second die. The first die
includes a first oxide bonding layer having a first plurality of
bond pads disposed therein and a first seal ring disposed in the
first oxide bonding layer. The first oxide bonding layer extends
over the first seal ring. The second die includes a second oxide
bonding layer having a second plurality of bond pads disposed
therein. The first plurality of bond pads is bonded to the second
plurality of bond pads. The first oxide bonding layer is bonded to
the second oxide bonding layer. An area interposed between the
first seal ring and the second oxide bonding layer is free of bond
pads.
Inventors: |
Hu; Chih-Chia; (Taipei,
TW) ; Kuo; Chun-Chiang; (Kaohsiung, TW) ; Jan;
Sen-Bor; (Tainan City, TW) ; Chen; Ming-Fa;
(Taichung City, TW) ; Chen; Hsien-Wei; (Hsinchu,
TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Taiwan Semiconductor Manufacturing Company, Ltd. |
Hsinchu |
|
TW |
|
|
Family ID: |
66633562 |
Appl. No.: |
16/003654 |
Filed: |
June 8, 2018 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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62592856 |
Nov 30, 2017 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 24/08 20130101;
H01L 2224/80896 20130101; H01L 23/5226 20130101; H01L 29/0649
20130101; H01L 2224/05555 20130101; H01L 24/33 20130101; H01L 24/05
20130101; H01L 24/94 20130101; H01L 2224/05687 20130101; H01L
2224/04 20130101; H01L 24/06 20130101; H01L 23/562 20130101; H01L
2225/06565 20130101; H01L 2224/94 20130101; H01L 2224/80895
20130101; H01L 2224/08145 20130101; H01L 2224/80201 20130101; H01L
25/50 20130101; H01L 2225/06593 20130101; H01L 2224/05554 20130101;
H01L 2224/05647 20130101; H01L 2225/06568 20130101; H01L 24/03
20130101; H01L 2224/80907 20130101; H01L 2924/3512 20130101; H01L
23/53295 20130101; H01L 2224/05551 20130101; H01L 2225/06524
20130101; H01L 25/0657 20130101; H01L 24/83 20130101; H01L 23/585
20130101; H01L 24/09 20130101; H01L 2224/80948 20130101; H01L
2224/09517 20130101; H01L 2225/06513 20130101; H01L 24/80 20130101;
H01L 2224/06136 20130101; H01L 2224/06517 20130101; H01L 2224/05096
20130101; H01L 2224/06051 20130101; H01L 2224/06131 20130101; H01L
2224/94 20130101; H01L 2224/80 20130101; H01L 2224/80201 20130101;
H01L 2924/00012 20130101; H01L 2224/05687 20130101; H01L 2924/05442
20130101; H01L 2224/05647 20130101; H01L 2924/00014 20130101; H01L
2224/04 20130101; H01L 2224/08 20130101 |
International
Class: |
H01L 23/58 20060101
H01L023/58; H01L 23/522 20060101 H01L023/522; H01L 23/532 20060101
H01L023/532; H01L 23/00 20060101 H01L023/00; H01L 29/06 20060101
H01L029/06 |
Claims
1. A structure comprising: a first die, the first die comprising: a
first oxide bonding layer having a first plurality of bond pads
disposed therein, and a first seal ring disposed in the first oxide
bonding layer, wherein the first oxide bonding layer extends over
the first seal ring; and a second die, the second die comprising: a
second oxide bonding layer having a second plurality of bond pads
disposed therein, wherein the first plurality of bond pads is
bonded to the second plurality of bond pads, wherein the first
oxide bonding layer is bonded to the second oxide bonding layer,
and wherein an area interposed between the first seal ring and the
second oxide bonding layer is free of bond pads.
2. The structure of claim 1, wherein the first plurality of bond
pads is directly bonded to the second plurality of bond pads in a
metal-to-metal bond which is free of a eutectic material, and
wherein the first oxide bonding layer is fusion bonded to the
second oxide bonding layer.
3. The structure of claim 1, wherein the second oxide bonding layer
extends over a second seal ring, and an area directly aligned with
the second seal ring is free of the second plurality of bond
pads.
4. The structure of claim 3, wherein the first seal ring along a
first edge of the first die and the second seal ring along a first
edge of the second die are aligned.
5. The structure of claim 4, wherein the first seal ring along a
second edge of the first die and the second seal ring are along a
second edge of the second die are offset.
6. The structure of claim 1, wherein each edge of the first die is
offset from each respective edge of the second die.
7. The structure of claim 1, wherein the first die further
comprises a semiconductor substrate and an interconnect disposed on
the semiconductor substrate, wherein the first seal ring comprises
a first portion in the interconnect coupled to the substrate, and a
second portion embedded in the first oxide bonding layer coupled to
the first portion.
8. The structure of claim 7, wherein a passivation layer is
interposed between the first oxide bonding layer and the
semiconductor substrate, wherein the first portion of the first
seal ring is coupled to the second portion of the first seal ring
by a third portion of the first seal ring, the third portion of the
first seal ring extending through the passivation layer.
9. A method, comprising: determining an alignment of a first die to
a second die by aligning active bond pads of the first die to
corresponding active bond pads of the second die, wherein a first
area of the first die and a second area of the second die are
aligned with a seal ring of the second die; removing all bond pads
in the first area of the first die; removing all bond pads in the
second area of the second die; and bonding the first die to the
second die according to the alignment.
10. The method of claim 9, wherein the bonding comprises: fusion
bonding the first area of the first die to the second area of the
second die, wherein an interface of the first area and the second
area is free of metal features.
11. The method of claim 9, further comprising: forming first bond
pads on the first die, the first bond pads including the active
bond pads of the first die and dummy bond pads of the first die;
and forming second bond pads on the second die, the second bond
pads including the active bond pads of the second die and dummy
bond pads of the second die.
12. The method of claim 11, wherein the first bond pads of the
first die are formed in a pattern and wherein a width of the first
area of the first die is greater than a pitch spacing of the first
bond pads of the first die.
13. The method of claim 9, wherein the second area of the second
die extends around a periphery of the second die.
14. The method of claim 13, wherein the first area of the first die
corresponds to the second area of the second die, the method
further comprising, forming one or more bond pads outside the first
area of the first die.
15. The method of claim 9, wherein the determining the alignment
further comprises aligning the seal ring of the second die with a
portion of a seal ring of the first die.
16. The method of claim 9, further comprising: forming a ring-like
bonding interface over and coupled to the seal ring of the second
die.
17. A method comprising: determining a first device layout of bond
pads disposed at a surface of a first device; determining a second
device layout of bond pads disposed at a surface of a second
device, the second device having a seal ring; determining an
alignment which aligns a first active bond pad of the first device
to a second active bond pad of the second device, wherein the
alignment causes the seal ring to align with a first region of the
first die; removing first bond pads in the first region from the
first device layout of bond pads; removing second bond pads in a
second region of the second device, wherein the second bond pads
align with the first bond pads according to the alignment; bonding
the first active bond pad to the second active bond; and bonding
the first region to the second region.
18. The method of claim 17, wherein an interface of the first
region and the second region is substantially free of metal
features.
19. The method of claim 17, further comprising: forming a first
ring metal in the first region; forming a second ring metal in the
second region; and bonding the first ring metal to the second ring
metal.
20. The method of claim 19, further comprising: coupling the second
ring metal to the seal ring.
Description
PRIORITY CLAIM AND CROSS-REFERENCE
[0001] This application claims priority to and the benefit of U.S.
Provisional Application No. 62/592,856, filed on Nov. 30, 2017,
entitled "Seal Ring for Hybrid-Bond," which application is hereby
incorporated herein by reference in its entirety.
BACKGROUND
[0002] In wafer-to-wafer bonding technology, various methods have
been developed to bond two package components (such as wafers)
together. The available bonding methods include fusion bonding,
eutectic bonding, direct metal bonding, hybrid bonding, and the
like. In the fusion bonding, an oxide surface of a wafer is bonded
to an oxide surface or a silicon surface of another wafer. In the
eutectic bonding, two eutectic materials are placed together, and
are applied with a high pressure and a high temperature. The
eutectic materials are hence molten. When the melted eutectic
materials are solidified, the wafers are bonded together. In the
direct metal-to-metal bonding, two metal pads are pressed against
each other at an elevated temperature, and the inter-diffusion of
the metal pads causes the bonding of the metal pads. In the hybrid
bonding, the metal pads of two wafers are bonded to each other
through direct metal-to-metal bonding, and an oxide surface of one
of the two wafers is bonded to an oxide surface or a silicon
surface of the other wafer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] Aspects of the present disclosure are best understood from
the following detailed description when read with the accompanying
figures. It is noted that, in accordance with the standard practice
in the industry, various features are not drawn to scale. In fact,
the dimensions of the various features may be arbitrarily increased
or reduced for clarity of discussion.
[0004] FIG. 1 illustrates a schematic top view of wafer, in
accordance with some embodiments.
[0005] FIGS. 2a through 2c illustrate various views of a die, in
accordance with some embodiments.
[0006] FIG. 3 illustrates a schematic top view of wafer, in
accordance with some embodiments.
[0007] FIGS. 4a through 4c illustrate various views of a die, in
accordance with some embodiments.
[0008] FIG. 5 illustrates a cross-sectional view of two bonded
dies, in accordance with some embodiments.
[0009] FIG. 6 illustrates a schematic top view of wafer, in
accordance with some embodiments.
[0010] FIGS. 7a through 7c illustrate various views of a die, in
accordance with some embodiments.
[0011] FIG. 8 illustrates a schematic top view of wafer, in
accordance with some embodiments.
[0012] FIGS. 9a through 9c illustrate various views of a die, in
accordance with some embodiments.
[0013] FIGS. 10a through 10c and FIG. 11 illustrates various views
of two bonded dies, in accordance with some embodiments.
[0014] FIG. 12 illustrates a schematic top view of wafer, in
accordance with some embodiments.
[0015] FIGS. 13a through 13c illustrate various views of a die, in
accordance with some embodiments.
[0016] FIG. 14 illustrates a cross-sectional view of two bonded
dies, in accordance with some embodiments.
[0017] FIG. 15 illustrates a cross-sectional view of two bonded
dies, in accordance with some embodiments.
[0018] FIG. 16 illustrates a cross-sectional view of two bonded
dies, in accordance with some embodiments.
[0019] FIG. 17 is a flow diagram for altering the design layout of
bond pads on a die, in accordance with some embodiments.
[0020] FIG. 18 is a flow diagram for altering the design layout of
bond pads on a die, in accordance with some embodiments.
DETAILED DESCRIPTION
[0021] The following disclosure provides many different
embodiments, or examples, for implementing different features of
the invention. Specific examples of components and arrangements are
described below to simplify the present disclosure. These are, of
course, merely examples and are not intended to be limiting. For
example, the formation of a first feature over or on a second
feature in the description that follows may include embodiments in
which the first and second features are formed in direct contact,
and may also include embodiments in which additional features may
be formed between the first and second features, such that the
first and second features may not be in direct contact. In
addition, the present disclosure may repeat reference numerals
and/or letters in the various examples. This repetition is for the
purpose of simplicity and clarity and does not in itself dictate a
relationship between the various embodiments and/or configurations
discussed.
[0022] Further, spatially relative terms, such as "beneath,"
"below," "lower," "above," "upper" and the like, may be used herein
for ease of description to describe one element or feature's
relationship to another element(s) or feature(s) as illustrated in
the figures. The spatially relative terms are intended to encompass
different orientations of the device in use or operation in
addition to the orientation depicted in the figures. The apparatus
may be otherwise oriented (rotated 90 degrees or at other
orientations) and the spatially relative descriptors used herein
may likewise be interpreted accordingly.
[0023] Embodiments described herein provide a hybrid bonding of two
distinct dies. Dies may be designed with bond pads to provide
electrical and mechanical attachment points to bond another die or
device thereto to form a package. Some of these bond pads may be
"active," that is, electrically coupled to a component within the
die, or "dummy," that is, electrically decoupled (e.g., floating)
from any component with in the die. When a die is hybrid bonded to
another die or component, dielectric materials at the surface of
each die are aligned and fusion bonded together and metal bond pads
in each die are aligned and directly bonded together. Die formation
and processing to achieve suitable mating surfaces for hybrid
bonding have heightened tolerances to help achieve a stronger or
more reliable bonding. As such, to avoid tolerance variances
resulting from die processing, such as dishing, a bond pad pattern
is usually carried out over the entire surface of the die so that
Chemical Mechanical Polishing (CMP) processes or the like uniformly
affect the surface of the die for a predictable and uniform result.
In some embodiments of the present disclosure, however, the design
of the dies is altered to provide a zone where dummy bond pads are
removed for mating to an area over a seal ring structure. Removing
the dummy bond pads from the layout has been shown to increase
bonding yield, especially where the spacing of the bond pads in the
pattern is small. In other embodiments, rather than removing the
dummy bond pads, the design is altered to mechanically and
electrically couple the dummy bond pads to the seal ring.
Embodiments described herein may be used in die-on-die,
wafer-on-wafer (WoW), chip-on-chip (CoC), or chip-on-wafer (CoW)
hybrid bonding processes where dummy bond pads are removed from an
otherwise uniform contact pad layout design on the die, dummy bond
pads are coupled to a seal ring, or a combination thereof.
[0024] Referring to the illustrated drawings, in Figures providing
multiple views, Figures ending in an "a" indicate a perspective
view illustration, figures ending in a "b" indicate a cross-section
view illustration, and figures ending in a "c" indicate a top down
view or plan view illustration. FIGS. 1-5 illustrate intermediate
stages of a hybrid bonding technique, in accordance with some
embodiments. FIGS. 1 through 2c illustrate a die 112, FIGS. 3
through 4c illustrate another die 212, and FIG. 5 illustrates a
hybrid bonding of die 112 with die 212, in accordance with some
embodiments.
[0025] FIG. 1 illustrates a schematic top view of wafer 100 in
accordance with some embodiments. Wafer 100 includes dies 112 and
the adjoining scribe lines 114 and scribe lines 116, wherein scribe
lines 114 and scribe lines 116 separate dies 112 from each other.
Scribe lines 114 have longitudinal directions parallel to the X
direction, and scribe lines 116 have longitudinal directions
parallel to the Y direction, which is perpendicular to the X
direction. In each of dies 112, there may be one or more seal rings
(e.g., shown as 136 in FIG. 2a), wherein the outer boundaries of
the seal ring unit 136 define the outer boundaries of dies 112.
Each of the scribe lines 114 is between and adjoining two rows of
dies 112, and each of the scribe lines 116 is between and adjoining
two columns of dies 112. It is noted that wafer 100 is intended to
be an example only, and the sizes of dies 112, scribe lines 114 and
scribe lines 116, etc. may vary based on the die designs.
[0026] FIG. 2a illustrates a schematic perspective view of die 112.
Die 112 in FIG. 2a may be singulated from wafer 100 or may still be
intact with wafer 100. Seal ring unit 136 (shown in phantom) is
disposed at a periphery of die 112 under the surface of the die and
may include one or more distinct seal rings (described in greater
detail below with respect to FIGS. 2b and 2c). In some embodiments,
die 112 comprises an array of bond pads 142 set over and around a
device area 118 of die 112. In some embodiments, the device area
118 may include the entire area of die 112 within seal ring unit
136. In other embodiments, the device area 118 may include a
portion of the area of die 112 within seal ring unit 136, such as
illustrated in FIG. 2a. In some embodiments, the device area 118
may include all the available bond pads 142 on the die or a subset
of the available bond pads 142. Arrangements of bond pads 142 may
be made in a pattern other than an array pattern. Bond pads 142 may
be sized similarly or differently, depending on the design of the
bond pads 142 on die 112.
[0027] Die 112 may include a logic device, micro-electro-mechanical
systems (MEMS) device, integrated passive device (IPD), driver, or
memory device such as memory cells including, and not limited to,
Static Random Access Memory (SRAM) cells, Dynamic Random Access
Memory (DRAM) Cells, Magneto-Resistive Random Access Memory (MRAM)
cells, or the like. Die 112 may include other types of devices.
[0028] Die 112 may have first width, e.g., in the X direction of
w1, which may be between about 2000 .mu.m and about 26000 .mu.m,
such as about 10000 .mu.m. Die 112 may have second width (or
length), e.g., in the Y direction of w2, which may be between about
2000 .mu.m and about 33000 .mu.m, such as about 10000 .mu.m. Other
dimensions for die 112 may be used.
[0029] FIG. 2b illustrates a cross-sectional view of die 112. The
cross-section of FIG. 2b is a portion of a cross-section taken
along the line A-A of FIG. 2c, however the details may be varied
from one view to another for the purposes of discussion. Die 112
includes a substrate 122, which may be a semiconductor substrate,
such as a silicon substrate, a silicon germanium substrate, a
silicon carbon substrate, an III-V compound semiconductor
substrate, or the like. A device area 118 is formed at the surface
or inside substrate 122. Device area 118 may comprise active or
passive devices, such as transistors, resistors, capacitors,
diodes, and the like. In some embodiments, device area 118 may
comprise an encapsulated die.
[0030] An interconnect structure 126 may be formed over the
substrate 122. Interconnect structure 126 may include insulating
layers 128, such as an inter-layer dielectric (ILD) and/or
inter-metal dielectric layers (IMD) and conductive features (e.g.,
metal lines 127 and vias 129) formed in alternating layers over
substrate 122 using any suitable method. Interconnect structure 126
may connect various active and/or passive devices in device area
118 of substrate 122 to form functional circuits. The insulating
layers 128 may comprise low-k dielectric materials having k values,
for example, lower than about 4.0 or even 2.8. In some embodiments,
insulating layers 128 may comprise undoped silicate glass (USG),
spin-on carbon, and the like. The thickness t1 of interconnect
structure 126 may be between about 0.1 .mu.m and about 6 .mu.m,
such as about 4 .mu.m. Other thicknesses may be used.
[0031] In some embodiments where device area 118 is an area of
substrate 122 used to create various active and passive devices,
interconnect structure 126 may be formed using a dual damascene
process. A dual damascene process may include, for example,
depositing insulating layers 128 (which may be formed as single
layers or multiple layers separated by one or more etch stop
layers), forming trenches in and via openings in the insulating
layers to expose some portions of the metal lines 127 and vias 129,
and filling the trenches and via openings with a conductive
material to form more metal lines 127 and vias 129. Optional metal
pads 131 can be formed in a top most layer of the interconnect
structure 126 in a manner similar to forming the metal lines 127. A
CMP is then performed to remove excess conductive material.
Accordingly, the portions of the conductive material filling the
trenches in the insulating layers 128 become the metal lines 127,
respectively, while the portions of the conductive material filling
the via openings become vias 129.
[0032] In embodiments where device area 118 is an encapsulated die,
in an example to form interconnect structure 126, first an
insulating layer 128 may be deposited over the substrate 122 and
device area 118. In some embodiments, the insulating layer 128 is
formed of a polymer, which may be a photo-sensitive material such
as PBO, polyimide, BCB, or the like, that may be patterned using a
lithography mask. In other embodiments, the insulating layer 128 is
formed of a nitride such as silicon nitride; an oxide such as
silicon oxide, PSG, BSG, BPSG; or the like. The insulating layer
128 may be formed by spin coating, lamination, CVD, the like, or a
combination thereof. The insulating layer 128 may be formed of
low-k materials.
[0033] The insulating layer 128 is then patterned. The patterning
forms openings to expose portions of substrate 122 and device area
118 which include contacts (not shown) to the devices. The
patterning may be by an acceptable process, such as by exposing the
insulating layer 128 to light when the insulating layer 128 is a
photo-sensitive material or by etching using, for example, an
anisotropic etch. If the insulating layer 128 is a photo-sensitive
material, the insulating layer 128 can be developed after the
exposure.
[0034] To form a first layer of metal lines 127 and vias 129, a
seed layer (not shown) is formed over the insulating layer 128 and
in openings through the insulating layer 128. In some embodiments,
the seed layer is a metal layer, which may be a single layer or a
composite layer comprising a plurality of sub-layers formed of
different materials. In some embodiments, the seed layer comprises
a titanium layer and a copper layer over the titanium layer. The
seed layer may be formed using, for example, PVD or the like. A
photo resist is then formed and patterned on the seed layer. The
photo resist may be formed by spin coating or the like and may be
exposed to light for patterning. The pattern of the photo resist
corresponds to the pattern of the metal lines 127. The patterning
forms openings through the photo resist to expose the seed layer. A
conductive material is formed in the openings of the photo resist
and on the exposed portions of the seed layer. The conductive
material may be formed by plating, such as electroplating or
electroless plating, or the like. The conductive material may
comprise a metal, like copper, titanium, tungsten, aluminum, or the
like. Then, the photo resist and portions of the seed layer on
which the conductive material is not formed are removed. The photo
resist may be removed by an acceptable ashing or stripping process,
such as using an oxygen plasma or the like. Once the photo resist
is removed, exposed portions of the seed layer are removed, such as
by using an acceptable etching process, such as by wet or dry
etching. The remaining portions of the seed layer and conductive
material form the pattern of the metal lines 127 and vias 129. The
vias 129 are formed in openings through insulating layer 128 to,
e.g., the substrate 122 or device area 118.
[0035] A subsequent insulating layer 128 may then be deposited over
the metal lines 127 and vias 129 and the process repeated as needed
to form a multilayer interconnect which forms a circuit and
provides input/output to the substrate 122 and device area 118.
Optional metal pads 131 may be formed in a top most layer of the
interconnect structure 126 in a manner similar to forming the metal
lines 127.
[0036] Interconnect structure 126 also includes a seal ring
structure 132A formed in a similar manner as the other layers of
the interconnect structure 126, by alternating layers of metal
lines and insulating materials where the metal lines are coupled by
vias. The seal ring structure 132A may be included to help prevent
delamination of the layers in the interconnect structure 126. In
some embodiments, an additional seal ring structure 134A may be
included. Seal ring structure 134A may be formed in a similar
manner as the other layers of the interconnect structure 126 and
seal ring structure 132A. The seal ring structure 134A may be wider
than seal ring structure 132A, narrower than seal ring structure
132A, or the same width as seal ring structure 132A.
[0037] A passivation layer 138 may be formed over the interconnect
structure 126 and patterned to form openings therein, exposing a
top metal layer of the interconnect structure 126 and exposing a
top metal layer of the seal ring structure 132A and a top metal
layer of the seal ring structure 134A. Passivation layer 138 may be
formed by the deposition and patterning of an insulating layer. In
some embodiments, the passivation layer 138 is formed of a polymer,
which may be a photo-sensitive material such as PBO, polyimide,
BCB, or the like, that may be patterned using a lithography mask.
In other embodiments, the passivation layer 138 is formed of a
nitride such as silicon nitride; an oxide such as silicon oxide,
PSG, BSG, BPSG; or the like. The passivation layer 138 may be
formed by spin coating, lamination, CVD, the like, or a combination
thereof. Passivation layer 138 may be between about 0.01 .mu.m and
2 .mu.m thick, such as about 0.9 .mu.m thick. Other thicknesses may
be used.
[0038] The passivation layer 138 is patterned to form openings to
expose portions of the top metal layer of the interconnect
structure 126. The patterning may be by an acceptable process, such
as by exposing the passivation layer 138 to light when the
passivation layer 138 is a photo-sensitive material or by etching
using, for example, an anisotropic etch. If the passivation layer
138 is a photo-sensitive material, the passivation layer 138 can be
developed after the exposure.
[0039] Seal rings structure 132A may be extended through and above
the passivation layer 138. A via 132B may be formed in the
passivation layer 138 and an overlying seal ring metal 132C may be
formed over the passivation layer 138. The resulting seal ring 132
may therefore comprise seal ring structure 132A in interconnect
structure 126, seal ring via 132B through passivation layer 138,
and seal ring metal 132C. In some embodiments, additional seal
rings may be included. In embodiments having one or more other seal
rings, such as seal ring 134, such seal rings may similarly
comprise the seal ring structure, such as seal ring structure 134A
in the interconnect structure 126, a via, such as seal ring via
134B through passivation layer 138, and a seal ring metal, such as
seal ring metal 134C. Seal ring unit 136 may comprise all of the
seal rings surrounding the periphery of the die (e.g., seal ring
132, seal ring 134, and so forth). Seal ring metal 132C and seal
ring metal 134C may form a continuous loop around the periphery of
the die in a top down view.
[0040] Seal ring via 132B and 134B may be formed by a process
similar to the formation of the metal lines and vias of
interconnect structure 126, described above. The passivation layer
138 may be patterned to form openings therein corresponding to the
seal ring via 132B and seal ring via 134B. A seed layer (not shown)
may then be deposited over the passivation layer and in the
openings. A subsequent mask can be deposited over the seed layer
and patterned to create openings according to the seal ring metal
132C and seal ring metal 134C. The seal ring via 132B and seal ring
metal 132C can then be formed by depositing a metal material such
as copper, titanium, the like, or a combination thereof, formed by
a plating process, such as electroless plating, electroplating, or
the like on the seed layer first deposited in the openings and
continuing the plating until the seal ring metal 132C has reached a
desired height. The resulting seal ring metal 132C and seal ring
metal 134C may have a height h1 of about 0.1 .mu.m to about 2.8
.mu.m, such as about 2.8 .mu.m. Other heights may be used for the
seal ring metal 132C and seal ring metal 134C. For example, in some
embodiments, h1 may be less than 0.1 .mu.m or greater than 2.8
.mu.m. Seal ring via 134B and seal ring metal 134C may be formed
simultaneously with seal ring via 132B and seal ring metal 132C.
Following the formation of the seal ring 132 and seal ring 134, the
mask may be removed by a suitable process, such as by ashing, and
the remaining seed layer stripped away.
[0041] Crack stoppers 130 may be formed around the die using
processes and materials similar to those discussed above with
respect to seal ring 132 and seal ring 134, with the exception that
the topmost layer of the crack stoppers 130 are not formed in a
continuous ring, but are formed as discontinuous metal layers (see,
e.g., the example top profile of crack stoppers 130 in FIG. 2c). In
some embodiments, the crack stoppers 130 may extend into
interconnect structure 126 in discontinuous segments which are
aligned with the topmost layer of the crack stoppers 130. In some
embodiments, the portion of the crack stoppers 130 in interconnect
structure 126 may be formed in a continuous ring, similar to seal
ring structure 132a, described above. Single or multiple rows of
crack stoppers 130 may be used (see, e.g., FIG. 2c), in some
embodiments, including one, two, three, four, five, or six, rows
and so forth. Additional rows of crack stoppers 130 may be used.
Crack stoppers 130 may be offset from one another to inhibit a
crack from entering the inner part of die 112. For example, a crack
which may start from an outside edge of die 112 and proceed toward
the inner part of die 112 may be halted by one of the crack
stoppers 130 and be stopped there instead of encroaching into the
inner part of die 112. Each crack stopper 130 is designed to end
propagation of any such cracks, rather than allow the crack to
proceed past the crack stoppers 130 to the inner part of the die
112. Crack stoppers 130 may appear in a top down view (see FIG. 2c)
as round, square, rectangular, or any suitable shape.
[0042] A bond dielectric layer 140 may be formed over the
passivation layer 138. In some embodiments, bond dielectric layer
140 is an oxide layer, which may comprise silicon oxide. In other
embodiments, bond dielectric layer 140 comprises other silicon
and/or oxygen containing materials such as SiON, SiN, or the like,
and may be formed by any suitable deposition technique. The bond
dielectric layer 140 may be deposited to a thickness t2 of about
1.5 .mu.m to about 7 .mu.m, such as about 6 .mu.m. Other
thicknesses may be used. The top surfaces of the seal ring metal
132C and seal ring metal 134C may be covered by the bond dielectric
layer 140. The distance d3 between the top surfaces of the seal
ring metal 132C, for example, and the top surface of the bond
dielectric layer 140 may be about 1.2 .mu.m to about 1.4 .mu.m,
such as about 1.3 .mu.m. Other distances for distance d3 may be
used.
[0043] Bond pads 142 are formed in bond dielectric layer 140, and
may be electrically coupled to device area 118 through metal lines
and vias, including bond pad vias 144. Bond pads 142 may be formed
of copper, aluminum, nickel, tungsten, or alloys thereof. The top
surface of bond dielectric layer 140 and the top surfaces of bond
pads 142 are level with each other, which is achieved through a
planarization that is performed during the formation of bond pads
142. The planarization may comprise Chemical Mechanical Polish
(CMP).
[0044] Bond pads 142 may be electrically connected to metal lines
127 and vias 129 by a corresponding bond pad via 144 for each bond
pad 142. In some embodiments, no bond pad vias 144 are formed
between bond pads 142 and the top metal of metal lines 127.
Accordingly, the bond pads may be in direct physical contact with
the top metal of the metal lines 127. In some embodiments, one or
more bond pad vias 144 may extend to the top of the bond dielectric
layer 140 and the corresponding bond pad 142 may be omitted.
[0045] Bond pad vias 144 may be formed by patterning the bond
dielectric layer 140 to form openings which expose metal lines 127
or optional metal pads 131 of interconnect structure 126. A metal
material such as copper, titanium, the like, or a combination
thereof, may be deposited in the openings by a suitable deposition
process, such as by a plating process, such as electroless plating,
electroplating, or the like on an optional seed layer first
deposited in the openings. In some embodiments, after formation of
the bond pad vias 144, an additional layer of the bond dielectric
layer 140 may be deposited over the bond pad vias 144, and the bond
dielectric layer 140 patterned again to provide openings
corresponding to the bond pads 142. Bond pads 142 may then be
formed by depositing a metal material such as copper, titanium, the
like, or a combination thereof, formed by a plating process, such
as electroless plating, electroplating, or the like on an optional
seed layer first deposited in the openings. In some embodiments,
other deposition processes may be used instead of or in combination
with a plating process, such as ALD, CVD, and the like. Excess
material of the bond pads 142 may be removed by planarization, such
as a CMP.
[0046] As shown in FIGS. 2a, 2b, and 2c, bond pads 142 are
distributed uniformly or substantially uniformly (for example, with
a pattern-density variation smaller than about 10 percent). The
(substantially) uniformly distributed bond pads 142 may be
distributed throughout an entirety or substantially the entirety of
(for example, more than 90 or 95 percent) of die 112. However,
rather than the (substantially) uniformly distributed bond pads 142
extending all the way to the edges of die 112, including over the
seal ring unit 136, the design may be altered by removing the bond
pads which would be over the seal ring unit 136 if the adjacent
pattern were allowed to continue over the seal ring unit 136.
Furthermore, all or substantially all (such as more than 90
percent) of bond pads 142 throughout the entire die 112 may have a
same top-view shape, a same top-view size, and/or a same pitch.
Accordingly, bond pads 142 may have a uniform pattern density
throughout die 112, except for the area over the seal ring unit
136. In some embodiments, the distance dl may be between about 2
.mu.m and about 10 .mu.m, such as about 9 .mu.m. Other distances
for the pitch may be used. In some embodiments, the width d4 of the
seal ring unit 136 and crack stop unit 130 may be between about 20
.mu.m and about 22 .mu.m, such as about 22 .mu.m. In some
embodiments, the width d4 of the seal ring unit 136 and crack stop
unit 130 may be less than 20 .mu.m, such as about 4 .mu.m or may be
greater than 22 .mu.m, such as about 30 .mu.m. Other distances may
be used.
[0047] Removing the bond pads which would be over the seal ring
unit 136 produces keep out zone 150. Keep out zone 150 may extend
further toward the inner part of die 112 than the seal ring unit
136. For example, keep out zone 150 may include an area over crack
stoppers 130. In some embodiments, keep out zone 150 may include an
area over a portion of metal lines 127, vias 129, or optional metal
pads 131 of interconnect structure 126. A pattern design for bond
pads 142 may initially include bond pads in keep out zone 150. The
pattern design may then be altered before manufacturing to remove
bond pads 142 from the design where keep out zone 150 is located on
die 112. For example, as illustrated in FIG. 2b, keep out zone 150
corresponds to the location of the seal ring unit 136 and extends
into the inner part of die 112 over the crack stoppers 130 and over
a portion of a metal line 127 of interconnect structure 126. In
other embodiments, the keep out zone may be located in other areas
of the die (see, e.g., FIG. 7b and its description) which is
described in greater detail in discussing other embodiments, below.
The location of keep out zone 150 is based at least in part on
where a second die will be bonded to die 112. When the second die
has the same footprint dimensions, the keep out zone 150 will be
located at the periphery of the die, corresponding to the area of
the seal ring unit 136. When the second die has a smaller
footprint, the keep out zone 150 will be located at least in part
in an interior part of the die. Examples of such embodiments are
described in greater detail below with respect to FIGS. 6 through
11.
[0048] In some embodiments, bond pads 142 may include a plurality
of active metal pads 142A and a plurality of dummy metal pads 142B.
Dummy metal pads 142B do not have electrical functions. Active
metal pads 142A may be electrically connected to device area 118
through bond pad vias 144 and interconnect structure 126. Dummy
metal pads 142B are electrically disconnected from devices in die
112, where the symbol "x" represents that no electrical connection
exists to connect dummy metal pads 142B to device area 118.
Accordingly, dummy metal pads 142B may be electrically floating. In
some embodiments, active metal pads 142A and dummy metal pads 142B
have the same top-view shape, the same top-view size, and comprise
the same material. Furthermore, active metal pads 142A and dummy
metal pads 142B are formed simultaneously. In alternative
embodiments, active metal pads 142A and dummy metal pads 142B have
different top-view shapes and/or different top-view sizes.
[0049] Active metal pads 142A and dummy metal pads 142B may have a
same top-view shape and/or a same top-view size. Therefore, whether
a bond pad 142 is used as an active metal pad 142A or a dummy metal
pad 142B is determined by its electrical connection such as whether
it is connected to device area 118 or not. It should be understood
that reference in the figures to a bond pad 142 contemplates both
an active metal pad 142A and dummy metal pad 142B depending on the
die design. The designers who design die 112 may uniformly
distribute bond pads 142 throughout die 112 and/or wafer 100, and
the electrical connections from device area 118 to bond pads 142
are made depending on the convenience in metal routing. For
example, when an electrical connection needs to be made to connect
to a part of device area 118, the most convenient bond pad 142,
which may be the one nearest to the part of device area 118, or the
one that is easiest to route to, is selected as the active metal
pad 142A. The bond pads 142 that are not selected thus become dummy
metal pads 142B.
[0050] FIG. 2c illustrates a top view of a corner portion of die
112. Although seal ring unit 136 and crack stoppers 130 would not
be visible in the top view, they have been illustrated for context
and provided with dashed outside edges. The seal ring unit 136
comprising seal ring 132 and seal ring 134 is illustrated to
continue around the periphery of die 112. All the bond pads 142 are
contained within the seal ring unit 136. A keep out zone 150 for
the seal ring unit 136 provides an area over the seal ring unit 136
which is free from bond pads 142. The keep out zone 150 may
continue around the entire edge of die 112. The top surface of the
seal ring unit 136 is below the surface of the bond dielectric
layer 140. As such, the keep out zone 150 provides a
bond-dielectric-layer area free of metal features continuously
extending from one edge of the keep out zone to the other edges of
the keep out zone for fusion bonding to another die while being
unencumbered by any metal features. When the keep out zone 150 is
aligned to a keep out zone on another die, and bonded thereto, the
bond yield rate is improved. The width d4 (see FIG. 2b) of the keep
out zone 150 may be between about 20 .mu.m and about 21.6 .mu.m,
such as about 21.6 .mu.m. Other distances may be used for the width
of the keep out zone 150. The length of the keep out zone 150 may
vary based on the size of the die which is to be bonded to die
112.
[0051] FIG. 2c also illustrates that some bond pads 142 may be
active bond pads having an active metal pad 142A which is coupled
to a bond pad via 144 (shown in phantom). Other bond pads 142 in
the pattern may be dummy bond pads having a dummy metal pad 142B
which is not coupled to a bond pad via 144.
[0052] FIGS. 3 through 4c illustrate another die 212 in accordance
with some embodiments. FIG. 3 illustrates a schematic top view of
wafer 200 in accordance with some embodiments. Wafer 200 includes
dies 212 and the adjoining scribe lines 214 and 216, wherein scribe
lines 214 and 216 separate dies 212 from each other. Scribe lines
214 have longitudinal directions parallel to the X direction, and
scribe lines 216 have longitudinal directions parallel to the Y
direction, which is perpendicular to the X direction. In each of
dies 212, there may be one or more seal rings (e.g., shown as 236
in FIG. 4a), wherein the outer boundaries of the seal rings define
the outer boundaries of dies 212. Each of the scribe lines 214 is
between and adjoining two rows of dies 212, and each of the scribe
lines 216 is between and adjoining two columns of dies 212. It is
noted that wafer 200 is intended to be an example only, and the
sizes of dies 212, scribe lines 214 and 216, etc. may vary based on
the die designs.
[0053] FIG. 4a illustrates a schematic perspective view of die 212.
Die 212 in FIG. 4a may be singulated from wafer 200 or may still be
intact with wafer 200. Seal ring unit 236 (shown in phantom) is
disposed at a periphery of die 212 under the surface of die 212 and
may include one or more distinct seal rings (described in greater
detail below with respect to FIGS. 4b and 4c). In some embodiments,
die 212 comprises an array of bond pads 242 set over and around a
device area 218 of die 212. In some embodiments, the device area
218 may include the entire area of die 212 within seal ring unit
236. In other embodiments, the device area 218 may include a
portion of the area of die 212 within seal ring unit 236, such as
illustrated in FIG. 4a. In some embodiments, the device area 218
may include all the available bond pads 242 on the die or a subset
of the available bond pads 242. Arrangements of bond pads 242 may
be made in a pattern other than an array pattern. Bond pads 242 may
be sized similarly or differently, depending on the design of the
bond pads 242 on die 212.
[0054] Die 212 may be a similar or identical device as die 112, in
some embodiments and may have similar dimensions thereto, including
thicknesses of layers and so forth. In some embodiments, die 212
can be different than die 112, and may include a logic device or
memory device such as memory cells including, and not limited to,
Static Random Access Memory (SRAM) cells, Dynamic Random Access
Memory (DRAM) Cells, Magneto-Resistive Random Access Memory (MRAM)
cells, or the like. Die 212 may include other types of devices.
[0055] FIG. 4b illustrates a cross-sectional view of die 212. The
cross-section of FIG. 4b is a portion of a cross-section taken
along the line A-A of FIG. 4c, however the details may be varied
from one view to another for the purposes of discussion. Die 212
includes substrate 222 which may be a semiconductor substrate, such
as a silicon substrate, a silicon germanium substrate, a silicon
carbon substrate, an III-V compound semiconductor substrate, or the
like. A device area 218 is formed at the surface or inside
substrate 222. Device area 218 may comprise active or passive
devices, such as transistors, resistors, capacitors, diodes, and
the like. In some embodiments, device area 218 may comprise an
encapsulated die.
[0056] An interconnect structure 226 may be formed over the
substrate 222. Interconnect structure 226 may include insulating
layers 228, such as an inter-layer dielectric (ILD) and/or
inter-metal dielectric layers (IMD) and conductive features (e.g.,
metal lines 227, vias 229, and optional metal pads 231) formed in
alternating layers over substrate 222 using processes and materials
such as those described above with respect to interconnect
structure 126 of FIG. 2b, which are not repeated. Interconnect
structure 226 may connect various active and/or passive devices in
device area 218 of substrate 222 to form functional circuits.
[0057] The interconnect structure 226 also includes a seal ring
structure 232A formed in a similar manner as the other layers of
the interconnect structure 226, by alternating layers of metal
lines and insulating materials where the metal lines are coupled by
vias. The seal ring structure 232A may be included to help prevent
delamination of the layers in the interconnect structure 226. In
some embodiments, an additional seal ring structure 234A may be
included. Seal ring structure 234A may be formed in a similar
manner as the other layers of the interconnect structure 226 and
seal ring structure 232A. The seal ring structure 234A may be wider
than seal ring structure 232A, narrower than seal ring structure
232A, or the same width as seal ring structure 232A.
[0058] A passivation layer 238 may be formed over the interconnect
structure 226 and patterned to form openings therein, exposing a
top metal layer of the interconnect structure 226 (or optional
metal pad 221) and exposing a top metal layer of the seal ring
structure 232A and a top metal layer of the seal ring structure
234A. Passivation layer 238 may be formed using processes and
materials such as those discussed above with respect to passivation
layer 138, which are not repeated.
[0059] Seal ring structure 232A may be extended through and above
the passivation layer 238. A via 232B may be formed in the
passivation layer 238 and an overlying seal ring metal 232C may be
formed over the passivation layer 238. The resulting seal ring 232
may therefore comprise seal ring structure 232A in interconnect
structure 226, seal ring via 232B through passivation layer 238,
and seal ring metal 232C. In some embodiments, additional seal
rings may be included. In embodiments having another seal ring,
such as seal ring 234, such seal rings may similarly comprise the
seal ring structure, such as seal ring structure 234A in the
interconnect structure 226, a via, such as via 234B through
passivation layer 238, and a seal ring metal, such as seal ring
metal 234C. Seal ring unit 236 may comprise all of the seal rings
surrounding the periphery of the die (e.g., seal ring 232, seal
ring 234, and so forth). Seal ring metal 232C and seal ring metal
234C may form a continuous loop around the periphery of the die in
a top down view.
[0060] Seal ring via 232B or seal ring via 234B may be formed using
processes and materials such as those discussed above with respect
to seal ring via 132B and seal ring via 134B, which are not
repeated. Similarly, seal ring metal 232C and 234C may be formed
using processes and materials such as those discussed above with
respect to seal ring metal 132C and seal ring metal 134C, which are
not repeated.
[0061] Crack stoppers 230 may be formed around the die. Crack
stoppers 230 may be formed using processes and materials such as
described above with respect to crack stoppers 130 which are not
repeated.
[0062] A bond dielectric layer 240 may be formed over the
passivation layer 238. In some embodiments, bond dielectric layer
240 is an oxide layer, which may comprise silicon oxide. In other
embodiments, bond dielectric layer 240 comprises other silicon
and/or oxygen containing materials such as SiON, SiN, or the like.
Bond pads 242 are formed in bond dielectric layer 240, and may be
electrically coupled to device area 218 through metal lines and
vias, including bond pad vias 244. Bond pads 242 may be formed of
copper, aluminum, nickel, tungsten, or alloys thereof. The top
surfaces of the seal ring metal 232C and seal ring metal 234C may
be covered by the bond dielectric layer 240. The top surface of
bond dielectric layer 240 and the top surfaces of bond pads 242 are
level with each other, which is achieved through a planarization
that is performed during the formation of bond pads 242. The
planarization may comprise a CMP process.
[0063] Bond pads 242 may be electrically connected to metal lines
227 and vias 229 by a corresponding bond pad via 244 for each bond
pad 242. In some embodiments, no bond pad vias 244 are formed
between bond pads 242 and the top metal of metal lines 227.
Accordingly, the bond pads may be in direct physical contact with
the top metal of the metal lines 227. In some embodiments, one or
more bond pad vias 244 may extend to the top of the bond dielectric
layer 240 and the corresponding bond pad 242 may be omitted. Bond
pad vias 244 and bond pads 242 may be formed using processes and
materials such as those discussed above with respect to the bond
pad vias 144 and bond pads 142 of FIG. 2b, which are not
repeated.
[0064] In some embodiments, bond pads 242 may include a plurality
of active metal pads 242A and a plurality of dummy metal pads 242B,
similar to the active metal pads 142A and dummy metal pads 142B of
FIG. 2b.
[0065] Referring now to FIG. 4c, FIG. 4c illustrates a top view of
a corner portion of die 212. The seal ring unit 236 comprising seal
ring 232 and seal ring 234 is illustrated to continue around the
periphery of die 212. All the bond pads 242 are contained within
the seal ring unit 236. A keep out zone 250 for the seal ring unit
236 provides an area over the seal ring unit 236 which is free from
bond pads 242. Keep out zone 250 is similar in size and shape as
keep out zone 150 of die 112. Keep out zone 250 is sized to be
aligned to keep out zone 150 of die 112 and has a dielectric bond
area which continuously extends from one edge of the keep out zone
to the other edges of the keep out zone for fusion bonding to
another die while being unencumbered by any metal features. The top
surface of the seal ring unit 236 is below the surface of the bond
dielectric layer 240. As such, the keep out zone 250 provides a
dielectric bond area for fusion bonding to another die, such as die
112. Keep out zone 250 may be located using similar processes as
described above with respect to keep out zone 150 of FIGS. 2b and
2c.
[0066] Referring to FIG. 5, FIG. 5 illustrates a cross-section that
includes die 112 bonded to die 212 to form die package 213. Bonding
can be wafer-to-wafer where both wafers are directly bonded
together, chip-to-chip where two singulated chips (or dies) are
directly bonded together, or chip-to-wafer where one or more chips
(or dies) are directly bonded together, wherein the dielectric
layers of one die are fusion bonded to another die and the metal
layers of one die and another die are bonded together without using
any eutectic material, such as solder. For example, in a
wafer-to-wafer bonding, the bonding of wafer 100 to wafer 200 is
through hybrid bonding, wherein dies 112 are bonded to dies 212
prior to singulation. In the hybrid bonding of wafers 100 and 200,
bond dielectric layer 140 is bonded to bond dielectric layer 240
through fusion bonding, and the metal of bond pads 142 are bonded
to the metal of bond pads 242 through metal-to-metal bonding.
Chip-to-chip or chip-to-wafer bonding proceeds similarly, except
for the method used for aligning the chips or chips and wafer.
[0067] The bonding may include a pre-bonding and an annealing.
During the pre-bonding, a small pressing force is applied to press
wafers 100 and 200 against each other. The pre-bonding may be
performed at the room temperature (for example, between about
21.degree. C. to about 25.degree. C.), although higher temperatures
may be used. After the pre-bonding, bond dielectric layers 140 and
240 are bonded to each other. The bonding strength is improved in a
subsequent annealing step, in which the bonded wafers 100 and 200
are annealed at a temperature between about 300.degree. C. and
about 400.degree. C., for example.
[0068] The annealing may be performed for a period of time between
about 1 hour and 2 hours. When temperature rises, the OH bond in
bond dielectric layer 140 and bond dielectric layer 240 break to
form strong Si--O--Si bonds, and hence wafers 100 and 200 are
bonded to each other through fusion bonds (and through Van Der
Waals force). In addition, during the annealing, the metal (such as
copper) in bond pads 142 and bond pads 242 diffuse into each other,
so that metal-to-metal bonds are also formed. Hence, the resulting
bonds between wafers 100 and 200 are hybrid bonds. After the
bonding, the bonded wafer 100 and 200 may be sawed into packages,
with each of the packages including die 112 bonded to die 212.
[0069] As shown in FIG. 5, bond pads 142 and bond pads 242 are
bonded to each other with a one-to-one correspondence. In some
embodiments, each of bond pads 142 has a corresponding bond pad 242
to bond to, and each of bond pads 242 has a corresponding bond pad
142 to bond to. Active metal pads 142A are bonded to active metal
pads 142A, and dummy metal pads 142B are bonded to dummy metal pads
142B. In some embodiments, dummy metal pads may be bonded to active
metal pads. For example, dummy metal pad 142B may be bonded to
active metal pad 242A. In some embodiments, a misalignment might
occur in the pattern or in the alignment of one wafer to the other
and a portion of one or more of bond pads 142 may slightly overhang
or underhang a corresponding one of bond pads 242.
[0070] Removing dummy metal pads 142B and 242B from over the seal
ring units 136 and 236 provides for a more reliable bonding to the
bond dielectric layers 140 and 240, thereby improving bonding yield
and creating bonds less prone to bond failure. This result is
unexpected because including dummy metal pads in this area can
provide a more uniform pattern density which would result in a more
level surface following planarization.
[0071] The embodiments discussed above apply when the die sizes are
the same such that the edges of the two dies are aligned. Similar
processes can be used to provide bonding with dies of two different
sizes. FIGS. 6 through 7c illustrate another die 312 in accordance
with some embodiments. FIG. 6 illustrates a schematic top view of
wafer 300 in accordance with some embodiments. Wafer 300 includes
dies 312 and the adjoining scribe lines 314 and 316 similar to
scribe lines 114 and 116 of FIG. 1.
[0072] FIG. 7a illustrates a schematic perspective view of die 312.
Die 312 in FIG. 7a may be singulated from wafer 300 or may still be
intact with wafer 300. Seal ring unit 336 is disposed at a
periphery of die 312 and may include one or more distinct seal
rings (described in greater detail below with respect to FIGS. 7b
and 7c). In some embodiments, die 312 comprises an array of bond
pads 342 set over and around a device area 318 of die 312. In some
embodiments, the device area 318 may include the entire area of die
312 within seal ring unit 336. In other embodiments, the device
area 318 may include a portion of the area of die 312 within seal
ring unit 336, such as illustrated in FIG. 7a. In some embodiments,
the device area 318 may include all the available bond pads 342 on
the die or a subset of the available bond pads 342. Arrangements of
bond pads 342 may be made in a pattern other than an array pattern.
Bond pads 342 may be sized similarly or differently, depending on
the design of the bond pads 342 on die 312.
[0073] Die 312 may be a similar device as die 112, in some
embodiments, and may have similar dimensions thereto, including
thicknesses of layers and so forth. In some embodiments, die 312
may include a logic device or memory device such as memory cells
including, and not limited to, Static Random Access Memory (SRAM)
cells, Dynamic Random Access Memory (DRAM) Cells, Magneto-Resistive
Random Access Memory (MRAM) cells, or the like. Die 312 may include
other types of devices.
[0074] FIG. 7b illustrates a cross-sectional view of die 312. The
cross-section of FIG. 7b is a portion of a cross-section taken
along the line A-A of FIG. 7c, however the details may be varied
from one view to another for the purposes of discussion. Die 312
includes a substrate 322, similar to substrate 122 and device area,
similar to device area 118.
[0075] An interconnect structure 326 may be formed over substrate
322. Interconnect structure 326 may include insulating layers 328
and conductive features (e.g., metal lines 327, vias 329, and
optional metal pads 331). Interconnect structure 326 may connect
various active and/or passive devices in device area 318 of
substrate 322 to form functional circuits. Interconnect structure
326 may be formed using materials and processes similar to those
discussed above with respect to interconnect structure 126 of FIG.
2b, which are not repeated.
[0076] Interconnect structure 326 also includes a seal ring
structure 332A, similar to seal ring structure 132A of FIG. 2b.
Other seal ring structures, such as seal ring structure 334A may
also be formed in interconnect structure 326. Seal ring structure
332A and seal ring structure 334A may be formed in a similar manner
as the other layers of the interconnect structure 326.
[0077] A passivation layer 338 may be formed over the interconnect
structure 326 and patterned to form openings therein, exposing a
top metal layer of the interconnect structure 326 (or optional
metal pad 331) and exposing a top metal layer of the seal ring
structure 332A and a top metal layer of the seal ring structure
334A. Passivation layer 338 may be formed using processes and
materials such as those discussed above with respect to passivation
layer 138, which are not repeated.
[0078] Seal ring structure 332A may be extended through and over
the passivation layer 338. A via 332B may be formed in the
passivation layer 338 and an overlying seal ring metal 332C may be
formed over the passivation layer 338. The resulting seal ring 332
may therefore comprise seal ring structure 332A in interconnect
structure 326, seal via 332B through passivation layer 338, and
seal ring metal 332C. In some embodiments, additional seal rings
may be included. In embodiments having additional seal rings, such
as seal ring 334, such seal rings may similarly comprise the seal
ring structure, such as seal ring structure 334A in the
interconnect structure 326, a via, such as via 334B through
passivation layer 338, and a seal ring metal, such as seal ring
metal 334C. Seal ring unit 336 may comprise all of the seal rings
surrounding the periphery of the die (e.g., seal ring 332, seal
ring 334, and so forth). Seal ring metal 332C and seal ring metal
334C may form a continuous loop around the periphery of the die in
a top down view.
[0079] Seal ring via 332B and seal ring via 334B may be formed
using processes and materials such as those discussed above with
respect to seal ring via 132B and seal ring via 134B, which are not
repeated. Similarly, seal ring metal 332C and seal ring metal 334C
may be formed using processes and materials such as those discussed
above with respect to seal ring metal 132C and seal ring metal
134C, which are not repeated.
[0080] Crack stoppers 330 may be formed around the die. Crack
stoppers 430 may be formed using processes and materials such as
described above with respect to crack stoppers 130 which are not
repeated.
[0081] A bond dielectric layer 340 may be formed over the
passivation layer 338 and seal ring unit 336. Bond dielectric layer
340 may be formed using processes and materials similar to those
discussed above with respect to bond dielectric layer 140, which
are not repeated.
[0082] Bond pads 342 are formed in bond dielectric layer 340, and
may be electrically coupled to device area 318 through metal lines
and vias, including bond pad vias 344. Bond pads 342 and bond pad
vias 344 may be formed using processes and materials such as those
discussed above with respect to bond pads 142 and bond pad vias
144, which are not repeated. Bond pads 342 may include a plurality
of active metal pads 342A and a plurality of dummy metal pads 342B,
similar to the active metal pads 142A and dummy metal pads 142B of
FIG. 2b.
[0083] Still referring to FIG. 7b, the dummy metal pads 342B can be
removed from the design pattern where the seal ring from the die to
be bonded will interface with die 312. Keep out zone 350
illustrates an area of the bond dielectric layer 340 which has a
surface comprising a continuous dielectric interface layer which is
free from bond pads 342. As illustrated in FIG. 7b, dummy metal
pads 342B may be included over the seal ring unit 336 as part of
the substantially uniform pattern of bond pads 342. In other
embodiments, the dummy metal pads 342B are optional and may be
omitted from over the seal ring unit 336. Other dummy metal pads
342B may be interspersed throughout the design pattern, depending
on whether a bond pad via 344 is used to couple the bond pad 342 to
a metal feature in the interconnect layer 326. In some embodiments,
such as illustrated in FIG. 7b, some of the bond pads 34 between
keep out zone 350 and the seal ring unit 336 may be active metal
pads 342A and may be used for bonding to other devices, or for
forming connectors thereon. In other embodiments not specifically
illustrated, all bond pads 342 between the keep out zone 350 and
seal ring unit 336 may be dummy metal pads 342B.
[0084] An area of the die 312 will interface with a keep out zone
of another die which will be bonded to die 412. Removing bond pads
342 in this area which will bond with the other die's keep out zone
produces keep out zone 350. Keep out zone 350 may include a portion
of bond dielectric layer 340 in an inner part of die 312, such as
areas over a portion of metal lines 327, vias 329, or optional
metal pads 331 of interconnect structure 326. Keep out zone 350 may
also include a portion of bond dielectric layer 340 over seal ring
unit 336 (see, e.g., FIG. 7c). A pattern design for bond pads 342
may initially include bond pads in keep out zone 350. The pattern
design may then be altered before manufacturing to remove bond pads
342 from the design where the keep out zone 350 is located on die
312. For example, as illustrated in FIG. 7b, keep out zone 350
corresponds in part to the location of where a keep out zone for
another die will be bonded. The location of keep out zone 150 is
thus based on where a second die will be bonded to die 112. When
the second die has smaller footprint dimensions than die 312, the
keep out zone 350 will be located at least in part at an inner
portion of bond dielectric layer 340. In some embodiments, one or
more edges of the two dies may be aligned so that part of the keep
out zone 350 is over seal ring unit 336 and part of keep out zone
350 is over an interior part of die 312. In some embodiments, the
bond pad vias 344 which correspond to the bond pads 342 which are
removed, may also be removed from the design, while in other
embodiments, some may remain in the design. Some embodiments may
have a combination where some of the bond pad vias 344 remain and
some are removed, such as illustrated in FIG. 7b.
[0085] Referring now to FIG. 7c, FIG. 7c illustrates a top view of
a corner portion of die 312. Although seal ring unit 336 and crack
stoppers 330 would not be visible in the top view, they have been
illustrated for context and provided with dashed outside edges. A
keep out zone 350 provides an area over die 312 which is free from
bond pads 342. The keep out zone 350 may continue along an edge of
die 312 over a portion of the seal ring unit 336, in some
embodiments. In other embodiments, the keep out zone 350 may be
completely within the seal ring unit 336 outline, such that the
keep out zone 350 does not overlap any of the seal ring unit 336.
The top surface of the seal ring unit 336 is below the surface of
the bond dielectric layer 340. As such, the keep out zone 350
provides a dielectric bond area continuously extending from one
edge of the keep out zone to the other edges of the keep out zone
for fusion bonding to the keep out zone of another die while being
unencumbered by any metal features. When the keep out zone 350 is
aligned to a keep out zone on another die, and bonded thereto, the
bond yield rate is improved. The keep out zone 350 provides a
dielectric bond area for fusion bonding to another die, such as die
412 (discussed below with respect to FIGS. 10a through 10c).
[0086] FIGS. 8 through 10c illustrate another die 412 in accordance
with some embodiments. FIG. 8 illustrates a schematic top view of
wafer 400 in accordance with some embodiments. Wafer 400 includes
dies 412 and the adjoining scribe lines 414 and 416 similar to
scribe lines 414 and 416 of FIG. 1. The foot print of die 412 may
be designed to have a smaller area than the foot print of die 312.
In some embodiments, die 412 may have a dimension in common with
the foot print of die 312 (e.g., having the same width, but
different lengths, or vice-versa), while in other embodiments, die
412 may have a smaller width and length than that of die 412.
[0087] FIG. 9a illustrates a schematic perspective view of die 412.
Die 412 in FIG. 9a may be singulated from wafer 400 or may still be
intact with wafer 400. Seal ring unit 436 (shown in phantom) is
disposed at a periphery of die 412 under the surface of die 412 and
may include one or more distinct seal rings (described in greater
detail below with respect to FIGS. 9b and 9c). In some embodiments,
die 412 comprises an array of bond pads 442 set over and around a
device area 418 of die 412. In some embodiments, the device area
418 may include the entire area of die 412 within seal ring unit
436. In other embodiments, the device area 418 may include a
portion of the area of die 412 within seal ring unit 436, such as
illustrated in FIG. 9a. In some embodiments, the device area 418
may include all the available bond pads 442 on the die or a subset
of the available bond pads 442. Arrangements of bond pads 442 may
be made in a pattern other than an array pattern. Bond pads 442 may
be sized similarly or differently, depending on the design of the
bond pads 442 on die 412.
[0088] Die 412 may be a similar device as die 112, in some
embodiments, and may have similar dimensions thereto, including
thicknesses of the layers and so forth. Die 412 has a smaller
footprint than die 312 in at least one lateral dimension, such
that, when bonded to die 312, die 312 overlaps die 412 by one or
more edges. Die 412 may have first width, e.g., in the X direction
of w3, which may be between about 2000 .mu.m and about 26000 .mu.m,
such as about 10000 .mu.m. Die 412 may have second width (or
length), e.g., in the Y direction of w4, which may be between about
2000 .mu.m and about 33000 .mu.m, such as about 10000 .mu.m. Other
dimensions for die 412 may be used. In some embodiments, die 412
may include a logic device or memory device such as memory cells
including, and not limited to, Static Random Access Memory (SRAM)
cells, Dynamic Random Access Memory (DRAM) Cells, Magneto-Resistive
Random Access Memory (MRAM) cells, or the like. Die 412 may include
other types of devices.
[0089] FIG. 9b illustrates a cross-sectional view of die 412. The
cross-section of FIG. 9b is a portion of a cross-section taken
along the line A-A of FIG. 9c, however the details may be varied
from one view to another for the purposes of discussion. Die 412
includes a substrate 422, similar to substrate 122 and device area,
similar to device area 118
[0090] An interconnect structure 426 may be formed over substrate
422. Interconnect structure 426 may include insulating layers 428
and conductive features (e.g., metal lines 427, vias 429, and
optional metal pads 431). Interconnect structure 426 may connect
various active and/or passive devices in device area 418 of
substrate 422 to form functional circuits. Interconnect structure
426 may be formed using materials and processes similar to those
discussed above with respect to interconnect structure 126 of FIG.
2b, which are not repeated.
[0091] Interconnect structure 426 also includes a seal ring
structure 432A, similar to seal ring structure 132A of FIG. 2b.
Other seal ring structures, such as seal ring structure 434A may
also be formed in interconnect structure 426. Seal ring structure
432A and seal ring structure 434A may be formed in a similar manner
as the other layers of the interconnect structure 426.
[0092] A passivation layer 438 may be formed over the interconnect
structure 426 and patterned to form openings therein, exposing a
top metal layer of the interconnect structure 426 and exposing a
top metal layer of the seal ring structure 432A and a top metal
layer of the seal ring structure 434A. Passivation layer 438 may be
formed using processes and materials such as those discussed above
with respect to passivation layer 138, which are not repeated.
[0093] Seal ring structure 432A may be extended through and over
the passivation layer 438. A via 432B may be formed in the
passivation layer 438 and an overlying seal ring metal 432C may be
formed over the passivation layer 438. The resulting seal ring 432
may therefore comprise seal ring structure 432A in interconnect
structure 426, seal ring via 432B through passivation layer 438,
and seal ring metal 432C. In some embodiments, additional seal
rings may be included, such as seal ring 434, which has similar
layers as seal ring 432. Seal ring unit 436 may comprise all of the
seal rings surrounding the periphery of the die (e.g., seal ring
432, seal ring 434, and so forth). Seal ring metal 432C and seal
ring metal 434C may form a continuous loop around the periphery of
the die in a top down view.
[0094] Seal ring via 432B and seal ring via 434B may be formed
using processes and materials such as those discussed above with
respect to seal ring via 132B and seal ring via 134B, which are not
repeated. Similarly, seal ring metal 432C and seal ring metal 334C
may be formed using processes and materials such as those discussed
above with respect to seal ring metal 132C and seal ring metal
134C, which are not repeated.
[0095] Crack stoppers 430 may be formed around the die. Crack
stoppers 430 may be formed using processes and materials such as
described above with respect to crack stoppers 130 which are not
repeated.
[0096] A bond dielectric layer 440 may be formed over the
passivation layer 438 and seal ring unit 436. Bond dielectric layer
440 may be formed using processes and materials similar to those
discussed above with respect to bond dielectric layer 140, which
are not repeated.
[0097] Bond pads 442 are formed in bond dielectric layer 440, and
may be electrically coupled to device area 418 through metal lines
and vias, including bond pad vias 444. Bond pads 442 and bond pad
vias 444 may be formed using processes and materials such as those
discussed above with respect to bond pads 142 and bond pad vias
144, which are not repeated. Bond pads 442 may include a plurality
of active metal pads 442A and a plurality of dummy metal pads 442B,
similar to the active metal pads 142A and dummy metal pads 142B of
FIG. 2b.
[0098] Still referring to FIG. 9b, the dummy metal pads 442B can be
removed from the design pattern in bond dielectric layer 440 where
the seal ring unit 436 of die 412 is located. Bond dielectric layer
440 will fusion bond with bond dielectric layer 340 of die 312 in
this area. Keep out zone 450 illustrates the area of the bond
dielectric layer 440 which is free from bond pads 442. Providing a
design of a die, such as die 412 to include keep out zone 450 may
be done in a manner similar to that described above with respect to
FIG. 2b, which is not repeated. Other dummy metal pads 442B may be
interspersed throughout the design pattern, depending on whether a
bond pad via 444 is used to couple the bond pad 442 to a metal
feature in interconnect structure 426.
[0099] Referring now to FIG. 9c, FIG. 9c illustrates a top view of
a corner portion of die 412. Although the seal ring unit 436 and
crack stoppers 430 would not be visible in the top view, they have
been illustrated for context and provided with dashed outside
edges. The seal ring unit 436 comprising seal ring 432 and seal
ring 434 is illustrated to continue around the periphery of die
412. All the bond pads 442 are contained within the seal ring unit
436. Keep out zone 450 for the seal ring unit 436 provides an area
over the seal ring unit 436 which is free from bond pads 442. Keep
out zone 450 is similar to keep out zone 150 of FIG. 2c, and
includes a continuous dielectric surface layer from one edge of
keep out zone 450 to the other edges of keep out zone 450, which is
free from bond pads 442. The top surface of the seal ring unit 436
is below the surface of the bond dielectric layer 440. As such, the
keep out zone 450 provides a dielectric bond area for fusion
bonding to another die, such as die 312.
[0100] Referring to FIG. 10a, a schematic perspective view of die
312 bonded to die 412 is shown. Die 412 has been flipped over and
bonded face-to-face with die 312. Seal ring unit 436 of die 412 is
shown in phantom and would not be visible. As seen in FIG. 10a, die
412 has the same length as die 312, but is narrower than die 312.
Die 412 has been positioned on die 312 so that two of the edges of
each die are aligned with a corresponding edge of the opposite die.
In other examples, die 412 may be positioned on die 312 so that a
third edge of each die is aligned with a corresponding edge of the
opposite die. In other examples, die 412 may be smaller in both
length and width than die 312 and may be positioned on die 312 such
that zero or one edge of each die is aligned with a corresponding
edge of the opposite die.
[0101] Referring now to FIG. 10b, FIG. 10b illustrates a
cross-section that includes die 312 bonded to die 412 to form die
package 413. Bonding can be chip-to-chip where two singulated chips
(or dies) are directly bonded together or chip-to-wafer where one
or more chips (or dies) are directly bonded together to a wafer
(e.g., wafer 300). The direct bonding may be accomplished by hybrid
bonding, which an example process is described above with respect
to FIG. 5.
[0102] As shown in FIG. 10b, bond pads 342 and bond pads 442 are
bonded to each other with a one-to-one correspondence. In some
embodiments, each of bond pads 342 has a corresponding bond pad 342
to bond to, and each of bond pads 442 has a corresponding metal pad
342 to bond to. In some embodiments, bond pads 442 which are
outside the footprint of die 412 (exposed from die 412) may remain
unbonded. In some embodiments, bond pads 442 outside the footprint
of die 412 may be bonded to another die (not shown) using similar
processes and materials as the bonding to die 412. Active metal
pads 342A are bonded to active metal pads 442A, and dummy metal
pads 342B are bonded to dummy metal pads 442B. In some embodiments,
dummy metal pads of one die or the other may be bonded to active
metal pads of the opposite die. For example, dummy metal pad 342B
may be bonded to active metal pad 442A. In some embodiments, a
slight misalignment might occur in the pattern or in the alignment
of one wafer to the other and a portion of one or more of bond pads
342 may slightly overhang or underhang a corresponding one of bond
pads 442.
[0103] FIG. 10c illustrates a top view of a corner portion of die
312 bonded to die 412. As shown in FIG. 10c, the keep out zones 350
and 450 are aligned to provide a direct fusion bonding of the bond
dielectric layer 340 to the bond dielectric layer 440 in that area.
As shown in FIG. 10c, in some embodiments, an edge of die 312 may
be aligned to an edge of die 412. Die 412 is flipped over and
bonded to die 312. The seal ring unit 436, crack stoppers 430 and
bond pads 442 would not be visible, but have been illustrated for
context.
[0104] Referring to FIG. 11, FIG. 11 illustrates another embodiment
where a die 312 is bonded to die 412 having a smaller footprint
(see FIG. 9a and its accompanying description), similar to the view
of FIG. 10c. As shown in FIG. 11, two or more adjacent edges of die
412 are not aligned to corresponding adjacent edges of die 312. In
some embodiments, some edges may be aligned while in other
embodiments, none of the edges are aligned.
[0105] FIGS. 12 through 13c illustrate another embodiment for a
seal ring design which includes bond pads over the seal ring unit,
but couples the bond pads over the seal ring unit to the seal ring.
Referring to FIG. 12, FIG. 12 illustrates a wafer 500 having dies
512 disposed thereon. Wafer 500 and dies 512 are substantially
similar to the wafer 100 and dies 112, except as described below.
Accordingly, the details for dies 512 are omitted for the sake of
brevity. Referring to FIG. 13a, die 512 contains similar features
and structures as dies 112 including a seal ring unit 536, device
area 518, and bond pads 542. In addition, die 512 includes
additional ring-like bond pads 552. Ring-like bond pads 552 include
a ring-like structure disposed over and coupled to each of the seal
ring unit 536.
[0106] Referring to FIG. 13b, a cross-section of die 512 is
illustrated in accordance with some embodiments. Die 512 contains
similar features and structures as die 112, including substrate
522, interconnect structure 526, passivation layer 538, bond
dielectric layer 540, and a seal ring unit 536 which may include
one or more seal ring structures 532 and 534, each including a seal
ring 532A (and 534A) in the interconnect structure 526, a seal ring
via 532B (and 534B), and seal ring metal 532C (and 534C). Die 512
may also include crack stoppers 530. Die 512 also includes bond pad
542, including active metal pads 542A coupled to a metal feature in
the interconnect structure 526 by bond pad vias 544 and dummy metal
pads 542B which are not coupled to the interconnect structure 526.
In addition to these common features, as noted above, die 512
includes one or more ring-like bond pads 552 coupled to each of the
seal ring structures in seal ring unit 536. The ring-like bond pads
552 may be formed in a continuous ring around the periphery of die
512 disposed over the seal ring structures. The ring-like bond pads
552 are coupled to the seal ring by one or more bond pad vias 554.
In some embodiments, bond pad vias 554 may be disposed at regular
intervals around the ring-like bond pads 552. In other embodiments,
the one or more bond pad vias 554 may also be ring-like, and are
formed in a trench all around the periphery of die 512. An inactive
zone 551 is located at the periphery of die 512. Inactive zone 551
is similar to keep out zone 150 of FIG. 2b, except that ring-like
bond pads 552, bond pad vias 554, and optional dummy metal pads
542/542B may be included. Although ring-like bond pads 552 are
inactive, they are coupled to the underlying seal ring unit 536. In
some embodiments, other dummy metal pads 542/542B which are not
coupled to any underlying features may also be included in inactive
zone 551.
[0107] In some embodiments, bond pad vias 554 may be formed in a
manner similar to the bond pad vias 544, which is not repeated. In
other embodiments, bond pad vias 554 may be formed in a separate
processing step than the forming of the bond pad vias 544. For
example, a first resist layer can be patterned to expose portions
of dielectric bond layer 540 corresponding to bond pad vias 554.
Openings in dielectric bond layer 540 may then be formed to expose
seal ring unit 536. A conductive material may then be deposited in
the openings to form bond pad vias 554. The process can be repeated
using a second resist layer to form bond pad vias 544. The order
for forming bond pad vias 544 and bond pad vias 554 can be
reversed. In some embodiments, the openings for each of bond pad
vias 544 and bond pad vias 554 can be separately formed, as
described above, and then the conductive material deposited
simultaneously.
[0108] Ring-like bond pad 552 may be formed in a manner similar to
the bond pads 542, which is not repeated. By forming a bond pads
over the seal ring, which are attached to the seal ring, the
bonding of die 512 to another die is improved over having dummy
bond pads alone.
[0109] Inactive zone 551 may be created in a manner similar to that
of keep out zone 150 of FIG. 2b. A pattern design for bond pads 542
may initially include bond pads in inactive zone 551. The pattern
design may then be altered to remove bond pads 542 from the design
where inactive zone 551 is located on die 512. For example, as
illustrated in FIG. 13b, inactive zone 551 corresponds to the
location of the seal ring unit 536 and extends into the inner part
of die 512 over the crack stoppers 530 and over a portion of a
metal line of interconnect structure 526. In other embodiments, the
inactive zone may be located in other areas of the die (see, e.g.,
FIG. 7b). The location of inactive zone 551 is based on where a
second die will be bonded to die 512. When the second die has the
same footprint dimensions, inactive zone 551 will be located at the
periphery of the die, corresponding to the area of seal ring unit
536. When the second die has a smaller footprint, inactive zone 551
will be located at least in part in an interior part of the die
512. Examples of such embodiments are described in greater detail
below with respect to FIGS. 15 and 16.
[0110] Referring now to FIG. 14, die 512 is bonded to a similarly
formed die 612, in accordance with some embodiments. Die 612 has
similar features as die 512 with corresponding elements labelled
similarly, except that the elements begin with a "6" instead of a
"5." Die 512 and die 612 may be bonded as a wafer-to-wafer,
chip-to-chip, or chip-to-wafer process. Die 512 and die 612 may be
hybrid bonded to each other, for example, using a hybrid bonding
process such as described above with respect to FIG. 5.
[0111] Referring now to FIG. 15, die 512 is bonded to another die
712, in accordance with some embodiments. Die 712 has similar
features as die 512 with corresponding elements labelled similarly,
except that the elements begin with a "7" instead of a "5." In some
embodiments, die 712 may be formed using processes consistent with
those discussed above with respect to die 312, except for the
inclusion of a keep out zone. Similar to that described above with
respect to FIG. 10b, however, die 512 is smaller than die 712 and
at least one of the edges of the dies 712 and 512 are not aligned
in top view (see, e.g., FIGS. 10c and 11). Similar to die 312
discussed above, the dummy metal pads 742B disposed over the seal
ring unit 736 may be omitted in some embodiments. Die 712 may also
include ring-like bond pads 752, similar to ring-like bond pads
552, as discussed above. Die 512 and die 712 may be hybrid bonded
to each other, for example, using a hybrid bonding process such as
described above with respect to FIG. 5. Ring-like bond pads 752 in
die 712 interfacing with inactive zone 551 of die 512 may be bonded
to the ring-like bond pads 552 of die 512.
[0112] Referring now to FIG. 16, die 512 is bonded to another die
812, in accordance with some embodiments. Die 812 has similar
features as die 512 with corresponding elements labelled similarly,
except that the elements begin with an "8" instead of a "5." Die
812 may be formed to be substantially similar to die 712, except
that instead of a keep out zone, die 812 includes inactive zone 851
including ring-like bond pads 852 (and bond pad vias 854) aligned
with the ring-like bond pads 552 as well as ring-like bond pads 852
(and bond pad vias 854) aligned with and coupled to the seal ring
structure 832 and seal ring structure 834 of seal ring unit 836.
Ring-like bond pads 852 (and bond pad vias 854) may be formed using
processes and materials similar to those discussed above with
respect to ring-like bond pads 552 (and bond pad vias 554). Die 512
and die 812 may be hybrid bonded to each other, for example, using
a hybrid bonding process such as described above with respect to
FIG. 5. One of skill will understand that the different features of
FIGS. 16 and 17 may be combined in another embodiment.
[0113] FIG. 17 illustrates a flow diagram for altering a bond pad
design to accommodate a keep out area, in accordance with some
embodiments. In step 1710, a substantially uniform bond pad layout
for a first die is created. A substantially uniform bond pad layout
can include a layout of bond pads with no more than about 10%
variation in pattern and/or bond pad sizes. At step 1720, an
interface in the first die is determined where a second die will
bond to the first die. The second die and first die will mate
according to how the bond pads in each respective die are
configured to be coupled together. Once the interface is
determined, the dummy metal bond pads around the periphery of the
first or second die can be removed from the design. In some
embodiments, where the first and second die have the same sizes,
the first die will interface with the second die across its entire
surface. In some embodiments where the first or second die is
smaller than the other, the interface between the two dies will be
smaller than the entire surface area for one of the dies.
[0114] At step 1730, the dummy metal bond pads are removed from the
layout design in the first and second dies which are directly in
line with a seal ring unit of either the first die or the second
die. In other words, the dummy metal bond pads are removed from the
layout design in the first die where the second die's seal ring
would be directly in line. Likewise, the dummy metal bond pads are
removed from the layout design in the second die which are directly
in line with the second die's seal ring. This provides that the
corresponding dummy metal bond pads in the each die are removed
from the design.
[0115] FIG. 18 illustrates a flow diagram for altering a bond pad
design to provide a ring-like dummy bond pad which is coupled to a
seal ring, in accordance with some embodiments. In step 1810, a
substantially uniform bond pad layout for a first die is created. A
substantially uniform bond pad layout can include a layout of bond
pads with no more than about 10% variation in pattern and/or bond
pad sizes. At step 1820, an interface in the first die is
determined where a second die will bond to the first die. The
second die and first die will mate according to how the bond pads
in each respective die are configured to be coupled together. In
some embodiments, where the first and second dies have the same
size, the first die will interface with the second die across its
entire surface. In some embodiments where the first or second die
is smaller than the other, the interface between the two dies will
be smaller than the entire surface area for one of the dies.
[0116] At step 1830, after the interface is determined, the dummy
metal bond pads are removed from the layout design in the first and
second dies which are directly in line with a seal ring unit of
either the first die or the second die. In other words, the dummy
metal bond pads are removed from the layout design in the first die
where the second die's seal ring would be directly in line.
Likewise, the dummy metal bond pads are removed from the layout
design in the second die which are directly in line with the second
die's seal ring. This provides that the corresponding dummy metal
bond pads in the each die are removed from the design.
[0117] At step 1840, the removed bond pads are replaced with a
ring-like bond pads which are coupled to the underlying seal ring
unit in step 1850. The coupling can be done by individual bond pad
vias disposed along the ring-like bond pads in some embodiments. In
other embodiments, the coupling can be done by a ring-like bond pad
via disposed under the ring-like bond pads which is physically and
electrically coupled to both the ring-like bond pads and the seal
ring unit at the periphery of the die. In some embodiments, the
bond pad vias can be coupled to an interconnect layer of the
die.
[0118] Embodiments provide a way to increase bond yield by
providing a better hybrid bonding interface to provide fusion
bonding of oxide materials in two dies and direct metal-to-metal
bonding of metal materials in the two dies. Removing dummy bond
pads over the seal rings provides a better bonding interface for
fusion bonding oxide bonding layers. In some embodiments, after
removing the dummy bond pads from the design, a ring-like bond pad
can be used which is coupled to the seal ring or an interconnect of
the die. Embodiments include wafer-on-wafer, chip-on-chip, and
chip-on-wafer bonding where the die sizes may match or may be
different.
[0119] One embodiment is a structure including a first die. The
first die includes a first oxide bonding layer having a first
plurality of bond pads disposed therein and a first seal ring
disposed in the first oxide bonding layer, where the first oxide
bonding layer extends over the first seal ring. The structure
further includes a second die. The second die includes a second
oxide bonding layer having a second plurality of bond pads disposed
therein, where the first plurality of bond pads is bonded to the
second plurality of bond pads, where the first oxide bonding layer
is bonded to the second oxide bonding layer, and where an area
interposed between the first seal ring and the second oxide bonding
layer is free of bond pads.
[0120] Another embodiment is a method including determining an
alignment of a first die to a second die by aligning active bond
pads of the first die to corresponding active bond pads of the
second die, where a first area of the first die and a second area
of the second die are aligned with a seal ring of the second die.
All bond pads are removed in the first area of the first die and in
the second area of the second die. The first die is bonded to the
second die according to the alignment.
[0121] Another embodiment is a method including determining a first
device layout of bond pads disposed at a surface of a first device.
A second device layout of bond pads disposed at a surface of a
second device is determined, the second device having a seal ring.
An alignment which aligns a first active bond pad of the first
device to a second active bond pad of the second device is
determined, where the alignment causes the seal ring to align with
a first region of the first die. First bond pads in the first
region are removed from the first device layout of bond pads.
Second bond pads are removed from a second region of the second
device which align with the first bond pads according to the
alignment. The first active bond pad is bonded to the second active
bond. The first region is bonded to the second region.
[0122] The foregoing outlines features of several embodiments so
that those skilled in the art may better understand the aspects of
the present disclosure. Those skilled in the art should appreciate
that they may readily use the present disclosure as a basis for
designing or modifying other processes and structures for carrying
out the same purposes and/or achieving the same advantages of the
embodiments introduced herein. Those skilled in the art should also
realize that such equivalent constructions do not depart from the
spirit and scope of the present disclosure, and that they may make
various changes, substitutions, and alterations herein without
departing from the spirit and scope of the present disclosure.
* * * * *