U.S. patent application number 15/157803 was filed with the patent office on 2017-05-04 for dual silicide liner flow for enabling low contact resistance.
The applicant listed for this patent is INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to Praneet Adusumilli, Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh.
Application Number | 20170125338 15/157803 |
Document ID | / |
Family ID | 58635089 |
Filed Date | 2017-05-04 |
United States Patent
Application |
20170125338 |
Kind Code |
A1 |
Adusumilli; Praneet ; et
al. |
May 4, 2017 |
DUAL SILICIDE LINER FLOW FOR ENABLING LOW CONTACT RESISTANCE
Abstract
A method for fabricating a semiconductor device includes
depositing a sacrificial liner in self-aligned contact openings in
first and second regions. The openings are filled with a
sacrificial material. The second region is blocked with a first
mask to remove the sacrificial material from the first region. The
first mask is removed from the second region, and the sacrificial
liner is removed from the first region. A first liner is formed in
the openings of the first region, and first contacts are formed in
the first region on the first liner. The first region is blocked
with a second mask to remove the sacrificial material from the
second region. The second mask is removed from the first region,
and the sacrificial liner is removed from the second region. A
second liner is formed in the openings of the second region, and
second contacts are formed in the second region.
Inventors: |
Adusumilli; Praneet;
(Albany, NY) ; Basker; Veeraraghavan S.;
(Schenectady, NY) ; Liu; Zuoguang; (Schenectady,
NY) ; Yamashita; Tenko; (Schenectady, NY) ;
Yeh; Chun-Chen; (Clifton Park, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
Armonk |
NY |
US |
|
|
Family ID: |
58635089 |
Appl. No.: |
15/157803 |
Filed: |
May 18, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
14928908 |
Oct 30, 2015 |
|
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15157803 |
|
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 23/525 20130101;
H01L 21/76897 20130101; H01L 21/28518 20130101; H01L 21/76846
20130101; H01L 23/535 20130101; H01L 27/092 20130101; H01L 21/76895
20130101; H01L 2221/1063 20130101; H01L 21/823871 20130101; H01L
23/5329 20130101 |
International
Class: |
H01L 23/525 20060101
H01L023/525; H01L 23/532 20060101 H01L023/532; H01L 27/092 20060101
H01L027/092 |
Claims
1. A semiconductor device, comprising: a first region including
n-type field effect transistors (NFETs); a second region including
p-type field effect transistors (PFETs); a first liner formed in
the self-aligned contact openings of the NFETs; first contacts
formed in the self-aligned contact openings of the NFETs on the
first liner; a second liner formed in the self-aligned contact
openings of the PFETs; and second contacts formed in the
self-aligned contact openings of the PFETs on the second liner,
wherein the self-aligned contact openings include only one liner in
the first region and only one liner in the second region and the
first liner and the second liner include different materials.
2. The device as recited in claim 1, wherein the first liner
includes Ti.
3. The device as recited in claim 1, wherein the first liner
includes TiN
4. The device as recited in claim 1, wherein the second liner
includes Pt.
5. The device as recited in claim 1, wherein the second liner
includes Ni.
6. The device as recited in claim 1, wherein the second liner
includes a combination of Ni and Pt.
7. The device as recited in claim 1, wherein the first contacts and
the second contacts include different materials.
8. The device as recited in claim 1, wherein the first liner and
the second liner form silicides with underlying regions.
9. The device as recited in claim 1, wherein the first contacts are
self-aligned contacts.
10. The device as recited in claim 1, wherein the second contacts
are self-aligned contacts.
Description
BACKGROUND
[0001] Technical Field
[0002] The present invention relates to semiconductor processing,
and more particularly to methods and devices for a dual liner with
improved contact resistance and reduced pinch off.
[0003] Description of the Related Art
[0004] In complementary metal oxide semiconductor processing
(CMOS), n-type and p-type devices are formed together. These
devices may share processing steps at certain points in a workflow
but need to be processed separately in others. One process where
the n-type and p-type devices are processed separately includes
dual liner integration for forming liners for self-aligned contact
(SAC) formation.
[0005] A first liner for n-type field effect transistors (NFETs) is
applied over both NFETs and p-type field effect transistors
(PFETs). The first liner is then removed from the PFETs followed by
a second liner over the PFETs and the NFETs. With shrinking contact
size, the NFET gets pinched off due to the presence of both liners.
Pinched off means that the contact hole gets blocked preventing the
contact hole from being filled with contact material. This also
increases contact resistance and could result in device
failure.
SUMMARY
[0006] A method for fabricating a semiconductor device includes
depositing a sacrificial liner in self-aligned contact openings in
first and second regions, where the first region includes a first
device type and the second region includes a second device type.
The openings are filled with a sacrificial material. The second
region is blocked with a first mask to remove the sacrificial
material from the first region. The first mask is removed from the
second region, and the sacrificial liner is removed from the first
region. A first liner is formed in the openings of the first
region, and first contacts are formed in the first region on the
first liner. The first region is blocked with a second mask to
remove the sacrificial material from the second region. The second
mask is removed from the first region, and the sacrificial liner is
removed from the second region. A second liner is formed in the
openings of the second region, and second contacts are formed in
the second region.
[0007] Another method for fabricating a semiconductor device
includes patterning an interlevel dielectric layer to form
self-aligned contact openings over field effect transistors;
depositing a sacrificial liner in the self-aligned contact
openings; filling the self-aligned contact openings with a
sacrificial material; blocking a p-type field effect transistor
(PFET) region with a first mask to remove the sacrificial material
from an n-type field effect transistor (NFET) region; removing the
first mask from the PFET region and the sacrificial liner from the
NFET region; forming a first liner in the self-aligned contact
openings of the NFET region, which contacts underlying regions;
forming first contacts in the NFET region on the first liner;
blocking the NFET region with a second mask to remove the
sacrificial material from the PFET region; removing the second mask
from the NFET region and the sacrificial liner from the PFET
region; forming a second liner in the openings of the PFET region,
which contacts underlying regions; and forming second contacts in
the PFET region.
[0008] A semiconductor device includes a first region including
n-type field effect transistors (NFETs), and a second region
including p-type field effect transistors (PFETs). A first liner is
formed in the self-aligned contact openings of the NFETs, and first
contacts are formed in the self-aligned contact openings of the
NFETs on the first liner. A second liner is formed in the
self-aligned contact openings of the PFETs, and second contacts are
formed in the self-aligned contact openings of the PFETs on the
second liner. The self-aligned contact openings include only one
liner in the first region and only one liner in the second region,
and the first liner and the second liner include different
materials.
[0009] These and other features and advantages will become apparent
from the following detailed description of illustrative embodiments
thereof, which is to be read in connection with the accompanying
drawings.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0010] The disclosure will provide details in the following
description of preferred embodiments with reference to the
following figures wherein:
[0011] FIG. 1 is a cross-sectional view of a semiconductor device
having n-type field effect transistors (NFETs) and p-type field
effect transistors (PFETs) formed thereon in accordance with the
present principles;
[0012] FIG. 2 is a cross-sectional view of the semiconductor device
of FIG. 1 having self-aligned contact openings formed for NFETs and
PFETs in accordance with the present principles;
[0013] FIG. 3 is a cross-sectional view of the semiconductor device
of FIG. 2 having the self-aligned contact openings lined with a
sacrificial liner in accordance with the present principles;
[0014] FIG. 4 is a cross-sectional view of the semiconductor device
of FIG. 3 having the self-aligned contact openings filled with a
sacrificial material in accordance with the present principles;
[0015] FIG. 5 is a cross-sectional view of the semiconductor device
of FIG. 4 having a PFET region blocked with a block mask in
accordance with the present principles;
[0016] FIG. 6 is a cross-sectional view of the semiconductor device
of FIG. 5 having the sacrificial material removed from the NFET
region in accordance with the present principles;
[0017] FIG. 7 is a cross-sectional view of the semiconductor device
of FIG. 6 having a liner and a main conductor formed in the
self-aligned contact holes in the NFET region in accordance with
the present principles;
[0018] FIG. 8 is a cross-sectional view of the semiconductor device
of FIG. 7 having a top surface planarized to form contacts in the
NFET region in accordance with the present principles;
[0019] FIG. 9 is a cross-sectional view of the semiconductor device
of FIG. 8 having a PFET region blocked with a block mask and the
sacrificial material removed from the PFET region in accordance
with the present principles;
[0020] FIG. 10 is a cross-sectional view of the semiconductor
device of FIG. 9 having a liner and a main conductor formed in the
self-aligned contact holes in the PFET region in accordance with
the present principles;
[0021] FIG. 11 is a cross-sectional view of the semiconductor
device of FIG. 10 having a top surface planarized to form contacts
in the PFET region in accordance with the present principles;
and
[0022] FIG. 12 is a block/flow diagram showing methods for forming
a semiconductor device in accordance with illustrative
embodiments.
DETAILED DESCRIPTION
[0023] In accordance with the present principles, devices and
methods for forming these devices are described that provide
flexibility in integrating n-type and p-type devices. In one useful
embodiment, formation of dual epitaxial growth or dual epi is
enabled by the process flow. In one embodiment, a sacrificial
material or mask (e.g., TiN) is formed and used in combination with
a sacrificial liner, e.g., an oxide. The sacrificial material and
liner are deposited in contact openings or holes so as to not allow
metals to touch epitaxially grown materials in regions located
within the holes. The regions may include silicided junctions,
source and drain regions, trench silicide contacts, etc.
[0024] The sacrificial material is employed to remove the liner
selectively while covering a device not being processed (one of
n-type field effect transistors (NFETs) or p-type field effect
transistors (PFETs)). The sacrificial liner may be removed during
actual metal pre-clean processing. This sacrificial liner ensures
no interface mixing prior to actual silicide liner deposition. A
first FET is covered with the sacrificial material during this
process. Contacts are formed by depositing conductive material and
planarizing the conductive material. The process is repeated to
form a liner and contacts in a second FET structure. In some
embodiments, contacts are formed by depositing conductive material
and planarizing the conductive material in separate processes for
the NFETs and the PFETs. This provides the possibility of using
different contact materials for NFETs and PFETs.
[0025] It is to be understood that the present invention will be
described in terms of a given illustrative architecture; however,
other architectures, structures, substrate materials and process
features and steps may be varied within the scope of the present
invention.
[0026] It will also be understood that when an element such as a
layer, region or substrate is referred to as being "on" or "over"
another element, it can be directly on the other element or
intervening elements may also be present. In contrast, when an
element is referred to as being "directly on" or "directly over"
another element, there are no intervening elements present. It will
also be understood that when an element is referred to as being
"connected" or "coupled" to another element, it can be directly
connected or coupled to the other element or intervening elements
may be present. In contrast, when an element is referred to as
being "directly connected" or "directly coupled" to another
element, there are no intervening elements present.
[0027] The present embodiments may include a design for an
integrated circuit chip, which may be created in a graphical
computer programming language, and stored in a computer storage
medium (such as a disk, tape, physical hard drive, or virtual hard
drive such as in a storage access network). If the designer does
not fabricate chips or the photolithographic masks used to
fabricate chips, the designer may transmit the resulting design by
physical means (e.g., by providing a copy of the storage medium
storing the design) or electronically (e.g., through the Internet)
to such entities, directly or indirectly. The stored design is then
converted into the appropriate format (e.g., GDSII) for the
fabrication of photolithographic masks, which typically include
multiple copies of the chip design in question that are to be
formed on a wafer. The photolithographic masks are utilized to
define areas of the wafer (and/or the layers thereon) to be etched
or otherwise processed.
[0028] Methods as described herein may be used in the fabrication
of integrated circuit chips. The resulting integrated circuit chips
can be distributed by the fabricator in raw wafer form (that is, as
a single wafer that has multiple unpackaged chips), as a bare die,
or in a packaged form. In the latter case the chip is mounted in a
single chip package (such as a plastic carrier, with leads that are
affixed to a motherboard or other higher level carrier) or in a
multichip package (such as a ceramic carrier that has either or
both surface interconnections or buried interconnections). In any
case the chip is then integrated with other chips, discrete circuit
elements, and/or other signal processing devices as part of either
(a) an intermediate product, such as a motherboard, or (b) an end
product. The end product can be any product that includes
integrated circuit chips, ranging from toys and other low-end
applications to advanced computer products having a display, a
keyboard or other input device, and a central processor.
[0029] It should also be understood that material compounds will be
described in terms of listed elements, e.g., NiPtSi, NiSi, PtSi,
etc. These compounds include different proportions of the elements
within the compound. In addition, other elements may be included in
the compound and still function in accordance with the present
principles. The compounds with additional elements will be referred
to herein as alloys.
[0030] Reference in the specification to "one embodiment" or "an
embodiment" of the present principles, as well as other variations
thereof, means that a particular feature, structure,
characteristic, and so forth described in connection with the
embodiment is included in at least one embodiment of the present
principles. Thus, the appearances of the phrase "in one embodiment"
or "in an embodiment", as well any other variations, appearing in
various places throughout the specification are not necessarily all
referring to the same embodiment.
[0031] It is to be appreciated that the use of any of the following
"/", "and/or", and "at least one of", for example, in the cases of
"A/B", "A and/or B" and "at least one of A and B", is intended to
encompass the selection of the first listed option (A) only, or the
selection of the second listed option (B) only, or the selection of
both options (A and B). As a further example, in the cases of "A,
B, and/or C" and "at least one of A, B, and C", such phrasing is
intended to encompass the selection of the first listed option (A)
only, or the selection of the second listed option (B) only, or the
selection of the third listed option (C) only, or the selection of
the first and the second listed options (A and B) only, or the
selection of the first and third listed options (A and C) only, or
the selection of the second and third listed options (B and C)
only, or the selection of all three options (A and B and C). This
may be extended, as readily apparent by one of ordinary skill in
this and related arts, for as many items listed.
[0032] Referring now to the drawings in which like numerals
represent the same or similar elements and initially to FIG. 1, a
cross-sectional view of a semiconductor device 10 is shown in
accordance with the present principles. The device 10 includes a
substrate 16, which may include a bulk substrate 15 having a
dielectric layer 17 formed thereon, or the substrate 15, the
dielectric layer 17 and a semiconductor layer to form fins 18 may
be part of a semiconductor-on-insulator (SOI) substrate 16. The
substrate 15 may include any suitable material, and in particular,
may include Si, Ge, SiGe, SiC, III-V material, etc. The fins 18 may
include any suitable semiconductor material, and in particular may
include Si, Ge, SiGe, etc. The dielectric layer 17 may include an
oxide, although other dielectric materials may be employed.
[0033] The fins 18 form channel regions for field effect
transistors (FETs) formed thereon. The device 10 may include n-type
FETs (NFETs) formed in an NFET region 12 and p-type FETs (PFETs)
formed in a PFET region 14. Gate structures 32 are formed over the
fins 18 and may include gate conductors 20, 22. A gate dielectric
25 which may cover sidewalls of the gate conductor 22 and is placed
between the gate conductors 20, 22 and the fin 18. The gate
conductor 20 may include a work function metal, such as e.g., Pt,
Ag, etc. and the gate conductor 22 may include a main conductor,
e.g., W, etc. The gate structures 32 include spacers 24 and a cap
26, which may include silicon nitride material.
[0034] Between gates 32 in the NFET region 12, silicided junctions,
source and drain regions, or trench silicide contacts 29
(hereinafter referred to as regions 29) are formed (depending on
the design). Between gates 32 in the PFET region 14, silicided
junctions, source and drain regions, or trench silicide contacts 30
(hereinafter referred to as regions 30) are formed (depending on
the design). The regions 29 and 30 may be formed by epitaxial
growth and may be doped in-situ. The regions 29 and 30 may include
different materials, e.g., the NFET may include TiSi, while the
PFET may include PtSi, NiSi, or NiPtSi. Regions 29, 30 may have
been processed already or may be processed in later steps.
[0035] A dielectric layer 34, e.g., an interlevel dielectric (ILD),
is formed over the NFET region 12 and the PFET region 14. The
dielectric layer 34 may include an oxide, although other dielectric
materials may be employed.
[0036] Referring to FIG. 2, the dielectric layer 34 is patterned to
form openings 36 down to the regions 29 and 30. The openings 36 are
formed by a reactive ion etch process in accordance with a
lithographically formed mask (not shown).
[0037] Referring to FIG. 3, a sacrificial liner 38 is formed in the
openings 36 in both the NFET region 12 and the PFET region 14. The
sacrificial liner 38 lines the openings and exposes portions of the
regions 29, 30. The sacrificial liner 38 protects the surface
(silicide) of the regions 29, 30 from being contaminated with any
material. The sacrificial liner 38 may include an oxide
material.
[0038] Referring to FIG. 4, a sacrificial material 40 is deposited
in the openings 36 on the sacrificial liner 38 and on a top surface
of the device 10 in both the NFET region 12 and the PFET region 14.
The sacrificial material 40 is selected to be easily removed by
standard cleaning or etching processes, such as standard clean 1
(SC1). In one embodiment, the sacrificial material 40 includes TiN
although of materials may be employed.
[0039] Referring to FIG. 5, a blocking mask 42 is deposited over
the sacrificial material 40 in both the NFET region 12 and the PFET
region 14. The blocking mask 42 is then patterned (e.g., using
lithographic processing) to remove the blocking mask 42 from the
NFET region 12. The blocking mask 42 may include a dielectric
material, a resist material or any other suitable material
configured to withstand processing in the NFET region 12.
[0040] Referring to FIG. 6, the exposed NFET region 12 is subjected
to an etch process, such as a SC1 process or a different etch
process to remove the sacrificial material 40. Once the sacrificial
material 40 is removed normal NFET processing may take place while
the PFET region 14 is blocked. The NFET region 12 may be processed
at this point by performing NFET epitaxial deposition and/or
silicide formation. Growth/deposition of trench epitaxial material
or deposition of NFET silicide metal or both may occur or other
processing may be performed depending on the design.
[0041] Referring to FIG. 7, the blocking mask 42 is selectively
removed from the PFET region 14. A metal preclean process is
performed, which removes sacrificial liner 38 from the NFET region
12. The preclean process may include, e.g., a gas cluster ion beam
(GCIB) process or SiCoNi.TM. etch process. After removing the
sacrificial liner 38 from the NFET region 12, a liner silicide 44
is formed in the openings 36 (FIG. 3) and over the sacrificial
material 40 in the PFET region 14. The liner silicide 44 may
include Ti, TiN, or other materials suitable for formation of a low
contact resistance connection with regions 29. The silicide liner
44 is followed by a main conductor deposition, which deposits a
conductive material 46 over the silicide liner 44. The conductive
material 46 may include W, although other conductive materials may
be employed.
[0042] Referring to FIG. 8, a planarization process is performed to
reduce a top surface down to the ILD 34. The planarization process
may include a recess etch or a chemical mechanical polish (CMP).
The planarization process forms contacts 50 (e.g., self-aligned
contacts (SAC)) for the NFETs in the NFET region 12.
[0043] Referring to FIG. 9, a blocking mask 52 is deposited over
the device 10 in both the NFET region 12 and the PFET region 14.
The blocking mask 52 is then patterned (e.g., using lithographic
processing) to remove the blocking mask 52 from the PFET region 14.
The blocking mask 52 may include a dielectric material, a resist
material or any other suitable material configured to withstand
processing in the PFET region 14.
[0044] The exposed PFET region 14 is subjected to an etch process,
such as a SC1 process or a different etch process to remove the
sacrificial material 40 from openings 36. Once the sacrificial
material 40 is removed normal PFET processing may take place while
the NFET region 12 is blocked. The PFET region 14 may be processed
at this point by performing PFET epitaxial deposition and/or
silicide formation. Growth/deposition of trench epitaxial material
or deposition of PFET silicide metal or both may occur or other
processing may be performed depending on the design.
[0045] Referring to FIG. 10, the blocking mask 52 is selectively
removed from the NFET region 12. A metal preclean process is
performed, which removes sacrificial liner 38 from the PFET region
14. The preclean process may include, e.g., a gas cluster ion beam
(GCIB) process or SiCoNi.TM. etch process. After removing the
sacrificial liner 38 from the PFET region 14, a liner material 54
is formed in the openings 36 (FIG. 3) and over the contacts 50 in
the NFET region 12. The liner material 44 may include Ni, NiPt, Pt,
or other materials suitable for formation of a low contact
resistance connection with regions 30. The liner material 54 is
followed by a main conductor deposition, which deposits a
conductive material 56 over the liner material 54. The conductive
material 56 may include W, although other conductive materials may
be employed. In one embodiment, the materials 46 and 56 may be the
same material (e.g., W). In other embodiments, the materials 46 and
56 may include different materials (e.g., Ti, W, TiC, Al, Ag, Pt,
etc.).
[0046] Referring to FIG. 11, a planarization process is performed
to reduce a top surface down to the ILD 34. The planarization
process may include a recess etch or a chemical mechanical polish
(CMP). The planarization process forms contacts 60 (e.g.,
self-aligned contacts (SAC)) for the PFETs in the PFET region
14.
[0047] The structure provided in FIG. 11 includes dual liner
materials 44, 54 formed separately for NFETs and PFETs. Since the
liners 44 and 54 are formed separately, they can be thinner and
prevent pinch off for the formation of the main conductor (e.g.,
conductors 46, 56). With shrinking contact size, thin liners on
each type of contact 50, 60 ensures more room for the main
conductor (lower resistance). In addition, only one liner is
employed in any trench, hence preventing buildup of materials that
could result in pinch off, lower contact resistance and possibly
device failure.
[0048] Referring to FIG. 12, methods for fabricating a
semiconductor device are shown in accordance with the present
principles. In some alternative implementations, the functions
noted in the blocks may occur out of the order noted in the
figures. For example, two blocks shown in succession may, in fact,
be executed substantially concurrently, or the blocks may sometimes
be executed in the reverse order, depending upon the functionality
involved. It will also be noted that each block of the block
diagrams and/or flowchart illustration, and combinations of blocks
in the block diagrams and/or flowchart illustration, can be
implemented by special purpose hardware-based systems that perform
the specified functions or acts or carry out combinations of
special purpose hardware and computer instructions.
[0049] In block 102, self-aligned contact openings are formed by
patterning an interlevel dielectric layer. In block 104, a
sacrificial liner is deposited in self-aligned contact openings in
first and second regions, where the first region includes a first
device type (e.g., NFET) and the second region includes a second
device type (e.g., PFET). It should be understood that while the
present disclosure describes processing the NFET region first;
however, the processing order may be reversed so that the PFET
region is processed first. Underlying regions in the self-aligned
contact openings remain uncontaminated by employing the sacrificial
liner for protection. The sacrificial liner may include an
oxide.
[0050] In block 106, the self-aligned contact openings are filled
with a sacrificial material, e.g., TiN. In block 108, the second
region is blocked with a first mask to remove the sacrificial
material from the first region. In block 110, the first mask is
removed from the second region, and the sacrificial liner is
removed from the first region.
[0051] In block 112, a first liner is formed in the openings of the
first region. If the first liner is employed for NFETs, the first
liner may include Ti or TiN. In block 114, first contacts are
formed in the first region on the first liner. In block 116, the
first region is blocked with a second mask to remove the
sacrificial material from the second region. In block 118, the
second mask is removed from the first region, and the sacrificial
liner is removed from the second region. In block 120, a second
liner is formed in the openings of the second region. If the second
liner is employed for PFETs, the second liner may include Pt, Ni or
a combination thereof. In block 122, second contacts are formed in
the second region. The first contacts and the second contacts may
include the same or different materials. The self-aligned contact
openings include only one liner in the first region and only one
liner in the second region, and the first liner and the second
liner include different materials. In one embodiment, the first
liner and the second liner form silicides with underlying regions.
In block 124, processing continues to complete the device.
[0052] Having described preferred embodiments for a dual silicide
liner flow for enabling low contact resistance (which are intended
to be illustrative and not limiting), it is noted that
modifications and variations can be made by persons skilled in the
art in light of the above teachings. It is therefore to be
understood that changes may be made in the particular embodiments
disclosed which are within the scope of the invention as outlined
by the appended claims. Having thus described aspects of the
invention, with the details and particularity required by the
patent laws, what is claimed and desired protected by Letters
Patent is set forth in the appended claims.
* * * * *