| Patent | Date |
|---|
Punch through stopper in bulk finFET device
Grant 11,404,560 - Basker , et al. August 2, 2 | 2022-08-02 |
Forming replacement low-k spacer in tight pitch fin field effect transistors
Grant 11,374,111 - Cai , et al. June 28, 2 | 2022-06-28 |
Vertical field effect transistor with bottom source-drain region
Grant 11,355,633 - Reznicek , et al. June 7, 2 | 2022-06-07 |
Nanosheet semiconductor devices with sigma shaped inner spacer
Grant 11,348,999 - Reznicek , et al. May 31, 2 | 2022-05-31 |
Scalable vertical transistor bottom source-drain epitaxy
Grant 11,335,804 - Yeh , et al. May 17, 2 | 2022-05-17 |
Vertical Transistor Including Symmetrical Source/drain Extension Junctions
App 20220130980 - Yeh; Chun-Chen ; et al. | 2022-04-28 |
Aspect ratio trapping in channel last process
Grant 11,309,408 - Leobandung , et al. April 19, 2 | 2022-04-19 |
Vertical Field Effect Transistor With Self-aligned Source And Drain Top Junction
App 20220059677 - Xie; Ruilong ; et al. | 2022-02-24 |
Stacked Field Effect Transistor With Wrap-around Contacts
App 20220052047 - Xie; Ruilong ; et al. | 2022-02-17 |
Vertical transistors having improved control of top source or drain junctions
Grant 11,239,342 - Cheng , et al. February 1, 2 | 2022-02-01 |
Vertical transistor including symmetrical source/drain extension junctions
Grant 11,239,343 - Yeh , et al. February 1, 2 | 2022-02-01 |
Stacked field effect transistor with wrap-around contacts
Grant 11,201,153 - Xie , et al. December 14, 2 | 2021-12-14 |
Reduced Source/drain Coupling For Cfet
App 20210366782 - Xie; Ruilong ; et al. | 2021-11-25 |
Nanosheet transistor having partially self-limiting bottom isolation extending into the substrate and under the source/drain and gate regions
Grant 11,183,558 - Yeh , et al. November 23, 2 | 2021-11-23 |
Vertical field effect transistor with self-aligned source and drain top junction
Grant 11,177,370 - Xie , et al. November 16, 2 | 2021-11-16 |
High thermal budget compatible punch through stop integration using doped glass
Grant 11,171,204 - Cheng , et al. November 9, 2 | 2021-11-09 |
Two-stage top source drain epitaxy formation for vertical field effect transistors enabling gate last formation
Grant 11,164,787 - Reznicek , et al. November 2, 2 | 2021-11-02 |
Reduced source/drain coupling for CFET
Grant 11,164,793 - Xie , et al. November 2, 2 | 2021-11-02 |
Nanosheet device integrated with a FINFET transistor
Grant 11,158,636 - Yeh , et al. October 26, 2 | 2021-10-26 |
High thermal budget compatible punch through stop integration using doped glass
Grant 11,152,460 - Cheng , et al. October 19, 2 | 2021-10-19 |
Reduced Source/drain Coupling For Cfet
App 20210296184 - Xie; Ruilong ; et al. | 2021-09-23 |
Nanosheet Semiconductor Devices With Sigma Shaped Inner Spacer
App 20210288141 - Reznicek; Alexander ; et al. | 2021-09-16 |
Vertical Field Effect Transistor With Self-aligned Source And Drain Top Junction
App 20210273077 - Xie; Ruilong ; et al. | 2021-09-02 |
Stacked Field Effect Transistor With Wrap-around Contacts
App 20210265348 - Xie; Ruilong ; et al. | 2021-08-26 |
Vertical Transistor Including Symmetrical Source/drain Extension Junctions
App 20210265488 - Yeh; Chun-Chen ; et al. | 2021-08-26 |
Nanosheet Transistor Having Partially Self-limiting Bottom Isolation Extending Into The Substrate And Under The Source/drain And Gate Regions
App 20210249506 - Yeh; Chun-Chen ; et al. | 2021-08-12 |
Nanosheet Device Integrated With A Finfet Transistor
App 20210233910 - Yeh; Chun-Chen ; et al. | 2021-07-29 |
Stacked field effect transistors with reduced coupling effect
Grant 11,069,684 - Xie , et al. July 20, 2 | 2021-07-20 |
Dielectric isolation for nanosheet devices
Grant 11,062,937 - Cheng , et al. July 13, 2 | 2021-07-13 |
Scalable Vertical Transistor Bottom Source-drain Epitaxy
App 20210210631 - Yeh; Chun-Chen ; et al. | 2021-07-08 |
Vertical Field Effect Transistor With Bottom Source-drain Region
App 20210210632 - Reznicek; Alexander ; et al. | 2021-07-08 |
Two-dimensional (2D) self-aligned contact (or via) to enable further device scaling
Grant 11,056,386 - Wang , et al. July 6, 2 | 2021-07-06 |
Circuit for CMOS based resistive processing unit
Grant 11,055,610 - Li , et al. July 6, 2 | 2021-07-06 |
Nanosheet transistor with dual inner airgap spacers
Grant 11,056,570 - Xie , et al. July 6, 2 | 2021-07-06 |
Circuit for CMOS based resistive processing unit
Grant 11,055,611 - Li , et al. July 6, 2 | 2021-07-06 |
Two-stage Top Source Drain Epitaxy Formation For Vertical Field Effect Transistors Enabling Gate Last Formation
App 20210193527 - Reznicek; Alexander ; et al. | 2021-06-24 |
Composite spacer enabling uniform doping in recessed fin devices
Grant 11,038,041 - Basker , et al. June 15, 2 | 2021-06-15 |
Vertical field effect transistor with reduced parasitic capacitance
Grant 11,018,240 - Cheng , et al. May 25, 2 | 2021-05-25 |
Asymmetric gate edge spacing for SRAM structures
Grant 11,011,528 - Reznicek , et al. May 18, 2 | 2021-05-18 |
Mechanically stable complementary field effect transistors
Grant 10,998,233 - Xie , et al. May 4, 2 | 2021-05-04 |
Transistors With Uniform Source/drain Epitaxy
App 20210119051 - Cheng; Kangguo ; et al. | 2021-04-22 |
Electrical isolation for nanosheet transistor devices
Grant 10,957,761 - Yeh , et al. March 23, 2 | 2021-03-23 |
Formation Failure Resilient Neuromorphic Device
App 20210064974 - Kim; Youngseok ; et al. | 2021-03-04 |
Dual silicide liner flow for enabling low contact resistance
Grant 10,916,471 - Adusumilli , et al. February 9, 2 | 2021-02-09 |
Transistors with uniform source/drain epitaxy
Grant 10,903,365 - Cheng , et al. January 26, 2 | 2021-01-26 |
Compact vertical injection punch through floating gate analog memory and a manufacture thereof
Grant 10,896,979 - Leobandung , et al. January 19, 2 | 2021-01-19 |
Two-dimensional (2d) Self-aligned Contact (or Via) To Enable Further Device Scaling
App 20200411376 - Wang; Junli ; et al. | 2020-12-31 |
Transistors With Uniform Source/drain Epitaxy
App 20200403099 - Cheng; Kangguo ; et al. | 2020-12-24 |
Composite spacer enabling uniform doping in recessed fin devices
Grant 10,854,733 - Basker , et al. December 1, 2 | 2020-12-01 |
Nanosheet transistor having improved bottom isolation
Grant 10,840,329 - Xie , et al. November 17, 2 | 2020-11-17 |
Nanosheet Transistor Having Improved Bottom Isolation
App 20200357884 - Xie; Ruilong ; et al. | 2020-11-12 |
Asymmetric Gate Edge Spacing For Sram Structures
App 20200357805 - Reznicek; Alexander ; et al. | 2020-11-12 |
Confined source drain epitaxy to reduce shorts in CMOS integrated circuits
Grant 10,833,198 - Xie , et al. November 10, 2 | 2020-11-10 |
Vertical field effect transistor with top and bottom airgap spacers
Grant 10,833,155 - Yeh , et al. November 10, 2 | 2020-11-10 |
Nanosheet transistor with optimized junction and cladding detectivity control
Grant 10,818,776 - Cheng , et al. October 27, 2 | 2020-10-27 |
Contact formation through low-tempearature epitaxial deposition in semiconductor devices
Grant 10,804,270 - Gluschenkov , et al. October 13, 2 | 2020-10-13 |
Fin structures with bottom dielectric isolation
Grant 10,804,136 - Cheng , et al. October 13, 2 | 2020-10-13 |
Electrical Isolation For Nanosheet Transistor Devices
App 20200312956 - Yeh; Chun-chen ; et al. | 2020-10-01 |
Vertical Field Effect Transistor With Top And Bottom Airgap Spacers
App 20200303497 - Yeh; Chun-Chen ; et al. | 2020-09-24 |
Fabrication of vertical field effect transistor structure with controlled gate length
Grant 10,784,357 - Cheng , et al. Sept | 2020-09-22 |
Fin field effect transistor fabrication and devices having inverted T-shaped gate
Grant 10,784,365 - Basker , et al. Sept | 2020-09-22 |
Confined Source Drain Epitaxy To Reduce Shorts In Cmos Integrated Circuits
App 20200295200 - Xie; Ruilong ; et al. | 2020-09-17 |
Integration of vertical-transport transistors and planar transistors
Grant 10,777,465 - Xie , et al. Sept | 2020-09-15 |
Mechanically Stable Complementary Field Effect Transistors
App 20200286788 - Xie; Ruilong ; et al. | 2020-09-10 |
Large area contacts for small transistors
Grant 10,749,031 - Cai , et al. A | 2020-08-18 |
Punch Through Stopper In Bulk Finfet Device
App 20200259002 - A1 | 2020-08-13 |
Dielectric Isolation For Nanosheet Devices
App 20200227305 - Cheng; Kangguo ; et al. | 2020-07-16 |
Fin Structures With Bottom Dielectric Isolation
App 20200227306 - Cheng; Kangguo ; et al. | 2020-07-16 |
Method and apparatus of forming high voltage varactor and vertical transistor on a substrate
Grant 10,714,470 - Cheng , et al. | 2020-07-14 |
Contact formation through low-temperature epitaxial deposition in semiconductor devices
Grant 10,692,868 - Gluschenkov , et al. | 2020-06-23 |
Vertical transistors with improved top source/drain junctions
Grant 10,680,081 - Cheng , et al. | 2020-06-09 |
Techniques for VFET top source/drain epitaxy
Grant 10,680,064 - Cheng , et al. | 2020-06-09 |
Forming Replacement Low-k Spacer In Tight Pitch Fin Field Effect Transistors
App 20200152765 - CAI; XIUYU ; et al. | 2020-05-14 |
Nanosheet Transistor With Dual Inner Airgap Spacers
App 20200144388 - Xie; Ruilong ; et al. | 2020-05-07 |
Vertical Field Effect Transistor With Reduced Parasitic Capacitance
App 20200135884 - Cheng; Kangguo ; et al. | 2020-04-30 |
Punch through stopper in bulk finFET device
Grant 10,629,709 - Basker , et al. | 2020-04-21 |
Forming replacement low-K spacer in tight pitch fin field effect transistors
Grant 10,622,457 - Cai , et al. | 2020-04-14 |
FinFET including tunable fin height and tunable fin width ratio
Grant 10,622,357 - Cai , et al. | 2020-04-14 |
VFET CMOS dual epitaxy integration
Grant 10,615,277 - Cheng , et al. | 2020-04-07 |
Method and apparatus of forming high voltage varactor and vertical transistor on a substrate
Grant 10,600,778 - Cheng , et al. | 2020-03-24 |
Forming replacement low-K spacer in tight pitch fin field effect transistors
Grant 10,593,780 - Cai , et al. | 2020-03-17 |
High Thermal Budget Compatible Punch Through Stop Integration Using Doped Glass
App 20200083323 - CHENG; KANGGUO ; et al. | 2020-03-12 |
High Thermal Budget Compatible Punch Through Stop Integration Using Doped Glass
App 20200083322 - CHENG; KANGGUO ; et al. | 2020-03-12 |
High thermal budget compatible punch through stop integration using doped glass
Grant 10,580,855 - Cheng , et al. | 2020-03-03 |
High thermal budget compatible punch through stop integration using doped glass
Grant 10,580,854 - Cheng , et al. | 2020-03-03 |
Dual Silicide Liner Flow For Enabling Low Contact Resistance
App 20200066583 - Adusumilli; Praneet ; et al. | 2020-02-27 |
Vertical field effect transistor with reduced parasitic capacitance
Grant 10,566,442 - Cheng , et al. Feb | 2020-02-18 |
Self-aligned contact process enabled by low temperature
Grant 10,566,454 - He , et al. Feb | 2020-02-18 |
Nanosheet transistor with dual inner airgap spacers
Grant 10,566,438 - Xie , et al. Feb | 2020-02-18 |
Nanosheet transitor with optimized junction and cladding defectivity control
Grant 10,566,443 - Cheng , et al. Feb | 2020-02-18 |
Nanosheet Transitor With Optimized Junction And Cladding Defectivity Control
App 20200044053 - Cheng; Kangguo ; et al. | 2020-02-06 |
Dual silicide liner flow for enabling low contact resistance
Grant 10,546,776 - Adusumilli , et al. Ja | 2020-01-28 |
Nanosheet transistor with optimized junction and cladding defectivity control
Grant 10,546,942 - Cheng , et al. Ja | 2020-01-28 |
CMOS structure having low resistance contacts and fabrication method
Grant 10,546,856 - Liu , et al. Ja | 2020-01-28 |
FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation
Grant 10,535,773 - Guo , et al. Ja | 2020-01-14 |
FinFET with merge-free fins
Grant 10,529,858 - He , et al. J | 2020-01-07 |
Vfet Cmos Dual Epitaxy Integration
App 20200006554 - Cheng; Kangguo ; et al. | 2020-01-02 |
Vertical Transistors Having Improved Control Of Top Source Or Drain Junctions
App 20200006528 - Cheng; Kangguo ; et al. | 2020-01-02 |
Self aligned gate shape preventing void formation
Grant 10,505,016 - Greene , et al. Dec | 2019-12-10 |
Vfet Cmos Dual Epitaxy Integration
App 20190363189 - Cheng; Kangguo ; et al. | 2019-11-28 |
VFET CMOS dual epitaxy integration
Grant 10,468,525 - Cheng , et al. No | 2019-11-05 |
Reduced capacitance in vertical transistors by preventing excessive overlap between the gate and the source/drain
Grant 10,453,939 - Cheng , et al. Oc | 2019-10-22 |
Integration of vertical-transport transistors and electrical fuses
Grant 10,439,031 - Xie , et al. O | 2019-10-08 |
Nanosheet Transistor With Dual Inner Airgap Spacers
App 20190305104 - Xie; Ruilong ; et al. | 2019-10-03 |
Vertical vacuum channel transistor
Grant 10,431,682 - Liu , et al. O | 2019-10-01 |
Extended Contact Area Using Undercut Silicide Extensions
App 20190267464 - Leobandung; Effendi ; et al. | 2019-08-29 |
Dual liner silicide
Grant 10,395,995 - Pranatharthiharan , et al. A | 2019-08-27 |
Vertical transistors with improved top source/drain junctions
Grant 10,396,208 - Cheng , et al. A | 2019-08-27 |
Parasitic capacitance reducing contact structure in a finFET
Grant 10,396,183 - Wang , et al. A | 2019-08-27 |
Test structure macro for monitoring dimensions of deep trench isolation regions and local trench isolation regions
Grant 10,396,000 - Yamashita , et al. A | 2019-08-27 |
Parasitic capacitance reducing contact structure in a finFET
Grant 10,388,769 - Wang , et al. A | 2019-08-20 |
Parasitic capacitance reducing contact structure in a finFET
Grant 10,388,768 - Wang , et al. A | 2019-08-20 |
Low resistance source drain contact formation
Grant 10,381,442 - Gluschenkov , et al. A | 2019-08-13 |
Vertically stacked multi-channel transistor structure
Grant 10,381,273 - Cheng , et al. A | 2019-08-13 |
Fabrication of vertical field effect transistor structure with controlled gate length
Grant 10,367,069 - Cheng , et al. July 30, 2 | 2019-07-30 |
Low-drive current FinFET structure for improving circuit density of ratioed logic in SRAM devices
Grant 10,361,210 - Basker , et al. | 2019-07-23 |
Method and apparatus of fabricating source and drain epitaxy for vertical field effect transistor
Grant 10,361,315 - Yeh , et al. | 2019-07-23 |
High doped III-V source/drain junctions for field effect transistors
Grant 10,355,086 - Cai , et al. July 16, 2 | 2019-07-16 |
FinFETs having strained channels, and methods of fabricating finFETs having strained channels
Grant 10,355,020 - Liu , et al. July 16, 2 | 2019-07-16 |
Integration Of Vertical-transport Transistors And Planar Transistors
App 20190214307 - Xie; Ruilong ; et al. | 2019-07-11 |
Extended contact area using undercut silicide extensions
Grant 10,347,739 - Leobandung , et al. July 9, 2 | 2019-07-09 |
Nanosheet transistors on bulk material
Grant 10,347,719 - Cheng , et al. July 9, 2 | 2019-07-09 |
Finfet Including Tunable Fin Height And Tunable Fin Width Ratio
App 20190206868 - Cai; Xiuyu ; et al. | 2019-07-04 |
Spacers for tight gate pitches in field effect transistors
Grant 10,340,362 - Xie , et al. | 2019-07-02 |
Inner spacer for nanosheet transistors
Grant 10,332,961 - Cheng , et al. | 2019-06-25 |
Low Resistance Source Drain Contact Formation with Trench Metastable Alloys and Laser Annealing
App 20190181012 - Gluschenkov; Oleg ; et al. | 2019-06-13 |
Random Matrix Hardware For Machine Learning
App 20190180185 - Sun; Xiao ; et al. | 2019-06-13 |
Fin field effect transistor fabrication and devices having inverted T-shaped gate
Grant 10,319,840 - Basker , et al. | 2019-06-11 |
Integrated circuit structure having VFET and embedded memory structure and method of forming same
Grant 10,319,731 - Xie , et al. | 2019-06-11 |
Localized fin width scaling using a hydrogen anneal
Grant 10,312,377 - Basker , et al. | 2019-06-04 |
Fin Field Effect Transistor Fabrication And Devices Having Inverted T-shaped Gate
App 20190165142 - Basker; Veeraraghavan S. ; et al. | 2019-05-30 |
Dual liner silicide
Grant 10,304,747 - Pranatharthiharan , et al. | 2019-05-28 |
Finfet With Sigma Recessed Source/drain And Un-doped Buffer Layer Epitaxy For Uniform Junction Formation
App 20190157457 - Guo; Dechao ; et al. | 2019-05-23 |
Methods of forming a gate contact structure for a transistor
Grant 10,297,452 - Xie , et al. | 2019-05-21 |
Contact Formation Through Low-tempearature Epitaxial Deposition In Semiconductor Devices
App 20190148377 - Gluschenkov; Oleg ; et al. | 2019-05-16 |
Method And Apparatus Of Forming High Voltage Varactor And Vertical Transistor On A Substrate
App 20190148360 - Cheng; Kangguo ; et al. | 2019-05-16 |
Method And Apparatus Of Forming High Voltage Varactor And Vertical Transistor On A Substrate
App 20190148362 - Cheng; Kangguo ; et al. | 2019-05-16 |
Semiconductor device having fins with in-situ doped, punch-through stopper layer and related methods
Grant 10,290,636 - Liu , et al. | 2019-05-14 |
Techniques for VFET Top Source/Drain Epitaxy
App 20190140052 - Cheng; Kangguo ; et al. | 2019-05-09 |
Test structure macro for monitoring dimensions of deep trench isolation regions and local trench isolation regions
Grant 10,283,423 - Yamashita , et al. | 2019-05-07 |
FinFET including tunable fin height and tunable fin width ratio
Grant 10,276,573 - Cai , et al. | 2019-04-30 |
Air gap adjacent a bottom source/drain region of vertical transistor device
Grant 10,276,659 - Xie , et al. | 2019-04-30 |
Aspect Ratio Trapping In Channel Last Process
App 20190123178 - Leobandung; Effendi ; et al. | 2019-04-25 |
Stacked nanosheet field-effect transistor with air gap spacers
Grant 10,269,983 - Frougier , et al. | 2019-04-23 |
Nanosheet transistors having thin and thick gate dielectric material
Grant 10,269,920 - Cheng , et al. | 2019-04-23 |
Contact Formation Through Low-tempearature Epitaxial Deposition In Semiconductor Devices
App 20190115347 - Gluschenkov; Oleg ; et al. | 2019-04-18 |
Forming vertical transistors and metal-insulator-metal capacitors on the same chip
Grant 10,256,231 - Cheng , et al. | 2019-04-09 |
High doped III-V source/drain junctions for field effect transistors
Grant 10,256,304 - Cai , et al. | 2019-04-09 |
Method Of Forming Vertical Field Effect Transistors With Different Gate Lengths And A Resulting Structure
App 20190103319 - Qi; Yi ; et al. | 2019-04-04 |
FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation
Grant 10,249,758 - Guo , et al. | 2019-04-02 |
Aspect ratio trapping in channel last process
Grant 10,249,736 - Leobandung , et al. | 2019-04-02 |
Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction
Grant 10,249,714 - Guo , et al. | 2019-04-02 |
Low resistance source drain contact formation with trench metastable alloys and laser annealing
Grant 10,249,502 - Gluschenkov , et al. | 2019-04-02 |
Method of forming vertical field effect transistors with different gate lengths and a resulting structure
Grant 10,249,538 - Qi , et al. | 2019-04-02 |
Compact Vertical Injection Punch through Floating Gate Analog Memory and a Manufacture Thereof
App 20190097060 - Leobandung; Effendi ; et al. | 2019-03-28 |
Methods Of Forming A Gate Contact Structure For A Transistor
App 20190096677 - Xie; Ruilong ; et al. | 2019-03-28 |
Vertical vacuum channel transistor
Grant 10,243,074 - Liu , et al. | 2019-03-26 |
Highly compact floating gate analog memory
Grant 10,242,991 - Leobandung , et al. | 2019-03-26 |
Stress memorization technique for strain coupling enhancement in bulk FINFET device
Grant 10,242,916 - Cheng , et al. | 2019-03-26 |
Vertical field-effect transistors with controlled dimensions
Grant 10,236,363 - Xie , et al. | 2019-03-19 |
Punch through stopper in bulk finFET device
Grant 10,224,420 - Basker , et al. | 2019-03-05 |
Fin field effect transistor fabrication and devices having inverted T-shaped gate
Grant 10,224,417 - Basker , et al. | 2019-03-05 |
Vertical transistor devices with different effective gate lengths
Grant 10,217,672 - Xie , et al. Feb | 2019-02-26 |
Integrated Circuit Structure Having Vfet And Embedded Memory Structure And Method Of Forming Same
App 20190051659 - Xie; Ruilong ; et al. | 2019-02-14 |
Metal-insulator-metal capacitor analog memory unit cell
Grant 10,204,907 - Leobandung , et al. Feb | 2019-02-12 |
Techniques for VFET top source/drain epitaxy
Grant 10,199,464 - Cheng , et al. Fe | 2019-02-05 |
Controlling self-aligned gate length in vertical transistor replacement gate flow
Grant 10,199,480 - Xie , et al. Fe | 2019-02-05 |
Nanosheet Transitor With Optimized Junction And Cladding Defectivity Control
App 20190035913 - Cheng; Kangguo ; et al. | 2019-01-31 |
Nanosheet Transitor With Optimized Junction And Cladding Defectivity Control
App 20190035911 - Cheng; Kangguo ; et al. | 2019-01-31 |
Circuit For Cmos Based Resistive Processing Unit
App 20190005381 - Li; Yulong ; et al. | 2019-01-03 |
Highly Compact Floating Gate Analog Memory
App 20190006377 - Leobandung; Effendi ; et al. | 2019-01-03 |
Circuit For Cmos Based Resistive Processing Unit
App 20190005382 - Li; Yulong ; et al. | 2019-01-03 |
Metal-insulator-metal Capacitor Analog Memory Unit Cell
App 20190006366 - Leobandung; Effendi ; et al. | 2019-01-03 |
Stress memorization technique for strain coupling enhancement in bulk finFET device
Grant 10,170,364 - Cheng , et al. J | 2019-01-01 |
Punch through stopper in bulk finFET device
Grant 10,170,594 - Basker , et al. J | 2019-01-01 |
Fin density control of multigate devices through sidewall image transfer processes
Grant 10,170,327 - He , et al. J | 2019-01-01 |
Finfet including improved epitaxial topology
Grant 10,164,110 - Basker , et al. Dec | 2018-12-25 |
Finfet With Sigma Recessed Source/drain And Un-doped Buffer Layer Epitaxy For Uniform Junction Formation
App 20180358465 - Guo; Dechao ; et al. | 2018-12-13 |
Punch Through Stopper In Bulk Finfet Device
App 20180350959 - Basker; Veeraraghavan S. ; et al. | 2018-12-06 |
Integration Of Vertical-transport Transistors And High-voltage Transistors
App 20180342507 - Xie; Ruilong ; et al. | 2018-11-29 |
Fabrication Of Vertical Field Effect Transistor Structure With Controlled Gate Length
App 20180342592 - Cheng; Kangguo ; et al. | 2018-11-29 |
Nanowire semiconductor device including lateral-etch barrier region
Grant 10,134,864 - Basker , et al. November 20, 2 | 2018-11-20 |
Floating gate architecture for deep neural network application
Grant 10,134,472 - Leobandung , et al. November 20, 2 | 2018-11-20 |
Vertical slit transistor with optimized AC performance
Grant 10,134,903 - Liu , et al. November 20, 2 | 2018-11-20 |
Series resistance reduction in vertically stacked silicon nanowire transistors
Grant 10,134,840 - Yeh , et al. November 20, 2 | 2018-11-20 |
Stacked Nanosheet Field-effect Transistor With Airgap Spacers
App 20180331232 - Frougier; Julien ; et al. | 2018-11-15 |
Self-aligned Contact Process Enabled By Low Temperature
App 20180331039 - HE; Hong ; et al. | 2018-11-15 |
Nanosheet Transistors On Bulk Material
App 20180331179 - Cheng; Kangguo ; et al. | 2018-11-15 |
Nanowire semiconductor device including lateral-etch barrier region
Grant 10,128,335 - Basker , et al. November 13, 2 | 2018-11-13 |
Air Gap Adjacent A Bottom Source/drain Region Of Vertical Transistor Device
App 20180308930 - Xie; Ruilong ; et al. | 2018-10-25 |
Punch through stopper in bulk FinFET device
Grant 10,109,723 - Basker , et al. October 23, 2 | 2018-10-23 |
Vertical Field Effect Transistor With Reduced Parasitic Capacitance
App 20180301541 - Cheng; Kangguo ; et al. | 2018-10-18 |
Vertical transistor having buried contact, and contacts using work function metals and silicides
Grant 10,103,247 - Xie , et al. October 16, 2 | 2018-10-16 |
Punch through stopper in bulk finFET device
Grant 10,103,251 - Basker , et al. October 16, 2 | 2018-10-16 |
Vertical Field Effect Transistor With Reduced Parasitic Capacitance
App 20180294340 - Cheng; Kangguo ; et al. | 2018-10-11 |
Vertical field effect transistor with reduced parasitic capacitance
Grant 10,096,692 - Cheng , et al. October 9, 2 | 2018-10-09 |
FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation
Grant 10,096,713 - Guo , et al. October 9, 2 | 2018-10-09 |
Punch through stopper in bulk finFET device
Grant 10,084,070 - Basker , et al. September 25, 2 | 2018-09-25 |
Vertical Field-effect Transistors With Controlled Dimensions
App 20180269312 - Xie; Ruilong ; et al. | 2018-09-20 |
Fabrication of vertical field effect transistor structure with controlled gate length
Grant 10,079,292 - Cheng , et al. September 18, 2 | 2018-09-18 |
Metal-insulator-metal capacitor analog memory unit cell
Grant 10,079,234 - Leobandung , et al. September 18, 2 | 2018-09-18 |
Composite Spacer Enabling Uniform Doping In Recessed Fin Devices
App 20180248017 - Basker; Veeraraghavan S. ; et al. | 2018-08-30 |
Semiconductor devices having low contact resistance and low current leakage
Grant 10,062,762 - Liu , et al. August 28, 2 | 2018-08-28 |
Techniques for VFET Top Source/Drain Epitaxy
App 20180240873 - Cheng; Kangguo ; et al. | 2018-08-23 |
Methods Of Forming Vertical Transistor Devices With Different Effective Gate Lengths And The Resulting Devices
App 20180240715 - Xie; Ruilong ; et al. | 2018-08-23 |
Low Resistance Source Drain Contact Formation
App 20180240875 - Gluschenkov; Oleg ; et al. | 2018-08-23 |
Silicon nitride fill for PC gap regions to increase cell density
Grant 10,056,378 - Guo , et al. August 21, 2 | 2018-08-21 |
Dual Liner Silicide
App 20180233417 - Pranatharthiharan; Balasubramanian ; et al. | 2018-08-16 |
Nanosheet Transistors On Bulk Material
App 20180233557 - Cheng; Kangguo ; et al. | 2018-08-16 |
Nanosheet Transistors Having Thin And Thick Gate Dielectric Material
App 20180233572 - Cheng; Kangguo ; et al. | 2018-08-16 |
Nanosheet transistors on bulk material
Grant 10,050,107 - Cheng , et al. August 14, 2 | 2018-08-14 |
Spacers For Tight Gate Pitches In Field Effect Transistors
App 20180219079 - Xie; Ruilong ; et al. | 2018-08-02 |
Self-aligned contact process enabled by low temperature
Grant 10,037,944 - He , et al. July 31, 2 | 2018-07-31 |
Parasitic capacitance reducing contact structure in a finFET
Grant 10,038,076 - Wang , et al. July 31, 2 | 2018-07-31 |
Integrated single-gated vertical field effect transistor (VFET) and independent double-gated VFET
Grant 10,037,919 - Xie , et al. July 31, 2 | 2018-07-31 |
Stress Memorization Technique For Strain Coupling Enhancement In Bulk Finfet Device
App 20180211879 - Cheng; Kangguo ; et al. | 2018-07-26 |
Method and structure to fabricate closely packed hybrid nanowires at scaled pitch
Grant 10,032,677 - Basker , et al. July 24, 2 | 2018-07-24 |
Vertical Transistors With Improved Top Source/drain Junctions
App 20180204950 - Cheng; Kangguo ; et al. | 2018-07-19 |
Forming Vertical Transistors And Metal-insulator-metal Capacitors On The Same Chip
App 20180204833 - Cheng; Kangguo ; et al. | 2018-07-19 |
Vertical Transistors With Improved Top Source/drain Junctions
App 20180204951 - Cheng; Kangguo ; et al. | 2018-07-19 |
Finfet With Merge-free Fins
App 20180197980 - He; Hong ; et al. | 2018-07-12 |
Stress memorization technique for strain coupling enhancement in bulk finFET device
Grant 10,020,227 - Cheng , et al. July 10, 2 | 2018-07-10 |
Methods for forming FinFETs having epitaxial Si S/D extensions with flat top surfaces on a SiGe seed layer
Grant 10,020,303 - He , et al. July 10, 2 | 2018-07-10 |
Air gap adjacent a bottom source/drain region of vertical transistor device
Grant 10,014,370 - Xie , et al. July 3, 2 | 2018-07-03 |
Spacers for tight gate pitches in field effect transistors
Grant 10,008,582 - Xie , et al. June 26, 2 | 2018-06-26 |
High Doped Iii-v Source/drain Junctions For Field Effect Transistors
App 20180175202 - Cai; Xiuyu ; et al. | 2018-06-21 |
Nanowire semiconductor device including lateral-etch barrier region
Grant 10,002,921 - Basker , et al. June 19, 2 | 2018-06-19 |
Composite spacer enabling uniform doping in recessed fin devices
Grant 10,002,945 - Basker , et al. June 19, 2 | 2018-06-19 |
Nanosheet transistors having thin and thick gate dielectric material
Grant 10,002,939 - Cheng , et al. June 19, 2 | 2018-06-19 |
Dual liner silicide
Grant 9,997,418 - Pranatharthiharan , et al. June 12, 2 | 2018-06-12 |
Implantation formed metal-insulator-semiconductor (MIS) contacts
Grant 9,997,609 - Chen , et al. June 12, 2 | 2018-06-12 |
Non-lithographic line pattern formation
Grant 9,997,367 - Tseng , et al. June 12, 2 | 2018-06-12 |
FinFETs with non-merged epitaxial S/D extensions having a SiGe seed layer on insulator
Grant 9,991,258 - He , et al. June 5, 2 | 2018-06-05 |
Implantation formed metal-insulator-semiconductor (MIS) contacts
Grant 9,991,355 - Chen , et al. June 5, 2 | 2018-06-05 |
FinFETs with non-merged epitaxial S/D extensions on a seed layer and having flat top surfaces
Grant 9,991,255 - He , et al. June 5, 2 | 2018-06-05 |
Anchored stress-generating active semiconductor regions for semiconductor-on-insulator FinFET
Grant 9,991,366 - Basker , et al. June 5, 2 | 2018-06-05 |
Spacers For Tight Gate Pitches In Field Effect Transistors
App 20180151689 - Xie; Ruilong ; et al. | 2018-05-31 |
FinFET semiconductor device having integrated SiGe fin
Grant 9,985,030 - Cheng , et al. May 29, 2 | 2018-05-29 |
High thermal budget compatible punch through stop integration using doped glass
Grant 9,985,096 - Cheng , et al. May 29, 2 | 2018-05-29 |
Salicide formation on replacement metal gate finFET devices
Grant 9,985,130 - Leobandung , et al. May 29, 2 | 2018-05-29 |
Fabrication Of Vertical Field Effect Transistor Structure With Controlled Gate Length
App 20180138277 - Cheng; Kangguo ; et al. | 2018-05-17 |
Low resistance source drain contact formation
Grant 9,972,682 - Gluschenkov , et al. May 15, 2 | 2018-05-15 |
Integration Of Vertical-transport Transistors And Electrical Fuses
App 20180122913 - Xie; Ruilong ; et al. | 2018-05-03 |
Inner Spacer For Nanosheet Transistors
App 20180122900 - Cheng; Kangguo ; et al. | 2018-05-03 |
Fin Field Effect Transistor Fabrication And Devices Having Inverted T-shaped Gate
App 20180122923 - Basker; Veeraraghavan S. ; et al. | 2018-05-03 |
Dual Liner Silicide
App 20180122711 - Pranatharthiharan; Balasubramanian ; et al. | 2018-05-03 |
Method of forming vertical field effect transistors with different threshold voltages and the resulting integrated circuit structure
Grant 9,960,271 - Xie , et al. May 1, 2 | 2018-05-01 |
FinFET semiconductor device
Grant 9,953,977 - Cheng , et al. April 24, 2 | 2018-04-24 |
FinFET with merge-free fins
Grant 9,947,791 - He , et al. April 17, 2 | 2018-04-17 |
Nanowire semiconductor device including lateral-etch barrier region
Grant 9,947,744 - Basker , et al. April 17, 2 | 2018-04-17 |
Tunneling fin type field effect transistor with epitaxial source and drain regions
Grant 9,947,586 - Basker , et al. April 17, 2 | 2018-04-17 |
Vertical Vacuum Channel Transistor
App 20180102433 - Liu; Qing ; et al. | 2018-04-12 |
Stress Memorization Technique For Strain Coupling Enhancement In Bulk Finfet Device
App 20180102290 - Cheng; Kangguo ; et al. | 2018-04-12 |
Vertical Vacuum Channel Transistor
App 20180102432 - Liu; Qing ; et al. | 2018-04-12 |
Reduced Capacitance In Vertical Transistors By Preventing Excessive Overlap Between The Gate And The Source/drain
App 20180097086 - Cheng; Kangguo ; et al. | 2018-04-05 |
High doped III-V source/drain junctions for field effect transistors
Grant 9,935,201 - Cai , et al. April 3, 2 | 2018-04-03 |
Methods of forming vertical transistor devices with different effective gate lengths
Grant 9,935,018 - Xie , et al. April 3, 2 | 2018-04-03 |
Method for making semiconductor device with filled gate line end recesses
Grant 9,935,179 - Cai , et al. April 3, 2 | 2018-04-03 |
Controlling Self-aligned Gate Length In Vertical Transistor Replacement Gate Flow
App 20180090598 - XIE; Ruilong ; et al. | 2018-03-29 |
Forming air-gap spacer for vertical field effect transistor
Grant 9,929,246 - Cheng , et al. March 27, 2 | 2018-03-27 |
Method for making a semiconductor device with sidewal spacers for confinig epitaxial growth
Grant 9,929,253 - Cai , et al. March 27, 2 | 2018-03-27 |
Dual liner silicide
Grant 9,929,059 - Pranatharthiharan , et al. March 27, 2 | 2018-03-27 |
Parasitic Capacitance Reducing Contact Structure In A Finfet
App 20180083124 - Wang; Miaomiao ; et al. | 2018-03-22 |
Inner spacer for nanosheet transistors
Grant 9,923,055 - Cheng , et al. March 20, 2 | 2018-03-20 |
Method for making strained semiconductor device and related methods
Grant 9,922,883 - Cai , et al. March 20, 2 | 2018-03-20 |
Parasitic Capacitance Reducing Contact Structure In A Finfet
App 20180076304 - Wang; Miaomiao ; et al. | 2018-03-15 |
Parasitic Capacitance Reducing Contact Structure In A Finfet
App 20180076303 - Wang; Miaomiao ; et al. | 2018-03-15 |
Nanosheet transistors on bulk material
Grant 9,917,152 - Cheng , et al. March 13, 2 | 2018-03-13 |
High doped III-V source/drain junctions for field effect transistors
Grant 9,917,195 - Cai , et al. March 13, 2 | 2018-03-13 |
Fabrication of vertical field effect transistor structure with controlled gate length
Grant 9,917,162 - Cheng , et al. March 13, 2 | 2018-03-13 |
Silicon Nitride Fill For Pc Gap Regions To Increase Cell Density
App 20180069002 - Guo; Dechao ; et al. | 2018-03-08 |
Composite Spacer Enabling Uniform Doping In Recessed Fin Devices
App 20180061966 - Basker; Veeraraghavan S. ; et al. | 2018-03-01 |
High Thermal Budget Compatible Punch Through Stop Integration Using Doped Glass
App 20180061940 - CHENG; KANGGUO ; et al. | 2018-03-01 |
Increased contact area for finFETs
Grant 9,899,525 - Basker , et al. February 20, 2 | 2018-02-20 |
Forming vertical transistors and metal-insulator-metal capacitors on the same chip
Grant 9,899,373 - Cheng , et al. February 20, 2 | 2018-02-20 |
Fin field effect transistor fabrication and devices having inverted T-shaped gate
Grant 9,893,171 - Basker , et al. February 13, 2 | 2018-02-13 |
Stress memorization technique for strain coupling enhancement in bulk finFET device
Grant 9,892,973 - Cheng , et al. February 13, 2 | 2018-02-13 |
High Thermal Budget Compatible Punch Through Stop Integration Using Doped Glass
App 20180040692 - CHENG; KANGGUO ; et al. | 2018-02-08 |
Parasitic Capacitance Reducing Contact Structure In A Finfet
App 20180040719 - Wang; Miaomiao ; et al. | 2018-02-08 |
FinFET including tunable fin height and tunable fin width ratio
Grant 9,887,196 - Cai , et al. February 6, 2 | 2018-02-06 |
Punch Through Stopper In Bulk Finfet Device
App 20180026120 - Basker; Veeraraghavan S. ; et al. | 2018-01-25 |
Formation of VFET and finFET
Grant 9,870,952 - Cheng , et al. January 16, 2 | 2018-01-16 |
Method and structure to fabricate closely packed hybrid nanowires at scaled pitch
Grant 9,865,508 - Basker , et al. January 9, 2 | 2018-01-09 |
Hetero-channel FinFET
Grant 9,859,423 - Liu , et al. January 2, 2 | 2018-01-02 |
Low-drive current FinFET structure for improving circuit density of ratioed logic in SRAM devices
Grant 9,859,286 - Basker , et al. January 2, 2 | 2018-01-02 |
Silicon nitride fill for PC gap regions to increase cell density
Grant 9,859,275 - Guo , et al. January 2, 2 | 2018-01-02 |
Self aligned epitaxial based punch through control
Grant 9,853,159 - Basker , et al. December 26, 2 | 2017-12-26 |
Method and structure for multigate FinFet device epi-extension junction control by hydrogen treatment
Grant 9,853,158 - Basker , et al. December 26, 2 | 2017-12-26 |
Aspect Ratio Trapping In Channel Last Process
App 20170365692 - Leobandung; Effendi ; et al. | 2017-12-21 |
High thermal budget compatible punch through stop integration using doped glass
Grant 9,847,388 - Cheng , et al. December 19, 2 | 2017-12-19 |
Stress Memorization Technique For Strain Coupling Enhancement In Bulk Finfet Device
App 20170358496 - Cheng; Kangguo ; et al. | 2017-12-14 |
Fin Field Effect Transistor Fabrication And Devices Having Inverted T-shaped Gate
App 20170352659 - Basker; Veeraraghavan S. ; et al. | 2017-12-07 |
Fin Field Effect Transistor Fabrication And Devices Having Inverted T-shaped Gate
App 20170352744 - Basker; Veeraraghavan S. ; et al. | 2017-12-07 |
Punch Through Stopper In Bulk Finfet Device
App 20170323956 - Basker; Veeraraghavan S. ; et al. | 2017-11-09 |
Forming vertical transistors and metal-insulator-metal capacitors on the same chip
Grant 9,812,443 - Cheng , et al. November 7, 2 | 2017-11-07 |
Controlling channel length for vertical FETs
Grant 9,806,153 - Cheng , et al. October 31, 2 | 2017-10-31 |
Dual silicide liner flow for enabling low contact resistance
Grant 9,805,973 - Adusumilli , et al. October 31, 2 | 2017-10-31 |
Self Aligned Epitaxial Based Punch Through Control
App 20170301786 - Basker; Veeraraghavan S. ; et al. | 2017-10-19 |
Buried source-drain contact for integrated circuit transistor devices and method of making same
Grant 9,793,171 - Liu , et al. October 17, 2 | 2017-10-17 |
Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction and semiconductor device having reduced junction leakage
Grant 9,793,272 - Guo , et al. October 17, 2 | 2017-10-17 |
Vertical vacuum channel transistor
Grant 9,793,395 - Liu , et al. October 17, 2 | 2017-10-17 |
Method Of Forming Epitaxial Buffer Layer For Finfet Source And Drain Junction Leakage Reduction
App 20170294510 - GUO; DECHAO ; et al. | 2017-10-12 |
Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction
Grant 9,786,661 - Guo , et al. October 10, 2 | 2017-10-10 |
Fabrication Of Vertical Field Effect Transistor Structure With Controlled Gate Length
App 20170288039 - Cheng; Kangguo ; et al. | 2017-10-05 |
Fabrication Of Vertical Field Effect Transistor Structure With Controlled Gate Length
App 20170288030 - Cheng; Kangguo ; et al. | 2017-10-05 |
Extended Contact Area Using Undercut Silicide Extensions
App 20170278942 - Leobandung; Effendi ; et al. | 2017-09-28 |
Self aligned gate shape preventing void formation
Grant 9,773,885 - Greene , et al. September 26, 2 | 2017-09-26 |
Fin Density Control Of Multigate Devices Through Sidewall Image Transfer Processes
App 20170271167 - He; Hong ; et al. | 2017-09-21 |
FinFET having controlled dielectric region height
Grant 9,768,027 - Guo , et al. September 19, 2 | 2017-09-19 |
Stress memorization technique for strain coupling enhancement in bulk finFET device
Grant 9,761,717 - Cheng , et al. September 12, 2 | 2017-09-12 |
Trench epitaxial growth for a FinFET device having reduced capacitance
Grant 9,755,031 - Liu , et al. September 5, 2 | 2017-09-05 |
Increased Contact Area For Finfets
App 20170250285 - Basker; Veeraraghavan S. ; et al. | 2017-08-31 |
Process for integrated circuit fabrication including a uniform depth tungsten recess technique
Grant 9,748,351 - Liu , et al. August 29, 2 | 2017-08-29 |
Multi-channel gate-all-around FET
Grant 9,748,352 - Liu , et al. August 29, 2 | 2017-08-29 |
Forming vertical and horizontal field effect transistors on the same substrate
Grant 9,741,716 - Cheng , et al. August 22, 2 | 2017-08-22 |
Tunneling Fin Type Field Effect Transistor With Epitaxial Source And Drain Regions
App 20170236755 - Basker; Veeraraghavan S. ; et al. | 2017-08-17 |
Nanowire Semiconductor Device Including Lateral-etch Barrier Region
App 20170229553 - Basker; Veeraraghavan S. ; et al. | 2017-08-10 |
Densely spaced fins for semiconductor fin field effect transistors
Grant 9,728,534 - He , et al. August 8, 2 | 2017-08-08 |
Fin density control of multigate devices through sidewall image transfer processes
Grant 9,728,419 - He , et al. August 8, 2 | 2017-08-08 |
Nanowire Semiconductor Device Including Lateral-etch Barrier Region
App 20170221991 - Basker; Veeraraghavan S. ; et al. | 2017-08-03 |
Low Resistance Source Drain Contact Formation
App 20170213889 - Gluschenkov; Oleg ; et al. | 2017-07-27 |
Low Resistance Source Drain Contact Formation with Trench Metastable Alloys and Laser Annealing
App 20170213739 - Gluschenkov; Oleg ; et al. | 2017-07-27 |
Reduced capacitance in vertical transistors by preventing excessive overlap between the gate and the source/drain
Grant 9,716,170 - Cheng , et al. July 25, 2 | 2017-07-25 |
Method For Making Semiconductor Device With Filled Gate Line End Recesses
App 20170200812 - CAI; XIUYU ; et al. | 2017-07-13 |
Self Aligned Gate Shape Preventing Void Formation
App 20170200807 - Greene; Andrew M. ; et al. | 2017-07-13 |
Stress Memorization Technique For Strain Coupling Enhancement In Bulk Finfet Device
App 20170194206 - Cheng; Kangguo ; et al. | 2017-07-06 |
Self Aligned Gate Shape Preventing Void Formation
App 20170178967 - Greene; Andrew M. ; et al. | 2017-06-22 |
Method and Structure to Fabricate Closely Packed Hybrid Nanowires at Scaled Pitch
App 20170170073 - Basker; Veeraraghavan S. ; et al. | 2017-06-15 |
Self-aligned Contact Process Enabled By Low Temperature
App 20170141038 - HE; Hong ; et al. | 2017-05-18 |
Dual Silicide Liner Flow For Enabling Low Contact Resistance
App 20170125289 - Adusumilli; Praneet ; et al. | 2017-05-04 |
Dual Silicide Liner Flow For Enabling Low Contact Resistance
App 20170125306 - Adusumilli; Praneet ; et al. | 2017-05-04 |
Dual Silicide Liner Flow For Enabling Low Contact Resistance
App 20170125338 - Adusumilli; Praneet ; et al. | 2017-05-04 |
High Doped Iii-v Source/drain Junctions For Field Effect Transistors
App 20170110583 - Cai; Xiuyu ; et al. | 2017-04-20 |
Forming Replacement Low-k Spacer In Tight Pitch Fin Field Effect Transistors
App 20170104082 - CAI; XIUYU ; et al. | 2017-04-13 |
Forming Replacement Low-k Spacer In Tight Pitch Fin Field Effect Transistors
App 20170103917 - CAI; XIUYU ; et al. | 2017-04-13 |
Stress Memorization Technique For Strain Coupling Enhancement In Bulk Finfet Device
App 20170084743 - Cheng; Kangguo ; et al. | 2017-03-23 |
Stress Memorization Technique For Strain Coupling Enhancement In Bulk Finfet Device
App 20170084744 - Cheng; Kangguo ; et al. | 2017-03-23 |
Dual Liner Silicide
App 20170084500 - Pranatharthiharan; Balasubramanian ; et al. | 2017-03-23 |
Method And Structure To Fabricate Closely Packed Hybrid Nanowires At Scaled Pitch
App 20170076990 - Basker; Veeraraghavan S. ; et al. | 2017-03-16 |
Vertical Slit Transistor With Optimized Ac Performance
App 20170077306 - Liu; Qing ; et al. | 2017-03-16 |
Punch Through Stopper In Bulk Finfet Device
App 20170077268 - Basker; Veeraraghavan S. ; et al. | 2017-03-16 |
Method and Structure to Fabricate Closely Packed Hybrid Nanowires at Scaled Pitch
App 20170077264 - Basker; Veeraraghavan S. ; et al. | 2017-03-16 |
Composite Spacer Enabling Uniform Doping In Recessed Fin Devices
App 20170062601 - Basker; Veeraraghavan S. ; et al. | 2017-03-02 |
Composite Spacer Enabling Uniform Doping In Recessed Fin Devices
App 20170062584 - Basker; Veeraraghavan S. ; et al. | 2017-03-02 |
High Thermal Budget Compatible Punch Through Stop Integration Using Doped Glass
App 20170062566 - CHENG; KANGGUO ; et al. | 2017-03-02 |
High Thermal Budget Compatible Punch Through Stop Integration Using Doped Glass
App 20170062557 - CHENG; KANGGUO ; et al. | 2017-03-02 |
Semiconductor Device Including Dual Spacer And Uniform Epitaxial Buffer Interface Of Embedded Sige Source/drain
App 20170062614 - Basker; Veeraraghavan S. ; et al. | 2017-03-02 |
Semiconductor Device Including Dual Spacer And Uniform Epitaxial Buffer Interface Of Embedded Sige Source/drain
App 20170062588 - Basker; Veeraraghavan S. ; et al. | 2017-03-02 |
Series Resistance Reduction In Vertically Stacked Silicon Nanowire Transistors
App 20170053982 - Cai; Xiuyu ; et al. | 2017-02-23 |
Salicide Formation On Replacement Metal Gate Finfet Devices
App 20170047250 - Leobandung; Effendi ; et al. | 2017-02-16 |
Low-k Spacer For Rmg Finfet Formation
App 20170040437 - He; Hong ; et al. | 2017-02-09 |
High Doped Iii-v Source/drain Junctions For Field Effect Transistors
App 20170033221 - Cai; Xiuyu ; et al. | 2017-02-02 |
High Doped Iii-v Source/drain Junctions For Field Effect Transistors
App 20170033197 - Cai; Xiuyu ; et al. | 2017-02-02 |
Test Structure Macro For Monitoring Dimensions Of Deep Trench Isolation Regions And Local Trench Isolation Regions
App 20170033023 - Yamashita; Tenko ; et al. | 2017-02-02 |
Non-merged Epitaxially Grown Mosfet Devices
App 20170033104 - HE; HONG ; et al. | 2017-02-02 |
Localized Fin Width Scaling Using A Hydrogen Anneal
App 20170033201 - BASKER; VEERARAGHAVAN S. ; et al. | 2017-02-02 |
Process For Integrated Circuit Fabrication Including A Uniform Depth Tungsten Recess Technique
App 20170012105 - LIU; QING ; et al. | 2017-01-12 |
Increased Contact Area For Finfets
App 20170012129 - Basker; Veeraraghavan S. ; et al. | 2017-01-12 |
Large Area Contacts For Small Transistors
App 20170012130 - CAI; Xiuyu ; et al. | 2017-01-12 |
Test Structure Macro For Monitoring Dimensions Of Deep Trench Isolation Regions And Local Trench Isolation Regions
App 20170005014 - Yamashita; Tenko ; et al. | 2017-01-05 |
Nanowire Semiconductor Device Including Lateral-etch Barrier Region
App 20160380054 - Basker; Veeraraghavan S. ; et al. | 2016-12-29 |
Nanowire Semiconductor Device Including Lateral-etch Barrier Region
App 20160380083 - Basker; Veeraraghavan S. ; et al. | 2016-12-29 |
Dual Liner Silicide
App 20160372332 - Pranatharthiharan; Balasubramanian ; et al. | 2016-12-22 |
Dual Channel Finfet With Relaxed Pfet Region
App 20160372493 - Cai; Xiuyu ; et al. | 2016-12-22 |
Punch Through Stopper In Bulk Finfet Device
App 20160372589 - Basker; Veeraraghavan S. ; et al. | 2016-12-22 |
Dual Liner Silicide
App 20160372380 - Pranatharthiharan; Balasubramanian ; et al. | 2016-12-22 |
Series Resistance Reduction In Vertically Stacked Silicon Nanowire Transistors
App 20160365411 - Yeh; Chun-Chen ; et al. | 2016-12-15 |
Punch Through Stopper In Bulk Finfet Device
App 20160365432 - Basker; Veeraraghavan S. ; et al. | 2016-12-15 |
Salicide Formation On Replacement Metal Gate Finfet Devices
App 20160343856 - Leobandung; Effendi ; et al. | 2016-11-24 |
Non-lithographic Line Pattern Formation
App 20160329214 - Tseng; Chiahsun ; et al. | 2016-11-10 |
Finfet Having Controlled Dielectric Region Height
App 20160314976 - Guo; Dechao ; et al. | 2016-10-27 |
Method And Structure For Multigate Finfet Device Epi-extension Junction Control By Hydrogen Treatment
App 20160315183 - Basker; Veeraraghavan S. ; et al. | 2016-10-27 |
Method For Making Strained Semiconductor Device And Related Methods
App 20160293494 - Cai; Xiuyu ; et al. | 2016-10-06 |
Finfets Having Strained Channels, And Methods Of Fabricating Finfets Having Strained Channels
App 20160293761 - Liu; Qing ; et al. | 2016-10-06 |
Symmetrical Extension Junction Formation With Low-k Spacer And Dual Epitaxial Process In Finfet Device
App 20160284820 - Basker; Veeraraghavan S. ; et al. | 2016-09-29 |
Macro To Monitor N-p Bump
App 20160284602 - Cai; Xiuyu ; et al. | 2016-09-29 |
Dual Channel Finfet With Relaxed Pfet Region
App 20160284607 - Cai; Xiuyu ; et al. | 2016-09-29 |
Buried Source-drain Contact For Integrated Circuit Transistor Devices And Method Of Making Same
App 20160284599 - Liu; Qing ; et al. | 2016-09-29 |
Method Of Forming Epitaxial Buffer Layer For Finfet Source And Drain Junction Leakage Reduction
App 20160284701 - GUO; DECHAO ; et al. | 2016-09-29 |
Method For Making A Semiconductor Device With Sidewal Spacers For Confinig Epitaxial Growth
App 20160284822 - Cai; Xiuyu ; et al. | 2016-09-29 |
Method Of Forming Epitaxial Buffer Layer For Finfet Source And Drain Junction Leakage Reduction
App 20160276463 - GUO; DECHAO ; et al. | 2016-09-22 |
Finfet Including Tunable Fin Height And Tunable Fin Width Ratio
App 20160276348 - Cai; Xiuyu ; et al. | 2016-09-22 |
Semiconductor Devices Having Fins, And Methods Of Forming Semiconductor Devices Having Fins
App 20160260741 - Liu; Qing ; et al. | 2016-09-08 |
Finfet Having Controlled Dielectric Region Height
App 20160254178 - Guo; Dechao ; et al. | 2016-09-01 |
Silicon Nitride Fill For Pc Gap Regions To Increase Cell Density
App 20160218102 - Guo; Dechao ; et al. | 2016-07-28 |
Anchored Stress-generating Active Semiconductor Regions For Semiconductor-on-insulator Finfet
App 20160218198 - Basker; Veeraraghavan S. ; et al. | 2016-07-28 |
Implantation Formed Metal-insulator-semiconductor (mis) Contacts
App 20160211342 - Chen; Chia-Yu ; et al. | 2016-07-21 |
Implantation Formed Metal-insulator-semiconductor (mis) Contacts
App 20160211343 - Chen; Chia-Yu ; et al. | 2016-07-21 |
Implantation Formed Metal-insulator-semiconductor (mis) Contacts
App 20160211340 - Chen; Chia-Yu ; et al. | 2016-07-21 |
Self-aligned Contact Process Enabled By Low Temperature
App 20160204257 - HE; Hong ; et al. | 2016-07-14 |
Semiconductor Device With Different Fin Sets
App 20160197072 - Liu; Qing ; et al. | 2016-07-07 |
Large Area Contacts For Small Transistors
App 20160190322 - LIU; Qing ; et al. | 2016-06-30 |
Vertical Slit Transistor With Optimized Ac Performance
App 20160190314 - Liu; Qing ; et al. | 2016-06-30 |
Hetero-channel Finfet
App 20160190317 - LIU; Qing ; et al. | 2016-06-30 |
High-reliability, Low-resistance Contacts For Nanoscale Transistors
App 20160190325 - LIU; Qing ; et al. | 2016-06-30 |
Semiconductor Devices Having Low Contact Resistance And Low Current Leakage
App 20160181390 - LIU; Qing ; et al. | 2016-06-23 |
Trench Epitaxial Growth For A Finfet Device Having Reduced Capacitance
App 20160181381 - Liu; Qing ; et al. | 2016-06-23 |
Reduced Trench Profile For A Gate
App 20160181384 - LIU; Qing ; et al. | 2016-06-23 |
Low-drive Current Finfet Structure For Improving Circuit Density Of Ratioed Logic In Sram Devices
App 20160181256 - Basker; Veeraraghavan S. ; et al. | 2016-06-23 |
Low-drive Current Finfet Structure For Improving Circuit Density Of Ratioed Logic In Sram Devices
App 20160181254 - Basker; Veeraraghavan S. ; et al. | 2016-06-23 |
| 