U.S. patent application number 14/828946 was filed with the patent office on 2017-02-23 for semiconductor device and manufacturing method thereof.
The applicant listed for this patent is TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.. Invention is credited to HSIEN-WEI CHEN, LI-HSIEN HUANG, LIN-CHIH HUANG, AN-JHIH SU, TIEN-CHUNG YANG.
Application Number | 20170053812 14/828946 |
Document ID | / |
Family ID | 57908896 |
Filed Date | 2017-02-23 |
United States Patent
Application |
20170053812 |
Kind Code |
A1 |
YANG; TIEN-CHUNG ; et
al. |
February 23, 2017 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Abstract
A semiconductor device includes a semiconductor substrate, a
conductive pad on the semiconductor substrate, and a conductor over
the conductive pad. The semiconductor device further has a
polymeric material disposed over the semiconductor substrate and
surrounding the conductor. The semiconductor device also includes
an electric conductive layer between the conductor and the
polymeric material. In the semiconductor device, an adhesion
strength between the electric conductive layer and the polymeric
material is greater than an adhesion strength between the polymeric
material and the conductor.
Inventors: |
YANG; TIEN-CHUNG; (HSINCHU,
TW) ; HUANG; LIN-CHIH; (HSINCHU CITY, TW) ;
CHEN; HSIEN-WEI; (HSINCHU CITY, TW) ; SU;
AN-JHIH; (TAOYUAN COUNTY, TW) ; HUANG; LI-HSIEN;
(HSINCHU COUNTY, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. |
Hsinchu |
|
TW |
|
|
Family ID: |
57908896 |
Appl. No.: |
14/828946 |
Filed: |
August 18, 2015 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 24/29 20130101;
H01L 2224/11602 20130101; H01L 2224/81416 20130101; H01L 2224/12105
20130101; H01L 24/11 20130101; H01L 24/19 20130101; H01L 2224/94
20130101; H01L 2924/18162 20130101; H01L 2224/05647 20130101; H01L
2224/133 20130101; H01L 2224/04105 20130101; H01L 2224/13199
20130101; H01L 2224/11013 20130101; H01L 2224/16227 20130101; H01L
2224/81411 20130101; H01L 24/13 20130101; H01L 2224/13005 20130101;
H01L 2224/81455 20130101; H01L 24/94 20130101; H01L 2225/1035
20130101; H01L 23/49894 20130101; H01L 24/05 20130101; H01L
2021/60022 20130101; H01L 23/4824 20130101; H01L 23/49866 20130101;
H01L 2224/05613 20130101; H01L 2224/81413 20130101; H01L 24/97
20130101; H01L 2224/73204 20130101; H01L 2224/0391 20130101; H01L
21/568 20130101; H01L 23/49811 20130101; H01L 24/03 20130101; H01L
2224/02166 20130101; H01L 2224/10126 20130101; H01L 2225/1058
20130101; H01L 21/78 20130101; H01L 23/485 20130101; H01L 2224/131
20130101; H01L 24/73 20130101; H01L 2224/11466 20130101; H01L
2224/81447 20130101; H01L 21/561 20130101; H01L 2224/05639
20130101; H01L 2224/81439 20130101; H01L 21/56 20130101; H01L 24/10
20130101; H01L 2224/0401 20130101; H01L 23/3128 20130101; H01L
2224/05611 20130101; H01L 2224/05616 20130101; H01L 2224/11462
20130101; H01L 21/486 20130101; H01L 24/20 20130101; H01L
2224/13026 20130101; H01L 21/565 20130101; H01L 23/3114 20130101;
H01L 2224/05655 20130101; H01L 2224/94 20130101; H01L 2224/03
20130101; H01L 2224/81416 20130101; H01L 2924/014 20130101; H01L
2924/00014 20130101; H01L 2224/05655 20130101; H01L 2924/014
20130101; H01L 2924/00014 20130101; H01L 2224/05616 20130101; H01L
2924/014 20130101; H01L 2924/00014 20130101; H01L 2224/131
20130101; H01L 2924/014 20130101; H01L 2924/00014 20130101; H01L
2224/13199 20130101; H01L 2924/00014 20130101; H01L 2224/81455
20130101; H01L 2924/014 20130101; H01L 2924/00014 20130101; H01L
2224/133 20130101; H01L 2924/00014 20130101; H01L 2224/81413
20130101; H01L 2924/014 20130101; H01L 2924/00014 20130101; H01L
2224/81411 20130101; H01L 2924/014 20130101; H01L 2924/00014
20130101; H01L 2224/81439 20130101; H01L 2924/014 20130101; H01L
2924/00014 20130101; H01L 2224/81447 20130101; H01L 2924/014
20130101; H01L 2924/00014 20130101; H01L 2224/05639 20130101; H01L
2924/014 20130101; H01L 2924/00014 20130101; H01L 2224/05613
20130101; H01L 2924/014 20130101; H01L 2924/00014 20130101; H01L
2224/05611 20130101; H01L 2924/014 20130101; H01L 2924/00014
20130101; H01L 2224/05647 20130101; H01L 2924/014 20130101; H01L
2924/00014 20130101 |
International
Class: |
H01L 21/48 20060101
H01L021/48; H01L 21/56 20060101 H01L021/56; H01L 23/498 20060101
H01L023/498; H01L 21/78 20060101 H01L021/78 |
Claims
1. A semiconductor device, comprising: a semiconductor substrate; a
conductive pad on the semiconductor substrate; a conductor over the
conductive pad; a polymeric material over the semiconductor
substrate and surrounding the conductor; an electric conductive
layer between the conductor and the polymeric material, and an
oxide compound of an element of the electric conductive layer,
wherein the oxide compound is between the electric conductive layer
and the polymeric material and the element tends to grab oxygen
atoms from the polymeric material more aggressively than the
conductor.
2. The semiconductor device of claim 1, wherein the electric
conductive layer is configured as a seed layer for the
conductor.
3. The semiconductor device of claim 1, wherein the spacing between
the conductor and an adjacent conductor is less than about 10
um.
4. The semiconductor device of claim 1, wherein the electric
conductive layer includes a first layer and a second layer, the
first layer is adjacent to the polymeric material, and the second
layer is adjacent to the conductor.
5. (canceled)
6. The semiconductor device of claim 4, wherein the second layer is
made with the same material as the conductor but with a different
micro structure.
7. The semiconductor device of claim 4, wherein a thickness of the
first layer is substantially greater than 50 nm, and a thickness of
the second layer is substantially greater than 100 nm.
8. The semiconductor device of claim 4, wherein the second layer
and the conductor are substantially made with a same material but
with different grain size.
9-20. (canceled)
21. The semiconductor device of claim 1, wherein the element has a
different standard electrode potential than the conductor.
22. The semiconductor device of claim 4, wherein a standard
electrode potential ratio between the first layer and the conductor
is between about 2.1 and about 7.5.
23. The semiconductor device of claim 1, wherein the electric
conductive layer has a width of about 150 nm to about 250 nm.
24. The semiconductor device of claim 4, wherein a ratio of atomic
weight between the first layer and the second layer is from about
0.6 to about 1.3.
25. The semiconductor device of claim 4, wherein the first layer
has a thickness substantially less than a thickness of the second
layer.
26. The semiconductor device of claim 4, wherein a ratio of a
thickness between the first layer and the second layer is about 1:1
to 1:3.
27. The semiconductor device of claim 1, wherein the polymeric
material includes a recess for receiving the conductor.
28. The semiconductor device of claim 1, wherein the electric
conductive layer is a composite structure including several
conductive layers.
29. The semiconductor device of claim 1, wherein the electric
conductive layer is surrounding the conductor.
30. The semiconductor device of claim 1, wherein the polymeric
material comprises a viscosity greater than about 1 Pas.
31. A semiconductor device, comprising: a semiconductor substrate;
a conductive pad on the semiconductor substrate; a conductor over
the conductive pad; a polymeric material over the semiconductor
substrate and surrounding the conductor; and an electric conductive
layer surrounding the conductor; wherein a quantitative interfacial
energy between the electric conductive layer and the polymeric
material is greater than a quantitative interfacial energy between
the polymeric material and the conductor, wherein the conductor,
the polymeric material and the electric conductive layer are
substantially coplanar.
32. The semiconductor device of claim 31, wherein the electric
conductive layer forms a multi-layer structure.
33. The semiconductor device of claim 1, wherein an adhesion
strength between the electric conductive layer and the polymeric
material is greater than an adhesion strength between the polymeric
material and the conductor.
Description
PRIORITY CLAIM AND CROSS-REFERENCE
[0001] The disclosure relates to a semiconductor device and a
method of manufacturing a semiconductor device.
BACKGROUND
[0002] Electronic equipments involving semiconductor devices are
indispensable from our daily life. With the advancement of
electronic technology, electronic equipments become more
complicated and involve greater amount of integrated circuitry for
executing the desired multi-functionality. Thus, manufacturing of
the electronic equipments includes more and more steps of assembly
and processing as well as materials for producing the semiconductor
devices in the electronic equipments. Therefore, there is a
continuous demand on simplifying the steps of production,
increasing production efficiency and lowering associated
manufacturing cost on each electronic equipment.
[0003] During the operations of manufacturing the semiconductor
devices, the semiconductor devices are assembled with numbers of
integrated components including various materials with difference
in thermal properties. As such, the integrated components are in
undesired configurations. The undesired configurations would lead
to yield loss of the semiconductor devices, poor bondability
between the components, development of cracks, delamination of the
components or etc. Furthermore, the components of the semiconductor
devices include various metallic materials which are in limited
quantity and thus in a high cost. The undesired configurations of
the components and the yield loss of the semiconductor devices
would further exacerbate materials wastage and thus the
manufacturing cost would increase.
[0004] As more different components with different materials are
involved and a complexity of the manufacturing operations of the
semiconductor device is increased, there are more challenges to
modify a structure of the semiconductor device and improve the
manufacturing operations. As such, there is a continuous need to
improve the method for manufacturing the semiconductor and solve
the above deficiencies.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] Aspects of the present disclosure are best understood from
the following detailed description when read with the accompanying
figures. It is noted that, in accordance with the standard practice
in the industry, various features are not drawn to scale. In fact,
the dimensions of the various features may be arbitrarily increased
or reduced for clarity of discussion.
[0006] FIG. 1 a schematic view of a semiconductor device in
accordance with some embodiments.
[0007] FIG. 2 is an enlarged view of a portion of a semiconductor
device in FIG. 1 in accordance with some embodiments.
[0008] FIG. 3A is a schematic view of a semiconductor device with a
semiconductor substrate in accordance with some embodiments.
[0009] FIG. 3B is a schematic view of a semiconductor device with a
conductive pad in accordance with some embodiments.
[0010] FIG. 3C is a schematic view of a semiconductor device with a
passivation in accordance with some embodiments.
[0011] FIG. 3D is a schematic view of a semiconductor device with a
polymeric material in accordance with some embodiments.
[0012] FIG. 3E is a schematic view of a semiconductor device with
an electric conductive layer in accordance with some
embodiments.
[0013] FIG. 3F is a schematic view of a semiconductor device with a
conductor in accordance with some embodiments.
[0014] FIG. 3G is a schematic view of a semiconductor device with
singulated die in accordance with some embodiments.
[0015] FIG. 3H is a schematic view of a semiconductor device with a
carrier and molding in accordance with some embodiments.
[0016] FIG. 3I is a schematic view of a semiconductor device with
redistribution layers, polymers, and a bond pad in accordance with
some embodiments.
[0017] FIG. 3J is a schematic view of a semiconductor device with a
bump in accordance with some embodiments.
[0018] FIG. 3K is a schematic view of a semiconductor device
without a carrier bonding with another die or another package in
accordance with some embodiments.
DETAILED DESCRIPTION
[0019] The following disclosure provides many different
embodiments, or examples, for implementing different features of
the provided subject matter. Specific examples of components and
arrangements are described below to simplify the present
disclosure. These are, of course, merely examples and are not
intended to be limiting. For example, the formation of a first
feature over or on a second feature in the description that follows
may include embodiments in which the first and second features are
formed in direct contact, and may also include embodiments in which
additional features may be formed between the first and second
features, such that the first and second features may not be in
direct contact. In addition, the present disclosure may repeat
reference numerals and/or letters in the various examples. This
repetition is for the purpose of simplicity and clarity and does
not in itself dictate a relationship between the various
embodiments and/or configurations discussed.
[0020] Further, spatially relative terms, such as "beneath,"
"below," "lower," "above," "upper" and the like, may be used herein
for ease of description to describe one element or feature's
relationship to another element(s) or feature(s) as illustrated in
the figures. The spatially relative terms are intended to encompass
different orientations of the device in use or operation in
addition to the orientation depicted in the figures. The apparatus
may be otherwise oriented (rotated 90 degrees or at other
orientations) and the spatially relative descriptors used herein
may likewise be interpreted accordingly.
[0021] FIG. 1 is an embodiment of a semiconductor device 100 and
100a is a portion of the semiconductor device 100 in FIG. 1. FIG. 2
is an enlarged view of 100a. Semiconductor device 100a includes a
semiconductor substrate 102. In some embodiments, the semiconductor
substrate 102 includes semiconductor materials such as silicon, and
is fabricated with a predetermined functional circuit within the
semiconductor substrate 102 produced by various operations such as
photolithography, etch, deposition, plating, etc. In some
embodiments, the semiconductor substrate 102 is singulated from a
silicon wafer by a mechanical or laser blade. In some embodiments,
the semiconductor substrate 102 is in a quadrilateral, a
rectangular or a square shape.
[0022] The semiconductor substrate 102 includes a surface 102b and
a conductive pad 102a is disposed on the surface 102b. In some
embodiments, the conductive pad 102a is electrically connected with
a circuitry external to the semiconductor substrate 102, so that a
circuitry internal to the semiconductor substrate 102 electrically
connects with the circuitry external to the semiconductor substrate
102 through the conductive pad 102a. In some embodiments, the
conductive pad 102a is configured for electrically coupling with a
conductive bump through a conductive trace attached on the
conductive pad 102a, so that the circuitry internal to the
semiconductor substrate 102 connects with the circuitry external to
the semiconductor substrate 102 from the conductive pad 102a to the
conductive bump through the conductive trace. In some embodiments,
the conductive pad 102a includes gold, silver, copper, nickel,
tungsten, aluminum, palladium and/or alloys thereof.
[0023] In some embodiments, a passivation 103 is disposed on the
surface 102b of the semiconductor substrate 102 and over the
conductive pad 102a. In some embodiments, the passivation 103
surrounds the conductive pad 102a. In some embodiments, the
passivation 103 partially covers a top surface 102c of the
conductive pad 102a. The passivation 103 is configured for
providing an electrical insulation and a moisture protection for
the semiconductor substrate 102, so that the semiconductor
substrate 102 is isolated from ambient environment. In some
embodiments, the passivation 103 is formed with dielectric
materials such as spin-on glass (SOG), silicon oxide, silicon
oxynitride, silicon nitride or the like. In some embodiments, the
passivation 103 is formed with a vapor deposition or a spin coating
process.
[0024] In some embodiments, the passivation 103 includes an opening
103a above the conductive pad 102a for exposing a portion of the
top surface 102c of the conductive pad 102a and thus for
electrically connecting the conductive pad 102a with the circuitry
external to the semiconductor substrate 102 through the conductive
trace.
[0025] In some embodiments, several conductors 104 are disposed
over the top surface 102c of the conductive pad 102a as in FIG. 1
with a spacing W being less than about 10 um. In some embodiments,
each conductor 104 is on an exposed portion of the top surface 102c
and a portion of the passivation 103 adjacent to the opening 103a.
The conductor 104 is extended from the exposed portion of the top
surface 102c to a top surface 104a of the conductor 104 as in FIG.
2. In some embodiments, the conductor 104 is extended along a
normal direction of the surface 102b. In some embodiments, the
conductor 104 is substantially upright and supported by the
conductive pad 102a.
[0026] In some embodiments, the conductor 104 is in a cylindrical
shape with various cross-sectional shapes such as circular shape,
quadrilateral shape or polygonal shape. In addition, a wide variety
of materials is selected for the conductor 104 such as metal or
metal alloy. In some embodiments, the conductor 104 includes copper
(Cu), gold (Au), platinum (Pt), titanium (Ti), nickel (Ni),
aluminum (Al), etc.
[0027] In some embodiments, a polymeric material 105 is disposed
over the passivation 103 and surrounding the conductor 104. The
polymeric material 105 is a dielectric filling inserted around the
conductor 104 in order to isolate adjacent conductors or avoid
moisture attack. In some embodiments, the polymeric material 105
includes a material such as epoxy, polyimide, polybenzoxazole
(PBO), solder resist (SR), ABF film, and the like. In some
embodiments, the conductor 104 and polymeric material 105 are
substantially coplanar.
[0028] In some embodiments, an electric conductive layer 106 is
disposed between the conductor 104 and the polymeric material 105.
The electric conductive layer 106 is a layer may be substantially
thinner than the conductor 104 and is extended along a longitudinal
sidewall of the conductor 104. In FIG. 2, the longitudinal sidewall
is defined as the surface extends along the normal direction of the
surface 102b. The electric conductive layer 106 is sandwiched by
the conductor 104 and the polymeric material 105 so as to form a
barrier to prevent a direct contact between the conductor 104 and
the polymeric material 105. The electric conductive layer 106 is a
continuous film and surrounds the longitudinal sidewall of
conductor 104 as the polymeric material 105. In some embodiment,
the electric conductive layer 106 includes an element which has at
least a different physical or chemical property than the conductor
104.
[0029] In some embodiment, the electric conductive layer 106
includes an element having a different standard electrode potential
than the conductor 104. In some embodiments, the electric
conductive layer 106 includes an element tending to grab the oxygen
atoms from the polymeric material 105 more aggressively than the
conductor 104. An oxide compound of the element may form between
the electric conductive layer 106 and the polymeric material 105.
The oxide compound provides a glue to further bond the conductor
104 and the polymeric material 105 in a more secured way. The
electric conductive layer 106 also includes an element which may
forms a coherent layer between the electric conductive layer 106
and the conductor 104. In order to possess two different
characteristics, the electric conductive layer 106 may be a
composite structure including several conductive layers.
[0030] As in FIG. 2, the electric conductive layer 106 includes at
least two layers, layer 106a and layer 106b. The layer 106a is more
adjacent to the polymeric material 105 comparing to layer 106b and
the layer 106a serves the element to form the oxide compound
between the electric conductive layer 106 and the polymeric
material 105. The layer 106b is more adjacent to the conductor 104
comparing to layer 106a and layer 106b serves the element to form
the coherent layer.
[0031] In some embodiment, the standard electrode potential ratio
between layer 106a and conductor 104 is between about 2.1 and about
7.5. In some embodiment, the standard electrode potential ratio
between layer 106a and conductor 104 is between about 4.0 and about
5.0. In some embodiment, the standard electrode potential ratio
between layer 106a and conductor 104 is between about 4.3 and about
4.7. The layer 106a may include element such as, Ti, Cr, Al,
doped-Si, Zr, Th, Ni, etc.
[0032] In some embodiment, the standard electrode potential ratio
between layer 106b and conductor 104 is between about 0.85 and
about 1.35. In some embodiment, the standard electrode potential
ratio between layer 106b and conductor 104 is between about 0.91
and about 1.07. The layer 106b may include element such as, Pt, Au,
Ag, Cu, etc.
[0033] In some embodiments, the electric conductive layer 106b
includes an element having a an adhesion strength between the
electric conductive layer 106 and the polymeric material 105
greater than an adhesion strength between the polymeric material
105 and the conductor 104. In some embodiments, the adhesion
strength may be referred to as a quantitative interfacial energy.
The quantitative interfacial energy defines as the quantitative
energy value of two specific substances. The magnitude of the value
represents the adhesion strength between the two specific
substances. Higher quantitative interfacial energy indicates that a
greater adhesion strength between the two specific substances.
[0034] In the present disclosure, the conductive layer 106 acts as
a reinforce structure between conductor 104 and polymeric material
105. The conductive layer 106 possesses a quantitative interfacial
energy higher than the quantitative interfacial energy between the
polymeric material 105 and the conductor 104. The inserted
conductive layer 106 separates the conductor 104 from directly
contacting the polymeric material 105; therefore a delamination
between the conductor 104 and polymeric material 105 is prevented.
In some embodiments, the adhesion strength between layer 106a and
polymeric material 105 may be greater than the adhesion strength
between layer 106b and polymeric material 105.
[0035] In some embodiments, a ratio of atomic weight between layer
106a and layer 106b may be about 0.6 to about 1.3. In some
embodiments, a ratio of atomic weight between layer 106a and layer
106b is about 0.65 to about 0.9. In some embodiments, a ratio of
atomic weight between layer 106a and layer 106b is about 0.70 to
about 0.85.
[0036] In some embodiments, a ratio of atomic weight between the
layer 106b and the conductor 104 may be about 0.8 to about 1.2. In
some embodiments, a ratio of atomic weight between the layer 106b
and the conductor 104 may be about 0.9 to about 1.1. In some
embodiments, a ratio of atomic weight between the layer 106b and
the conductor 104 may be about 0.95 to about 1.05. In some
embodiments, the layer 106b may be made with a same material as the
conductor 104 but with different micro structure, such as crystal
orientation, or grain size. In some embodiments, the grain size of
the layer 106b may be greater than the grain size of the conductor
104. In some embodiments, thickness of the 106a is substantially
greater than 50 nm, and thickness of layer 106b is substantially
greater than 100 nm. In some embodiments, a ratio of the thickness
between the layer 106a and the layer 106b may be about 1:1 to
1:3.
[0037] The electric conductive layer 106 may be further extended
under the bottom surface of the conductor 104. In some embodiments,
a portion of the electric conductive layer 106 is disposed between
the conductive pad 102a and the conductor 104. In some embodiments,
the electric conductive layer 106 is disposed between the
passivation 103 and the conductor 104. In some embodiments, the
electric conductive layer 106 is a continuous film surrounding the
conductor 104. In some embodiments, the electric conductive layer
106 has a width of about 150 nm to about 250 nm. In some
embodiments, a wide variety of materials is selected for the
electric conductive layer 106 such as metal or metal alloy.
[0038] In some embodiments, a molding 107 is disposed to surround
the semiconductor substrate 102. In some embodiments, the molding
107 is disposed adjacent to a sidewall 102d of the semiconductor
substrate 102. In some embodiments, top surfaces of the conductor
104, polymeric material 105 and the molding 107 are substantially
coplanar.
[0039] In some embodiments, the semiconductor device 100 includes a
polymer 109 disposed over the molding 107, the conductor 104 and
the polymeric material 105. A recessed portion 118 of the polymer
109 is formed above the top surface 104a of the conductor 104 as in
FIG. 2. In some embodiments, the semiconductor device 100 further
includes a first redistribution layer (RDL) 112 disposed on the
conductor 104 and polymer 109 as in FIG. 2. In some embodiments,
the semiconductor device 100 further includes a polymer 110
disposed over the polymer 109 and the first redistribution layer
112 as in FIG. 2. In some embodiments, the semiconductor device 100
further includes a via 117 formed above an end portion 112b of the
first redistribution layer 112, and a bond pad 114 is disposed on
the polymer 110 and first redistribution layer 112 as in FIG. 2. In
some embodiments, the semiconductor device 100 further includes a
bump 115 disposed on the bond pad 114 as in FIG. 2.
[0040] FIG. 3A-FIG. 3K is an embodiment of a method of
manufacturing a semiconductor device. The method includes a number
of operations (201, 202, 203, 204, 205, 206, 207, 208, 209, 210,
and 211).
[0041] In operation 201, a semiconductor substrate 102 is provided
as in FIG. 3A. In some embodiments, the semiconductor substrate 102
includes semiconductor material such as silicon. In operation 202,
a conductive pad 102a is formed on the semiconductor substrate 102
as in FIG. 3B. In some embodiments, the conductive pad 102a is
disposed on a surface 102b of the semiconductor substrate 102.
[0042] In operation 203, a passivation 103 is disposed over the
semiconductor substrate 102, and some of the passivation 103 is
removed to form an opening 103a as in FIG. 3C. In some embodiments,
some of the passivation 103 above a top surface 102c of the
conductive pad 102a is removed by etching operations to expose the
top surface 102c of the conductive pad 102a and form the opening
103a. In some embodiments, the opening 103a is extended from a top
surface 103b of the passivation 103 to the top surface 102c of the
conductive pad 102a.
[0043] In operation 204, a polymeric material 105 is disposed over
conductive pad 102a and the passivation 103, and the polymeric
material 105 is patterned with an opening 105a above the conductive
pad 102a as in FIG. 3D. In some embodiments, the width of the
opening 105a is between about 10 um and about 100 um. The polymeric
material 105 is patterned to provide a path for a conductive
material or conductive trace passing through. In some embodiments,
the polymeric material 105 is patterned to form the opening 105a by
photolithography, and several polymeric blocks are formed as FIG.
3D. The spacing between adjacent polymeric blocks may be 40 um to
100 um. In some embodiments, a photoresist material is disposed to
cover the polymeric material 105, and then the photoresist material
is partially exposed through a photomask in order to etch away
those polymeric material 105 adjacent to or over the conductive pad
102a, so that the opening 105a is formed above the conductive pad
102a.
[0044] In operation 205, the conductive pad 102a, the passivation
103 and the polymeric material 105 are surrounded with an electric
conductive layer 106 as in FIG. 3E. In some embodiments, the
electric conductive layer 106 is disposed by electroplating or
deposition. In some embodiments, the electric conductive layer 106
is formed by sputtering and configured as a seed layer for the
conductor. The electric conductive layer 106 is a thin film to be
disposed inside the opening 105a and lines along the exposed
surfaces of the opening 105a. A portion of the electric conductive
layer 106 also covers the conductive pad 102a. The forming
operation of the electric conductive layer 106 may further include
two sub-operations to form layers 106a and 106b in FIG. 2
separately. Layers 106a and 106b may be formed in-situ or
independently, and the micro structure between these two layers are
distinguishable under analysis tools like TEM (Transmission
Electron Microscope) or SEM (Scanning Electron Microscope).
[0045] In operation 206, a conductor 104 is disposed over and
adjacent to the electric conductive layer 106 as in FIG. 3F.
Because the conductor 104 is formed after the opening 105a is
defined, the spacing W of the conductors can be determined by the
width and spacing of the polymeric material 105. The advantage to
perform a filling-first (forming the pattern of polymeric material
before forming the conductor 104) operation is to ensure the gap
filling quality between adjacent conductors 104. The filling-first
operation can satisfy the requirement for small spacing conductor,
for example, when W is less than 10 um. The polymeric material 105
used as a conductor gap filling may have viscosity range from 1 to
1000 Pas. If the polymeric material 105 is filled into the
conductor gap after the formation of small spacing conductors, the
flow resistance of the polymeric material 105 may lead to a poor
gap filling, such as voids, between the conductors. The poor gap
filling quality does not only an issue for visual defect; it also
contributes to some fatal reliability failures. The filling-first
operation disclosed in the present disclosure provides a solution
to eliminate the undesired poor gap filling issue. Because the
polymeric material 105 is blanket coated over the semiconductor
substrate prior to forming any uneven surface features (such as
conductor array), the gap filling capability of the polymeric
material 105 becomes insignificant to the device defect and
reliability quality. It should be also appreciated that since the
opening 105a is formed by a photolithography operation, the
dimension for the opening 105a (for a conductor 104 to be disposed
therein) can be reduced with the advanced exposure technology.
Therefore, a small spacing conductor 104 (W<10 um) requirement
can be satisfied by the filling-first operation. In some
embodiments, the conductor 104 is disposed by various methods such
as electroplating, sputtering or etc. In some embodiments, the
conductor 104 includes a metal such as copper.
[0046] In operation 207, the semiconductor substrate 102 is
singulated into several individual dies 108 as in FIG. 3G. In some
embodiments, the semiconductor substrate 102 is singulated by a
mechanical or laser blade.
[0047] In operation 208, the die 108 singulated from the
semiconductor substrate 102 is placed on a carrier 116. A molding
107 is disposed on the carrier 116 to surround the die 108. A
removal or planarization operation is introduced to remove a
portion of the molding 107 in order to expose the top surface 104a
of the conductor 104 and a top surface 105b of the polymeric
material 105, such that there is no molding 107 remaining on the
conductor 104 and the polymeric material. FIG. 3H is an embodiment
showing the structure after the removal operation. In some
embodiments, the top portion of the molding 107, the conductor 104,
and the electric conductive layer 106 are concurrently removed by
an operation such as etching or grinding in order to be
coplanar
[0048] In operation 209, a polymer 109 is disposed over molding
107, the conductor 104 and the polymeric material 105 as in FIG.
3I. In some embodiments, the polymer 109 includes a polymeric
material such as epoxy, polyimide, polybenzoxazole (PBO), solder
resist (SR), ABF film, and the like.
[0049] A recessed portion 118 is formed above the top surface 104a
of the conductor 104 as in FIG. 3I. In some embodiments, some of
the polymer 109 above the top surface 104a are removed by
photolithography.
[0050] A first redistribution layer (RDL) 112 is disposed as in
FIG. 3I. In some embodiments, the first RDL 112 is disposed on the
polymer 109 by electroplating or sputtering. In some embodiments,
the first RDL 112 includes an extended portion 112a extending from
the top surface 109a of the polymer 109 to the top surface 104a of
the conductor 104. The extended portion 112a is disposed along the
recessed portion 118. The first RDL 112 is electrically connected
with the conductor 104 through the top surface 104a and the
extended portion 112a.
[0051] A polymer 110 is disposed as in FIG. 3I. In some
embodiments, the polymer 110 is disposed on the first RDL 112. The
polymer 110 covers the top of the semiconductor device 100. In some
embodiments, the polymer 110 includes a polymeric material such as
epoxy, polyimide, polybenzoxazole (PBO), solder resist (SR), ABF
film, and the like.
[0052] A via 117 is formed and a bond pad 114 is disposed as in
FIG. 3I. In some embodiments, the via 117 is formed by removing
some of the polymer 110 above the first RDL 112. In some
embodiments, some of the polymer 110 is removed by photolithography
to form the via 117. In some embodiments, the via 117 is in a
tapered configuration. In some embodiments, the via 117 is extended
from a top surface 110a of the polymer 110 to an end portion 112b
of the first RDL 112.
[0053] In some embodiments, the bond pad 114 is formed above the
end portion 112b of the first RDL and the polymer 110. In some
embodiments, the bond pad 114 fills the via 117 and extends from
the top surface 110a of the polymer 110 to the end portion 112b of
the first RDL, so that the bond pad 114 is electrically connected
with the first RDL 112. In some embodiments, the bond pad 114 is an
under bump metallurgy (UBM) pad which is a solderable surface for
receiving a bump and electrically connecting the bond pad 114 with
the circuitry external to the die 108.
[0054] In operation 210, a bump 115 is disposed on the bond pad 114
as in FIG. 3J. In some embodiments, the bump 115 is a solder bump,
solder ball, solder paste or etc. In some embodiments, the bump 115
is configured for attaching with a pad on another die, another
substrate or another semiconductor package. In some embodiments,
the bump 115 is a conductive bump or a conductive joint. In some
embodiments, the conductive pad 102a is electrically connected with
the bump 115 through the conductor 104, the first RDL 112 and the
bond pad 114.
[0055] In operation 211, the carrier 101 is removed from the
semiconductor device 100 as in FIG. 3K. In some embodiments, the
semiconductor device 100 is detached from the carrier 101 for
subsequent operations.
[0056] The structure shown in FIG. 3J is flipped upside down and
attached to another substrate 120 at the bottom of FIG. 3K. The
substrate 120 may be a package substrate, board (e.g., a printed
circuit board (PCB)), a wafer, a die, an interposer substrate, or
other suitable substrate. The bump structure is coupled to the
substrate 120 through various conductive attachment points. For
example, a conductive region 122 is formed and patterned on the
substrate 120. The conductive region 122 is a contact pad or a
portion of a conductive trace, which is presented by a mask layer
124. In one embodiment, the mask layer 124 is a solder resist layer
formed and patterned on the substrate 120 to expose the conductive
region 122. The mask layer 124 has a mask opening, which provides a
window for solder joint formation. For example, a solder layer
including alloys of tin, lead, silver, copper, nickel, bismuth, or
combinations thereof may be provided on the conductive region 122.
The semiconductor device 100 can be coupled to the substrate 120
through a joint solder structure 126 between the bond pad 114 and
the conductive region 122. An exemplary coupling process includes a
flux application, chip placement, reflowing of melting solder
joints, and/or cleaning of flux residue. The semiconductor
substrate 102, the joint solder structure 126, and the other
substrate 120 may be referred to as a packaging assembly, or in the
present embodiment, a flip-chip packaging assembly.
[0057] In some embodiments, the semiconductor device 100 is bonded
with another package by a package bump to become a package on
package (PoP). In some embodiments, the semiconductor device 100 is
electrically connected with another package through the package
bump. In some embodiments, several conductive members of the
semiconductor device 100 are correspondingly bonded with several
package pads of another package through several package bumps to
become PoP.
[0058] In some embodiments, a semiconductor device includes a
semiconductor substrate, a conductive pad on the semiconductor
substrate, and a conductor over the conductive pad. The
semiconductor device further has a polymeric material disposed over
the semiconductor substrate and surrounding the conductor. The
semiconductor device also includes an electric conductive layer
between the conductor and the polymeric material. In the
semiconductor device, an adhesion strength between the electric
conductive layer and the polymeric material is greater than an
adhesion strength between the polymeric material and the
conductor.
[0059] In some embodiments, the electric conductive layer is
configured as a seed layer for the conductor. In some embodiments,
the spacing between the conductor and an adjacent conductor is less
than about 10 um. In some embodiments, the electric conductive
layer includes a first layer and a second layer, the first layer is
adjacent to the polymeric material, and the second layer is
adjacent to the conductor. In some embodiments, a ratio of atomic
weight between the first layer and the second layer is about 0.6 to
about 1.3. In some embodiments, a ratio of atomic weight between
the second layer and the conductor is about 0.8 to about 1.2. In
some embodiments, a thickness of the first layer is substantially
greater than 50 nm, and a thickness of the second layer is
substantially greater than 100 nm. In some embodiments, the second
layer and the conductor is substantially made with a same material
but with different grain size.
[0060] In some embodiments, a semiconductor device includes a
semiconductor substrate, a conductive pad on the semiconductor
substrate, and a conductor over the conductive pad. The
semiconductor device further has a polymeric material disposed over
the semiconductor substrate and surrounding the conductor. The
semiconductor device also includes an electric conductive layer
between the conductor and the polymeric material. In the
semiconductor device, the electric conductive layer includes an
element having a different standard electrode potential than the
conductor.
[0061] In some embodiments, the element has a lower standard
electrode potential than the conductor. In some embodiments, an
oxide compound of the element is between the electric conductive
layer and the polymeric material. In some embodiments, the electric
conductive layer is a composite structure including several
conductive layers. In some embodiments, the electric conductive
layer includes a first layer and a second layer, the first layer is
adjacent to the polymeric material, and the second layer is
adjacent to the conductor. In some embodiments, the standard
electrode potential ratio between the first layer and the conductor
is between about 2.1 and about 7.5. In some embodiments, a
thickness of the first layer is substantially greater than 50 nm,
and a thickness of the second layer is substantially greater than
100 nm.
[0062] In some embodiments, a method of manufacturing a
semiconductor device includes providing a semiconductor substrate,
forming a conductive pad on the semiconductor substrate, and
disposing a polymeric material over the semiconductor substrate.
The method further includes patterning the polymeric material to
provide an opening, forming an electric conductive layer to line in
the opening, and disposing a conductor in the opening and adjacent
to the electric conductive layer. The method also includes
disposing a molding over the semiconductor substrate, and removing
a portion of the molding to expose a top surface of the
conductor.
[0063] In some embodiments, further comprising singulating the
semiconductor substrate into a plurality of dies. In some
embodiments, forming the electric conductive layer further
comprises forming two distinguishable layers. In some embodiments,
the polymeric material comprises a viscosity greater than about 1
Pas. In some embodiments, removing a portion of the molding
includes grinding.
[0064] The foregoing outlines features of several embodiments so
that those skilled in the art may better understand the aspects of
the present disclosure. Those skilled in the art should appreciate
that they may readily use the present disclosure as a basis for
designing or modifying other processes and structures for carrying
out the same purposes and/or achieving the same advantages of the
embodiments introduced herein. Those skilled in the art should also
realize that such equivalent constructions do not depart from the
spirit and scope of the present disclosure, and that they may make
various changes, substitutions, and alterations herein without
departing from the spirit and scope of the present disclosure.
* * * * *