U.S. patent application number 14/722411 was filed with the patent office on 2015-09-10 for doping of copper wiring structures in back end of line processing.
The applicant listed for this patent is International Business Machines Corporation. Invention is credited to Thomas W. Dyer, Daniel C. Edelstein, Tze-man Ko, Andrew H. Simon, Wei-tsu Tseng.
Application Number | 20150255397 14/722411 |
Document ID | / |
Family ID | 50186351 |
Filed Date | 2015-09-10 |
United States Patent
Application |
20150255397 |
Kind Code |
A1 |
Dyer; Thomas W. ; et
al. |
September 10, 2015 |
DOPING OF COPPER WIRING STRUCTURES IN BACK END OF LINE
PROCESSING
Abstract
A method of forming a metal interconnect structure includes
forming a copper line within an interlevel dielectric (ILD) layer;
directly doping a top surface of the copper line with a copper
alloy material; and forming a dielectric layer over the ILD layer
and the copper alloy material; wherein the copper alloy material
serves an adhesion interface layer between the copper line and the
dielectric layer.
Inventors: |
Dyer; Thomas W.; (Pleasant
Valley, NY) ; Edelstein; Daniel C.; (White Plains,
NY) ; Ko; Tze-man; (Hopewell Junction, NY) ;
Simon; Andrew H.; (Fishkill, NY) ; Tseng;
Wei-tsu; (Hopewell Junction, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
International Business Machines Corporation |
Armonk |
NY |
US |
|
|
Family ID: |
50186351 |
Appl. No.: |
14/722411 |
Filed: |
May 27, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
14274962 |
May 12, 2014 |
9059177 |
|
|
14722411 |
|
|
|
|
13599256 |
Aug 30, 2012 |
8765602 |
|
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14274962 |
|
|
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Current U.S.
Class: |
257/751 |
Current CPC
Class: |
H01L 21/76886 20130101;
H01L 21/76849 20130101; H01L 21/76867 20130101; H01L 23/5329
20130101; H01L 2924/0002 20130101; H01L 23/53238 20130101; H01L
21/76873 20130101; H01L 2924/0002 20130101; H01L 2924/00 20130101;
H01L 21/76846 20130101; H01L 21/76834 20130101 |
International
Class: |
H01L 23/532 20060101
H01L023/532 |
Claims
1. A metal interconnect structure, comprising: a copper line formed
within an interlevel dielectric (ILD) layer; a barrier layer
surrounding bottom and sidewall surfaces of the copper line, with a
sidewall of the copper line having a sidewall copper alloy
concentration; a top surface of the copper line directly doped with
a copper alloy material, the top surface of the copper line having
a top copper alloy concentration; wherein the top copper alloy
concentration is greater than the sidewall copper alloy
concentration; and a dielectric layer formed over the ILD layer and
the copper alloy material.
2. The structure of claim 1, wherein: the copper alloy material
comprises a doped region of CuMn having a manganese concentration
of greater than 0.5% atomic; and the dielectric layer comprises an
NBLoK (SiC(N,H)) layer.
3. The structure of claim 1, wherein the copper line has a
thickness of about 3 microns (.mu.m).
4. The structure of claim 1, wherein: the top surface of the copper
line is directly doped with a copper alloy material comprising a
high concentration CuMn seed layer having a manganese concentration
of about 2.0% atomic; and the dielectric layer comprises NBLoK
(SiC(N,H)).
5. The structure of claim 4, wherein the copper line is formed on a
low concentration CuMn seed layer having a manganese concentration
of about 0.5% atomic or less.
Description
DOMESTIC PRIORITY
[0001] This application is a continuation of U.S. patent
application Ser. No. 14/274,962, filed May 12, 2014, which is a
divisional application of U.S. patent application Ser. No.
13/599,256, filed Aug. 30, 2012, now U.S. Pat. No. 8,765,602, the
disclosure of which is incorporated by reference herein in its
entirety.
BACKGROUND
[0002] The present disclosure relates generally to semiconductor
device manufacturing techniques and, more particularly, to doping
of copper wiring structures in back end of line (BEOL)
processing.
[0003] Integrated circuits are typically fabricated with multiple
levels of patterned metallization lines, which are electrically
separated from one another by interlayer dielectrics containing
vias at selected locations, to provide electrical connections
between levels of the patterned metallization lines. In recent
years, copper (Cu) has replaced aluminum (Al) as the metal of
choice for wiring of microelectronic devices, such as
microprocessors and memories. However, copper has a tendency to
diffuse through insulators, such as silicon dioxide, during high
temperature processes. As a result, the use of copper wiring also
necessitates the placement of efficient diffusion barriers
surrounding the copper wires, thereby keeping the copper atoms
confined to the intended wiring locations and preventing circuit
malfunctions, such as shorts.
[0004] As electronic devices become smaller, there is also a
continuing desire in the electronics industry to increase the
circuit density in electronic components, e.g., integrated
circuits, circuit boards, multi-chip modules, chip test devices,
and the like, without degrading electrical performance, e.g.,
without introducing cross-talk capacitive coupling between wires
while at the same time increasing speed or signal propagation of
these components. One method for accomplishing these goals is to
reduce the dielectric constant of the dielectric material in which
the wires are embedded. Toward this end, a new class of low
dielectric constant (low-K) materials has been created. Low-K
interlevel dielectric (ILD) materials are advantageous so long as
device reliability is not compromised. However, the lower the
dielectric constant of the low-K dielectric material, the more
challenging the integration becomes. For example, low-K generally
corresponds to lower modulus, lower thermal conductivity, increased
porosity, and greater susceptibility to plasma damage, in turn
leading to lower reliability.
SUMMARY
[0005] In an exemplary embodiment, a method of forming a metal
interconnect structure includes forming a copper line within an
interlevel dielectric (ILD) layer; directly doping a top surface of
the copper line with a copper alloy material; and forming a
dielectric layer over the ILD layer and the copper alloy material;
wherein the copper alloy material serves an adhesion interface
layer between the copper line and the dielectric layer.
[0006] In another embodiment, a method of forming a metal
interconnect structure includes forming an opening within an
interlevel dielectric (ILD) layer; forming a first seed layer in
the opening; forming a copper layer in the opening over the first
seed layer; planarizing the copper layer and the first seed layer
so as to define a copper line; directly doping a top surface of the
copper line with a copper alloy material; and forming a dielectric
layer over the ILD layer and the copper alloy material; wherein the
copper alloy material serves an adhesion interface layer between
the copper line and the dielectric layer.
[0007] In another embodiment, a metal interconnect structure
includes a copper line formed within an interlevel dielectric (ILD)
layer; a barrier layer surrounding bottom and sidewall surfaces of
the copper line; a top surface of the copper line directly doped
with a copper alloy material; and a dielectric layer formed over
the ILD layer and the copper alloy material; wherein the copper
alloy material serves an adhesion interface layer between the
copper line and the dielectric layer.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0008] Referring to the exemplary drawings wherein like elements
are numbered alike in the several Figures:
[0009] FIG. 1 is a scanning electron microscope (SEM) image
illustrating delamination of an NBLoK insulating layer from a lower
copper wiring line;
[0010] FIG. 2 is an enlarged image of a portion of FIG. 1,
illustrating delamination of an NBLoK insulating layer;
[0011] FIGS. 3 through 6 are a series of cross-sectional views
illustrating a method of doping the top surface of the copper line
with a metal dopant, in which:
[0012] FIG. 3 illustrates an ILD layer having a wiring opening
patterned therein, and a high doped seed layer formed over the top
surface of the ILD layer;
[0013] FIG. 4 illustrates a copper layer electroplated over the
seed layer of FIG. 3;
[0014] FIG. 5 illustrates chemical mechanical planarization or
polishing (CMP) of the excess copper layer and seed layer of FIG.
4;
[0015] FIG. 6 illustrates a layer of NBLoK formed over the layer
and the copper layer of FIG. 5, resulting in diffusion of the
dopant species from the seed layer into the copper layer;
[0016] FIGS. 7 through 12 are a series of cross-sectional views
illustrating a method of a metal interconnect structure by doping
the top surface of the copper line with a metal dopant, in
accordance with an exemplary embodiment, in which:
[0017] FIG. 7 illustrates an ILD layer having a wiring opening
patterned therein, and a high doped seed layer formed over the top
surface of the ILD layer;
[0018] FIG. 8 illustrates a copper layer electroplated over the
seed layer of FIG. 7;
[0019] FIG. 9 illustrates CMP of the excess copper layer and seed
layer of FIG. 8;
[0020] FIG. 10 illustrates the formation of a high doped seed layer
over the ILD layer, low concentration seed layer, and copper layer
of FIG. 9;
[0021] FIG. 11 illustrates an anneal of the device of FIG. 10 so as
to drive dopant atoms into the top surface of the copper layer,
creating a doped region;
[0022] FIG. 12 illustrates removal of the high concentration seed
layer of FIG. 11 and deposition of a NBLoK layer;
[0023] FIGS. 13 through 16 are a series of cross-sectional views
illustrating an alternative embodiment of FIGS. 9 through 12, in
which:
[0024] FIG. 13 illustrates CMP of the excess copper layer and seed
layer of FIG. 8, wherein the copper layer and seed layer are
recessed below the ILD layer;
[0025] FIG. 14 illustrates the formation of a high doped seed layer
over the ILD layer, low concentration seed layer, and copper layer
of FIG. 13;
[0026] FIG. 15 illustrates planarization of the portion of the high
doped seed layer over the ILD layer of FIG. 14, leaving the high
doped seed layer, and an anneal to drive dopant atoms into the top
surface of the copper layer, creating a doped region;
[0027] FIG. 16 illustrates deposition of a NBLoK layer over the
device of FIG. 15;
[0028] FIGS. 17 and 18 are cross-sectional views illustrating an
alternative embodiment of FIGS. 15 and 16, in which:
[0029] FIG. 17 illustrates planarization of the portion of the high
doped seed layer over the ILD layer of FIG. 14, leaving the high
doped seed layer; and
[0030] FIG. 18 illustrates deposition of an NBLoK layer over the
device of FIG. 17.
DETAILED DESCRIPTION
[0031] FIG. 1 is a scanning electron microscope (SEM) image
illustrating delamination of an NBLoK insulating layer from a lower
copper wiring line. As illustrated in FIG. 1, the lower copper
wiring line 102 has a layer of NBLoK dielectric 104 formed
thereupon. The lower copper wiring line 102 is intended to be
electrically connected to an upper copper wiring line 106 by vias
108. However, as will be noted, due to the weak NBLoK adhesion to
copper, delamination of the NBLoK dielectric 104 from the top
surface of the lower copper wiring line 102 has also caused
separation of the vias from the lower copper wiring line 102, in
turn leading to device opens. This delamination is also more
clearly depicted in the enlarged image of FIG. 2.
[0032] Adhesion between the copper lines and NBLoK can be greatly
enhanced by doping the top surface of the copper line with a heavy
noble metal, such as manganese (Mn). One possible manner of
locating the Mn at the top surface is by using a copper manganese
(CuMn) seed layer prior to copper plating, and thereafter thermally
diffusing the Mn through the copper line up to the top surface, as
illustrated in FIGS. 3-6.
[0033] As particularly shown in FIG. 3, an interlevel dielectric
(ILD) layer 302 (e.g., oxide, nitride, low-k dielectrics, etc.) has
a wiring opening 304 patterned therein, in accordance with
damascene processing techniques. A seed layer 306 is formed over
the top surface of the ILD layer 302, as well as over sidewall and
bottom surfaces of the opening 304 in preparation for copper
material plating. Although not specifically illustrated in FIG. 3,
one skilled in the art will appreciate one or more barrier layers
(e.g., tantalum, titanium based) may be formed over the ILD layer
302 prior to seed layer deposition.
[0034] In the example depicted, the seed layer 306 includes a CuMn
alloy having a manganese dopant concentration of about 2% atomic.
Notably, such a concentration is higher than typically may be used
in conjunction with a CuMn seed layer for electromigration
prevention purposes. In the latter case, such a seed layer
concentration may only be on the order of about 0.5% atomic.
Generally speaking, electromigration concerns are more prevalent
for the smaller thicknesses of wiring on the lower levels. However,
CuMn seed concentrations higher than about 0.5% atomic on these
levels may have the disadvantage of significantly increasing line
resistance. It will be noted that other metal materials may also be
used for dopant alloy materials such as, for example, cobalt (Co),
ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), osmium
(Os), iridium (Ir), platinum (Pt), and gold (Au).
[0035] In FIG. 4, a copper layer 308 is electroplated over the seed
layer 306 so as to completely overfill the opening. This is
followed by chemical mechanical planarization or polishing (CMP) of
the excess copper layer 308 and seed layer 306 (and barrier layer)
to expose the top surface of the ILD layer 302, as shown in FIG. 5.
Then, as shown in FIG. 6, a layer of NBLoK 310 is formed over the
ILD layer 302 and the copper layer 308. The deposition occurs at an
elevated temperature of about 400.degree. C., resulting in
diffusion of the Mn species from the seed layer 306 into the copper
layer 308. Those Mn atoms which diffuse to the top surface of the
copper layer 308 are depicted by region 312 in FIG. 6, wherein the
doped region 312 is intended to promote a better adhesion interface
between the copper layer 308 and the NBLoK layer 310. Layer 302, in
a preferred embodiment is NBLoK, but can be any dielectric layer
which inhibits copper diffusion.
[0036] One difficulty, however, with a seed layer/diffusion
approach to top surface doping is relatively large thickness (e.g.,
about 3 micron (.mu.m)) of copper line the dopant atoms must travel
to reach the surface. As a result, the doping levels of the Mn at
the doped region 312 are relatively low, which ultimately limits
the adhesion benefit of the Mn. In other words, it is difficult to
get enough Mn through the thick copper lines to reach the top
surface where it is beneficial for adhesion. In addition, the
increase in Mn concentration at the seed layer will increase the
line resistance of the copper lines, as compared to lines having a
lower CuMn seed layer concentration, or lines having only a Cu seed
layer. Moreover, diffusion through the entire line structure also
leads to larger variability in the line resistances themselves.
[0037] Accordingly, FIGS. 7 through 12 are a series of
cross-sectional views illustrating a method of forming a metal
interconnect structure by doping the top surface of a copper line
with a metal dopant, in accordance with an exemplary embodiment.
The exemplary embodiment improves NBLoK-to-copper adhesion by
directly doping the top surface of the copper lines with up to 2%
CuMn (or other suitable copper alloy material). Specifically, an
exemplary embodiment involves doping the top surface of the copper
lines with an dopant material such as Mn by sputtering CuMn
directly on the top surface of the copper lines, thermally driving
the Mn into the copper surface, and thereafter removing the
sputtered CuMn with a touch-up CMP step.
[0038] In comparison with the previously described technique, FIG.
7 illustrates an ILD layer 302 (e.g., oxide, nitride, etc.) having
a wiring opening 304 patterned therein, in accordance with
damascene processing techniques. A seed layer 314 is formed over
the top surface of the ILD layer 302, as well as over sidewall and
bottom surfaces of the opening 304 in preparation for copper
material plating. However, whereas the seed layer 306 of FIG. 3 has
the increased 2% CuMn concentration, the seed layer 314 may have a
low CuMn concentration of about 0.5% atomic Mn, or perhaps no
dopant material at all. In FIG. 8, a copper layer 308 is
electroplated over the seed layer 314 so as to completely overfill
the opening. This is followed by CMP of the excess copper layer 308
and seed layer 314 (and barrier layer, not shown), as shown in FIG.
9.
[0039] Then, as shown in FIG. 10, a high concentration CuMn seed
layer 316 (e.g., 2% atomic Mn) is formed over the ILD layer 302,
low concentration CuMn seed layer 314, and copper layer 308. The
seed layer 316 may be formed by sputtering, for example. An anneal
is then performed so as to drive Mn atoms into the top surface of
the copper layer, creating a doped region 312 as shown in FIG. 11.
The sputtered high concentration CuMn seed layer 316 is then
removed such as by CMP, leaving the doped region 312 as an
interface for better adhesion of NBLoK. The deposition of the NBLoK
layer 310 is illustrated in FIG. 12.
[0040] In an alternative embodiment, following the processing shown
in FIG. 8, the copper layer 308 and seed layer 314 may be further
recessed below the top surface of the ILD layer 302, such as by
intentional dishing (over-polish) during CMP or by a separate wet
etch step to create a recess 318 as shown in FIG. 13. The recess
318 may be on the order of about 0.2 .mu.m in depth, for example.
Then, as shown in FIG. 14, a high concentration CuMn seed layer 316
(e.g., 2% atomic Mn) is formed over the ILD layer 302, low
concentration CuMn seed layer 314, and copper layer 308. Again, the
seed layer 316 may be formed by sputtering, for example. In one
embodiment, an anneal may then be performed as described above so
as to drive Mn atoms into the top surface of the copper layer,
creating a doped region 312.
[0041] As shown in FIG. 15, the portions of the high concentration
CuMn seed layer 316 atop the ILD layer 302 may be removed by CMP,
leaving a portion of the high concentration CuMn seed layer 316
over the low concentration CuMn seed layer 314 and copper layer
308. As such, the combination of the doped region 312 and remaining
high concentration CuMn seed layer 316 provide an interface for
better adhesion of NBLoK by ensuring high Mn doping (.about.2%) on
this surface. The deposition of the NBLoK layer 310 is illustrated
in FIG. 16.
[0042] In still another embodiment, because of the recessing in
FIG. 13, which leaves a portion of the high concentration CuMn seed
layer 316 atop the low concentration CuMn seed layer 314 and copper
layer 308, an anneal need not be performed. That is, as shown in
FIG. 17, the sputtered high concentration CuMn seed layer 316 atop
the low concentration CuMn seed layer 314 and copper layer 308
serves as the interface for the subsequently deposited NBLoK layer.
The deposition of the NBLoK layer 310 is illustrated in FIG.
18.
[0043] As discussed above, prior to forming a low concentration
CuMn seed layer or perhaps a Cu seed layer in a patterned opening,
a diffusion barrier layer is typically formed prior to seed layer
deposition. It will be noted that a similar barrier layer(s) may
also be formed prior to deposition of the high concentration CuMn
seed layer 316.
[0044] While the disclosure has been described with reference to a
preferred embodiment or embodiments, it will be understood by those
skilled in the art that various changes may be made and equivalents
may be substituted for elements thereof without departing from the
scope of the disclosure. In addition, many modifications may be
made to adapt a particular situation or material to the teachings
of the disclosure without departing from the essential scope
thereof. Therefore, it is intended that the disclosure not be
limited to the particular embodiment disclosed as the best mode
contemplated for carrying out this disclosure, but that the
disclosure will include all embodiments falling within the scope of
the appended claims.
* * * * *