U.S. patent application number 14/168112 was filed with the patent office on 2015-07-30 for replacement metal gate including dielectric gate material.
This patent application is currently assigned to GLOBALFOUNDRIES Inc.. The applicant listed for this patent is GLOBALFOUNDRIES Inc., International Business Machines Corporation. Invention is credited to Linus Jang, Sivananda K. Kanakasabapathy, Sanjay C. Mehta, Soon-Cheon Seo, Raghavasimhan Sreenivasan.
Application Number | 20150214331 14/168112 |
Document ID | / |
Family ID | 53679812 |
Filed Date | 2015-07-30 |
United States Patent
Application |
20150214331 |
Kind Code |
A1 |
Jang; Linus ; et
al. |
July 30, 2015 |
REPLACEMENT METAL GATE INCLUDING DIELECTRIC GATE MATERIAL
Abstract
A method of fabricating a semiconductor device includes forming
at least one semiconductor fin on a semiconductor substrate. A
plurality of gate formation layers is formed on an etch stop layer
disposed on the fin. The plurality of gate formation layers include
a dummy gate layer formed from a dielectric material. The plurality
of gate formation layers is patterned to form a plurality of dummy
gate elements on the etch stop layer. Each dummy gate element is
formed from the dielectric material. A spacer layer formed on the
dummy gate elements is etched to form a spacer on each sidewall of
dummy gate elements. A portion of the etch stop layer located
between each dummy gate element is etched to expose a portion the
semiconductor fin. A semiconductor material is epitaxially grown
from the exposed portion of the semiconductor fin to form
source/drain regions.
Inventors: |
Jang; Linus; (Clifton Park,
NY) ; Kanakasabapathy; Sivananda K.; (Niskayuna,
NY) ; Mehta; Sanjay C.; (Niskayuna, NY) ; Seo;
Soon-Cheon; (Glenmont, NY) ; Sreenivasan;
Raghavasimhan; (Schenectady, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
International Business Machines Corporation
GLOBALFOUNDRIES Inc. |
Armonk
Grand Cayman |
NY |
US
KY |
|
|
Assignee: |
GLOBALFOUNDRIES Inc.
Grand Cayman
NY
International Business Machines Corporation
Armonk
|
Family ID: |
53679812 |
Appl. No.: |
14/168112 |
Filed: |
January 30, 2014 |
Current U.S.
Class: |
438/164 |
Current CPC
Class: |
H01L 29/6656 20130101;
H01L 29/66795 20130101; H01L 29/66575 20130101; H01L 27/1211
20130101; H01L 29/4966 20130101; H01L 29/7855 20130101; H01L
21/823425 20130101; H01L 29/41791 20130101; H01L 29/7851 20130101;
H01L 21/823437 20130101; H01L 21/31053 20130101; H01L 21/823481
20130101; H01L 29/41783 20130101; H01L 2029/7858 20130101; H01L
29/51 20130101; H01L 21/3065 20130101; H01L 21/28238 20130101; H01L
21/823468 20130101; H01L 29/66545 20130101; H01L 21/845 20130101;
H01L 21/31111 20130101; H01L 21/823431 20130101; H01L 27/0886
20130101; H01L 21/02164 20130101; H01L 21/31116 20130101; H01L
21/31144 20130101; H01L 21/2018 20130101 |
International
Class: |
H01L 29/66 20060101
H01L029/66; H01L 21/8234 20060101 H01L021/8234 |
Claims
1. A method of fabricating a semiconductor device, the method
comprising: forming at least one semiconductor fin on a
semiconductor substrate; forming an etch stop layer on an upper
surface of the at least one semiconductor fin; forming a plurality
of gate formation layers on the etch stop layer and the substrate,
the plurality of gate formation layers including a dummy gate layer
formed from a dielectric material; patterning the plurality of gate
formation layers to form a plurality of dummy gate elements on the
etch stop layer, each dummy gate element formed from the dielectric
material; depositing a spacer layer that conforms with an outer
surface of each dummy gate element; and etching the spacer layer to
form a spacer on each sidewall of the dummy gate elements and
etching a portion of the etch stop layer located between each dummy
gate element to expose a portion of the semiconductor fin.
2. The method of claim 1, further comprising epitaxially growing a
semiconductor material from the exposed portion of the
semiconductor fin after etching the spacer layer and the portion of
the etch stop layer.
3. The method of claim 2, wherein the dummy gate element is formed
from a material selected from a group comprising of boron carbide
(BC), carbon (C), silicon dioxide (SiO.sub.2), and a silicon boron
carbide material that contains nitrogen (SiB:C(N)).
4. The method of claim 3, wherein the patterning the plurality of
gate formation layers includes patterning a photoresist layer to
form a plurality of photoresist elements at a top surface of the
plurality of gate formation layers.
5. The method of claim 4, wherein the patterning the plurality of
gate formation layers further includes patterning a gate hardmask
layer formed on an upper surface of the dummy gate layer according
to the plurality of photoresist elements to form a plurality of
respective gate caps on the dummy gate layer.
6. The method of claim 5, wherein the patterning the plurality of
gate formation layers further includes patterning the dummy gate
layer according to the plurality of gate caps to form the plurality
of dummy gate elements.
7. The method of claim 6, wherein the patterning the plurality of
gate formation layers is performed according to a trilayer resist
patterning scheme.
8. A method of fabricating a semiconductor device, the method
comprising: forming at least one semiconductor fin on a
semiconductor substrate; forming an etch stop layer on an upper
surface of the at least one semiconductor fin; patterning a
photoresist layer to form a plurality of photoresist elements above
a dummy gate layer that is formed from a dielectric material;
patterning the dummy gate layer using the plurality of photoresist
elements to form plurality of respective dummy gate elements on the
etch stop layer, each dummy gate element formed from the dielectric
material; depositing a spacer layer that conforms to an outer
surface of each dummy gate element; etching the spacer layer to
form a spacer on each sidewall of the dummy gate elements; and
etching a portion of the etch stop layer located between each dummy
gate element to expose a portion of the semiconductor fins.
9. The method of claim 8, wherein the etching a portion of the etch
stop layer includes performing a pre-clean process after etching
the spacer layer, the pre-clean process forming cavities in the
etch stop layer located between the dummy gate elements to expose
an underlying portion of the at least one semiconductor fin.
10. The method of claim 9, further comprising epitaxially growing
semiconductor material from the cavities such that a portion of the
epitaxially grown semiconductor material contacts a pair of
opposing spacers to form a source/drain region.
11. The method of claim 10, further comprising depositing a contact
dielectric layer that fills a void between the spacers and covers
an upper portion of the dummy gate elements.
12. The method of claim 11, further comprising performing a
planarization process that partially recesses the contact
dielectric layer and stops on the dummy gate elements such that an
upper portion of the dummy gate elements is flush with the contact
dielectric layer.
13. The method of claim 12, further comprising removing the dummy
gate elements to form respective trenches between a pair of
respective spacers.
14. The method of claim 13, further comprising filling each trench
with a metal gate material to form a respective metal gate
element.
15. The method of claim 14, further comprising a plurality of gate
formation layers formed on an upper surface of the dummy gate
layer, the plurality of gate formation layers including a hardmask
layer formed on a gate hardmask layer formed on an upper surface of
the dummy gate layer, and an organic layer interposed between the
hardmask layer and the photoresist layer.
16. A method of fabricating a semiconductor device, the method
comprising: forming at least one semiconductor fin on a
semiconductor substrate; forming an etch stop layer on an upper
surface of the at least one semiconductor fin; forming a plurality
of dummy gate elements on the etch stop layer, each dummy gate
element formed from a dielectric material and having a hardmask
gate cap formed on an upper surface of the semiconductor fin;
depositing a high-dielectric constant layer that conforms to an
outer surface of each dummy gate element and depositing a spacer
layer on the high-dielectric constant layer; performing a first
etching process that etches the spacer layer to form a spacer on
each sidewall of dummy gate elements and exposes an upper portion
of the high-dielectric constant layer; performing a second etching
process different from the first etching process that selectively
etches the upper portion of the high-dielectric constant layer to
expose each hardmask gate cap; removing the hardmask gate caps and
the dummy gate elements to form a trench between a respective pair
of spacers; and performing a third etching process after removing
the dummy gates elements to remove a portion of the high-dielectric
constant material from the sidewalls of the spacers such that a
remaining portion of the high-dielectric constant material is
interposed between the spacers and the etch stop layer.
17. The method of claim 16, further comprising performing a
planarization process before removing the dummy gate elements to
recess the hardmask gate cap such that an upper portion of the
dummy gate elements is exposed.
18. The method of claim 17, wherein the dummy gate element is
formed from a material selected from a group comprising of boron
carbide (BC), carbon (C), silicon dioxide (SiO.sub.2), and a
silicon boron carbide material that contains nitrogen
(SiB:C(N)).
19. The method of claim 18, further comprising depositing a gate
material in the trenches to form a metal gate element that contacts
the spacers, the remaining portion of high-dielectric constant
material and the etch stop layer.
20. The method of claim 19, wherein the first etching process is a
reactive ion etching process, the second etching process is a
carina etching process, and the third etching process is a carina
etching process.
Description
BACKGROUND
[0001] The present invention relates to semiconductor device
fabrication, and in particular, to a replacement metal gate
process.
[0002] A replacement metal gate (RMG) process, i.e., a gate last
process, has been traditionally used in semiconductor fabrications
processes to form a semiconductor device including one or more gate
elements 102 that wrap around on one or more semiconductor fins
104. The gate elements 102 typically extend in a direction
perpendicular to the direction of the semiconductor fins 104 as
illustrated in FIG. 1. The RMG process utilizes a dummy gate
element formed from amorphous silicon (a-Si) or polysilicon (PC),
which is ultimately replaced with a metal gate element as
understood by those ordinarily skilled in the art. However, the
silicon material of the dummy gate element may be exposed when
recessing the spacers formed on the sidewalls of the dummy gate
element. Consequently, epitaxial material may be inadvertently
grown on the exposed silicon of the dummy gate element which may
result in a short between the epitaxially grown source/drain
regions and the epitaxial material grown on the gate element.
SUMMARY
[0003] According to at least one embodiment a method of fabricating
a semiconductor device comprises forming at least one semiconductor
fin on a semiconductor substrate. A plurality of gate formation
layers is formed on an etch stop layer that is formed on one or
more of the semiconductor fins. The plurality of gate formation
layers include a dummy gate layer formed from a dielectric
material. The plurality of gate formation layers is patterned to
form a plurality of dummy gate elements on the etch stop layer.
Each dummy gate element is formed from the dielectric material. A
spacer layer formed on the dummy gate elements is etched to form a
spacer on each sidewall of dummy gate elements. A portion of the
etch stop layer located between each dummy gate element is etched
to expose a portion the semiconductor fin. A semiconductor material
is epitaxially grown from the exposed portion of the semiconductor
fin to form source/drain regions.
[0004] According to another exemplary embodiment, a method of
fabricating a semiconductor device comprises forming at least one
semiconductor fin on a semiconductor substrate. The at least one
semiconductor fin includes an etch stop layer formed on an upper
surface thereof. The method further comprises forming a plurality
of dummy gate elements on the etch stop layer. Each dummy gate
element is formed from a dielectric material and has a hardmask
gate cap formed on an upper surface thereof. The method further
comprises depositing a high-dielectric layer that conforms to an
outer surface of each dummy gate element. A spacer layer is
deposited on the high-dielectric layer. The method further
comprises performing a first etching process that etches the spacer
layer to form a spacer on each sidewall of dummy gate elements and
exposes an upper portion of the high-dielectric layer. The method
further comprises performing a second etching process that is
different from the first etching process that selectively etches
the upper portion of the high-dielectric layer to expose each
hardmask gate cap. The method further comprises removing the
hardmask gate caps and the dummy gate elements to form a trench
between a respective pair of spacers. The method further comprises
performing a third etching process after removing the dummy gates
elements to remove a portion of the high-dielectric material from
the sidewalls of the spacers such that a remaining portion of the
high-dielectric material is interposed between the spacers and the
etch stop layer.
[0005] Additional features are realized through the techniques of
the present invention. Other embodiments are described in detail
herein and are considered a part of the claimed invention. For a
better understanding of the invention with the features, refer to
the description and to the drawings.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0006] The subject matter which is regarded as the invention is
particularly pointed out and distinctly claimed in the claims at
the conclusion of the specification. The forgoing features are
apparent from the following detailed description taken in
conjunction with the accompanying drawings in which:
[0007] FIG. 1 is an isometric view of a conventional array of
semiconductor fins having gate elements formed thereon;
[0008] FIG. 2A is block diagram of a starting substrate including a
plurality of gate formation layers formed on a semiconductor fin
according to a first orientation extending along a Y-axis to define
a length;
[0009] FIG. 2B illustrates the starting substrate of FIG. 2A
according to a second orientation showing the gate formation layers
formed on a plurality of semiconductor fins and extending along an
X-axis to define a width;
[0010] FIG. 3A illustrates the substrate of FIGS. 2A-2B according
to the first orientation following patterning of a photoresist
layer;
[0011] FIG. 3B illustrates the substrate of FIG. 3A according to
the second orientation;
[0012] FIG. 4A illustrates the substrate of FIGS. 3A-3B according
to the first orientation following etching of an optical planar
layer and hardmask layer to form individual hardmask gate caps;
[0013] FIG. 4B illustrates the substrate of FIG. 4A according to
the second orientation;
[0014] FIG. 5A illustrates the substrate of FIGS. 4A-4B according
to the first orientation after etching dummy gate layer according
to the patterned hardmask layer to form individual dummy gate
elements;
[0015] FIG. 5B illustrates the substrate of FIG. 5A according to
the second orientation;
[0016] FIG. 6 illustrates the substrate of FIG. 5A following
deposition of a conformal spacer layer on sidewalls of the dummy
gates elements, gate caps, and on exposed surfaces of the etch stop
layer located between each dummy gate element;
[0017] FIG. 7 illustrates the substrate of FIG. 6 following an
etching process that partially etches the spacer layer formed on
the dummy gate element and that removes the spacer layer formed on
the etch stop layer;
[0018] FIG. 8 illustrates the substrate of FIG. 7 following a
pre-clean process that removes a portion of the etch stop layer
located between each dummy gate element to expose a portion of the
underlying semiconductor fin;
[0019] FIG. 9 illustrates the substrate of FIG. 8 following an
epitaxial growth process that grows an epitaxial material on the
exposed portion of the semiconductor fin located between the dummy
gate elements;
[0020] FIG. 10 illustrates the substrate of FIG. 9 following
deposition of a block dielectric layer that fills the region
between the dummy gate elements and that covers the gate caps;
[0021] FIG. 11 illustrates the substrate of FIG. 10 following a
planarization process that recesses the block dielectric layer and
a portion of the spacer layer to expose the dummy gate
elements;
[0022] FIG. 12 illustrates the substrate of FIG. 11 following
removal of the dummy gate elements to form respective gate
trenches;
[0023] FIG. 13 illustrates the substrate of FIG. 12 following a
high-dielectric layer deposition and work function metal filling
process that fills the trenches with a gate metal to form
respective metal gate elements;
[0024] FIG. 14 illustrates another exemplary embodiment of the
present disclosure where a conformal high-dielectric layer is
deposited on sidewalls of the dummy gates elements, gate caps, and
on exposed surfaces of the etch stop layer located between each
dummy gate element, and a conformal spacer layer is formed on an
upper surface of the high-dielectric layer;
[0025] FIG. 15 illustrates the substrate of FIG. 14 following an
etching process that partially removes the spacer layer formed on
the etch stop layer and that etches the spacer layer formed on the
dummy gate element to expose an upper portion of the
high-dielectric layer;
[0026] FIG. 16 illustrates the substrate of FIG. 15 following an
etching process that removes an upper portion of the
high-dielectric layer;
[0027] FIG. 17 illustrates the substrate of FIG. 16 following a
planarization process that recesses a block dielectric layer and
gate caps to expose the dummy gate elements;
[0028] FIG. 18 illustrates the substrate of FIG. 17 following
removal of the dummy gate elements to form respective gate trenches
and to expose the high-dielectric layer formed on sidewalls of the
trenches;
[0029] FIG. 19 illustrates the substrate of FIG. 18 following an
etching process that removes the high-dielectric layer formed on
sidewalls of the trenches; and
[0030] FIG. 20 illustrates the substrate of FIG. 19 following a
high-dielectric layer deposition and work function metal filling
process that fills the trenches with a gate metal to form
respective metal gate elements.
[0031] FIG. 21 is a flow diagram illustrating a method of
fabricating a semiconductor device according to an exemplary
embodiment of the present disclosure.
DETAILED DESCRIPTION
[0032] With reference now to FIGS. 2A-2B, a starting semiconductor
substrate 200 including a plurality of gate formation layers formed
on one or more semiconductor fins 202 is illustrated according to
an exemplary embodiment of the present disclosure. The substrate
200 extends along an X-axis to define a width and a Y-axis to
define a length. The semiconductor fins 202 may be formed on a
buried oxide (BOX) layer 204 formed on the substrate 200. It is
appreciated, however, that the semiconductor fins 202 may be formed
on a bulk semiconductor layer of the substrate 200. An etch stop
layer 206 may be formed on an upper surface of the semiconductor
fins 202. The BOX layer and the etch stop layer may be formed from
a dielectric material including, but not limited to, silicon oxide
(SiO.sub.2). Although a finFET semiconductor device is described
going forward, it is appreciated that the inventive teachings
described herein may be applied to various other semiconductor
topologies including, but not limited to, a planar semiconductor
device, and a nanowire semiconductor device.
[0033] The gate formation layers are formed on an upper surface of
the etch stop layer 206 formed on each semiconductor fin 202. The
plurality of gate formation layers include, for example, a dummy
gate dielectric layer 208, a gate hardmask layer 210, an optical
planar layer (OPL) 212, an anti-reflective coating (ARC) layer 214,
and a photoresist layer 216. Although not illustrated, The ARC
layer 214 may be replaced with a silicon oxide layer.
[0034] The dummy gate dielectric layer 208 may be formed directly
on an upper surface of the etch stop layer 206, for example. Unlike
a conventional replacement metal gate (RMG) process, the dummy gate
dielectric layer 208 is formed from a dielectric material instead
of amorphous silicon (Si) or polysilicon (PC). The dummy gate
dielectric layer 208 may be formed from various materials
including, but not limited to, boron carbide (BC), a silicon boron
carbide material that contains nitrogen (i.e., SiB:C(N)), carbon
(C), compressed carbon, and SiO.sub.2. Therefore, at least one
exemplary embodiment of the present disclosure may prevent
inadvertent epitaxially growth on exposed portions of the dummy
gate element (described below). Accordingly, shorting between
epitaxially grown source-drain regions and the dummy gate element
may be prevented.
[0035] The gate hardmask layer 210 is stacked on the dummy gate
dielectric layer 208 and may be formed from various materials
including, but not limited to, silicon nitride (SiN) and silicon
dioxide (SiO.sub.2). The OPL 212 is stacked on the gate hardmask
layer 210 to form a planarized upper surface. The OPL 212 may be
formed from an organic dielectric layer (ODL) material including,
but not limited to, amorphous carbon, CHM701B, commercially
available from Cheil Chemical Co., Ltd., HM8006 and HM8014,
commercially available from JSR Corporation, and ODL-102,
commercially available from ShinEtsu Chemical, Co., Ltd.
[0036] The SiARC layer 214 is stacked on the OPL 212 and may
comprise Si, for example, to form a silicon-containing ARC (SiARC)
layer as described going forward. The photoresist layer 216 may be
deposited according to a chemical vapor deposition (CVD) process or
an atomic layer deposition (ALD) process as understood by those
ordinarily skilled in the art.
[0037] Referring to FIGS. 3A-3B, the photoresist layer 216 is
patterned to form one or more individual gate resist elements 218.
The gate resist elements 218 ultimately determine the pattern of
respective dummy gate elements to be formed on the substrate 200 as
understood by those ordinarily skilled in the art. The stacked
arrangement of the photoresist layer 216, the SiARC layer 214 and
the OPL 212 may form a multilayer element (e.g., a trilateral
element) such that a trilayer resist (TLR) patterning scheme may be
performed that forms one or more dummy gate elements.
[0038] According to at least embodiment, the TLR pattering scheme
comprises, for example, patterning the photoresist layer 216 using
lithography and trimming, performing first a reactive ion etching
(RIE) plasma process to etch through the SiARC layer 214 utilizing
the patterned photoresist layer 216 (i.e., the gate resist elements
218) as a first pattern mask where a portion of the photoresist
layer 216 is consumed during the during first etching, performing a
second etching process to etch the ODL utilizing the patterned
SiARC layer 214 as a second pattern mask where the photoresist
layer 216 is completely consumed during the second etching,
performing a third etching process to remove (e.g., burn-off) the
SiARC layer 214, performing a fourth etching process to etch the
gate hardmask layer 210 utilizing the etched ODL as a third pattern
mask where a portion of the gate hardmask layer 210 is removed
during the third etching such that individual hardmask gate caps
220 are formed on the dummy gate dielectric layer 208, and
stripping the etched ODL using an RIE or wet cleaning process to
form one or more individual hardmask gate caps 220 on the dummy
gate dielectric layer 208 as illustrated in FIGS. 4A-4B.
Accordingly, the pattern of the photoresist layer 216 may be
transferred to the gate hardmask layer 210 for ultimately forming
the pattern of dummy gate elements as discussed in greater detail
below
[0039] Referring to FIGS. 5A-5B, the dummy gate dielectric layer
208 is patterned according to the patterned gate hardmask layer 210
(i.e., the hardmask gate caps 220) to form individual dummy gate
elements 222. The dummy gate dielectric layer 208 may be etched
using a reactive ion etching (RIE) process as understood by those
ordinarily skilled in the art. Accordingly, one or more individual
dummy gate elements 222 are formed that wrap around one or more
semiconductor fins 202.
[0040] Turning now to FIG. 6, a conformal spacer layer 224 is
deposited on sidewalls of the dummy gates elements 222, hardmask
gate caps 220, and on exposed surfaces of the etch stop layer 206
located between each dummy gate element 222. The conformal spacer
layer 224 may be formed from, for example, silicon nitride
(SiN).
[0041] Referring to FIG. 7, the spacer layer 224 formed on the
dummy gate element 222 is partially etched such that spacers 226
are formed on sidewalls of the dummy gate element 222. Various
etching processes may be used to etch the spacer layer 224
including, but not limited to, RIE. A portion of the spacer layer
224 formed on the hardmask gate cap 220 may also be removed such
that the underlying gate cap 220 is exposed as further illustrated
in FIG. 7.
[0042] Referring to FIG. 8, a pre-clean process is performed that
removes a portion of the etch stop layer 206 located between each
dummy gate element 222. Accordingly, a cavity 228 is formed between
each dummy gate element 222, which exposes a portion of the
underlying semiconductor fin 202. The pre-clean process may be
performed using a hydrogen fluoride (HF) based wet clean process,
or a dry etching process that uses remote plasma that reacts with
the etch stop layer 206, while being selective to the spacers
226.
[0043] Turning now to FIG. 9, an epitaxial growth process is
performed that grows an epitaxial semiconductor material 230 on the
exposed portion of the semiconductor fin 202 located between the
dummy gate elements 222. Well-known processes used to epitaxially
grow an epitaxial semiconductor material 230 including, but not
limited to, silicon doped with germanium (Ge), carbon (C), and
phosphorus (P), or any dopants desired to lower external resistance
for forming a source/drain region. The epitaxial semiconductor
material 230 may be grown from a portion of the semiconductor fin
202 exposed by a respective cavity 228 and may extend therefrom to
contact the sidewalls of a pair of opposing spacers 226 to form one
or more source/drain regions.
[0044] Referring to FIG. 10, a contact dielectric layer 232 is
deposited on the hardmask gate caps 220 and in the voids between
the dummy gate elements 222. The contact dielectric layer 232 may
also contact one or more source/drain regions of one or more
semiconductor fins 202. Various methods may be used to deposit the
contact dielectric layer 232 including, but not limited to,
chemical vapor deposition (CVD) and atomic layer deposition (ALD).
The contact dielectric layer 232 may be formed from various
materials including, but not limited to, SiO.sub.2.
[0045] Referring now to FIG. 11, a planarization process is
performed, which partially recesses the contact dielectric layer
232 and a portion of the spacer layer 224 to expose the dummy gate
elements 222. The planarization process may stop on the upper
surface of the dummy gate elements 222 such that the upper surface
of the contact dielectric layer 232 is flush with the upper
surfaces of the dummy gate elements 222.
[0046] Turning to FIG. 12, the dummy gate elements 222 are removed
according to a replacement metal gate (RMG) process as understood
by those ordinarily skilled in the art. For example, the dummy gate
elements 222 may be removed using an RIE process or a wet etching
process. Accordingly, gate trenches 234 that expose the underlying
etch stop layer 206 of the semiconductor fin 202 are formed between
a respective pair of spacers 226. According to at least one
embodiment, an anneal process may be performed after removing the
dummy gate elements 222 to activate the dopants of the source/drain
regions. The anneal process may generate a temperature of
approximately 900 degrees Celsius (C) or higher, for example.
[0047] Referring to FIG. 13, a metal filling process is performed
that fills the trenches with a gate metal to form respective metal
gate elements 236. The gate metal may include various metal
materials including, but not limited to, tungsten (W), tantalum
(Ta), titanium (Ti), Niobium (Nb), rhenium (Rh), aluminum (Al),
tungsten nitride (WN), titanium nitride (TiN) and tantalum nitride
(TaN). According to this exemplary embodiment, each metal may
contact a respective pair of spacers 226 and a respective etch stop
layer 206. In another embodiment, one or more work function metal
(WFM) layers may be deposited in the trenches 234 and formed on the
sidewalls of the spacers 226 before filling the trenches 234 with
the metal gate material. The WFM layer may tune the threshold
voltage of a resulting semiconductor device as understood by those
ordinarily skilled in the art.
[0048] Turning now to FIGS. 14-20, a process flow that interposes a
high-dielectric constant layer 238 (i.e., a high-k layer 238)
between the spacers 226 and the sidewalls of each dummy gate
element 222 is illustrated according to an exemplary embodiment of
the present disclosure. In this regard, FIG. 14 illustrates a
conformal high-k layer 238 interposed between a conformal spacer
layer 224 and the dummy gate elements 222. The conformal high-k
layer 238 may first be deposited on sidewalls of the dummy gates
elements 222, hardmask gate caps 220, and exposed surfaces of the
etch stop layer 206 located between each dummy gate element 222.
The high-k layer 238 may be formed from various high-k materials
including, but not limited to, hafnium oxide (HfO.sub.2). The
conformal spacer layer 224 may then be formed on an upper surface
of the high-k layer 238. The conformal spacer layer 224 may be
formed from, for example, SiN.
[0049] Referring to FIG. 15, an etching process is performed that
partially removes the spacer layer 224 formed on the etch stop
layer 206 and that etches the spacer layer 224 formed on the dummy
gate element 222. Accordingly, an upper portion of the high-k layer
238 is exposed.
[0050] Referring to FIG. 16, a second etching process, such as a
carina etch for example, is performed that removes the exposed
upper portion of the high-k layer 238. The carina etch is selective
to the spacer layer 224 such that the high-k layer 238 is removed
while the spacer layer 224 is maintained. Accordingly, an upper
portion of the underlying hardmask gate cap 220 is exposed.
[0051] Referring to FIG. 17, a planarization process that partially
recesses a contact dielectric layer 232 is performed which exposes
an upper portion of the dummy gate elements 222. The contact
dielectric layer 232 is formed as previously discussed above. The
planarization process may stop on the upper surface of the dummy
gate elements 222 such that the upper surface of the contact
dielectric layer 232 is flush with the upper surfaces of the dummy
gate elements 222.
[0052] Referring now to FIG. 18, the dummy gate elements 222 are
removed according to a replacement metal gate (RMG) process as
understood by those ordinarily skilled in the art. For example, an
RIE process or a wet etching process may be used to remove the
dummy gate elements 222. Accordingly, gate trenches 234 are formed
that expose portions of the underlying etch stop layer 206 located
between the remaining high-k layer 238 formed on sidewalls of the
spacers 226.
[0053] Referring to FIG. 19, an etching process is performed that
removes portions of the high-k layer 238 from the sidewalls of the
spacers 226 such that the length of each trench 234 increases.
Various etchings process may be used to remove the high-k layer 238
including, but not limited to, a carina etch. As illustrated in
FIG. 19, for example, a portion of the high-k layer 238' may be
maintained between the spacer 226 and the etch stop layer 206,
while the trench 234 exposes a portion of the etch stop layer 206
located between the spacers 226. Although not illustrated, at least
one exemplary embodiment of the present teachings utilizes the
high-k layer 238 as a gate oxide layer. In this regard, the
properties of the high-k layer 238 may change during the dummy gate
pull process to affect work function properties. For purpose of
gate work function control, the high-k layer 238 may be best used
as a sacrificial layer and may be omitted at FIG. 19, and deposited
as a high-k gate oxide layer before performing a metal filling
process described below. Accordingly, process of removing portions
of the high-k layer 238 from the sidewalls is optional and may be
skipped at this stage of the exemplary process flow.
[0054] Turning now to FIG. 20, a metal filling process is performed
that fills the trenches 234 with a gate metal to form respective
metal gate elements 236. The gate metal may include various metal
materials including, but not limited to, tungsten (W), tantalum
(Ta), titanium (Ti), Niobium (Nb), rhenium (Rh), aluminum (Al),
tungsten nitride (WN), titanium nitride (TiN) and tantalum nitride
(TaN). According to this exemplary embodiment, the metal gate
elements 236 may contact the spacers 226, the remaining high-k
material, and the etch stop layer 206. As discussed above, a high-k
layer 238 for forming a gate oxide layer may be deposited in the
trenches 234 before depositing the gate metal in the trenches
234.
[0055] FIG. 21 is a flow diagram illustrating a method of
fabricating a semiconductor device according to an exemplary
embodiment of the present disclosure. The method begins at
operation 2100, and proceeds to operation 2102 where a plurality of
gate formation layers are formed on one or more semiconductor fins.
The semiconductor fins are formed on a semiconductor substrate as
understood by those ordinarily skilled in the art. At operation
2104, the plurality of gate formation layers are etched such that a
one or more hardmask gate caps are patterned atop a dummy gate
dielectric layer. A trilayer resist (TLR) patterning scheme may be
used to etch the gate formation layer, for example. At operation
2106, the dummy gate dielectric layer is etched to form one or more
dummy gate elements having a respective hardmask gate cap formed on
an upper surface thereof. The pattern of the one or more gate
elements may be based on a pattern of the one or more hardmask gate
caps previously formed atop the dummy gate dielectric layer. At
operation 2108, a conformal spacer layer is deposited on sidewalls
of the dummy gates elements, the gate caps, and on the exposed
surfaces of the etch stop layer located between each dummy gate
element. According to another exemplary embodiment, a conformal
high-k layer may be deposited on sidewalls of the dummy gates
elements, the gate caps, and on the exposed surfaces of the etch
stop layer located between each dummy gate element. Thereafter, the
conformal spacer layer is deposited on top of the high-k layer. In
this regard, the high-k layer is interposed between the dummy gate
elements and the spacer layer.
[0056] Turning to operation 2110, the spacer layer formed on the
dummy gate element is partially etched such that the spacers are
formed on the sidewalls of the dummy gate element and a portion of
the underlying gate cap is exposed. At operation 2112, a pre-clean
process is performed that removes a portion of the etch stop layer
located between each dummy gate element. Accordingly, a portion of
the underlying semiconductor fin located between each dummy gate
element is exposed. At operation 2114, an epitaxial material is
grown on the exposed portion of the semiconductor fin located
between the dummy gate elements. At operation 2116, a contact
dielectric layer is deposited on the gate caps and in the voids
between the dummy gate elements. At operation 2118, a portion of
contact dielectric layer and a portion of the spacers are recessed
using, for example, a chemical mechanical planarization (CMP)
process. The planarization process may stop on the upper surface of
the dummy gate elements such that the upper surface of the contact
dielectric layer is flush with the upper surfaces of the dummy gate
elements. At operation 2120, the dummy gate elements are removed
according to a replacement metal gate (RMG) process as understood
by those ordinarily skilled in the art. For example, a wet etching
process or RIE process may be used to remove the dummy gate
elements. Accordingly, gate trenches that expose the underlying
etch stop layer are formed between a respective pair of spacers. At
operation 2122, the trenches are filled with a metal gate material
to form respective metal gate elements, and the method ends at
operation 2124.
[0057] The terminology used herein is for the purpose of describing
particular embodiments only and is not intended to be limiting of
the invention. As used herein, the singular forms "a", "an" and
"the" are intended to include the plural forms as well, unless the
context clearly indicates otherwise. It will be further understood
that the terms "comprises" and/or "comprising," when used in this
specification, specify the presence of stated features, integers,
steps, operations, elements, and/or components, but do not preclude
the presence or addition of one more other features, integers,
steps, operations, element components, and/or groups thereof.
[0058] The corresponding structures, materials, acts, and
equivalents of all means or step plus function elements in the
claims below are intended to include any structure, material, or
act for performing the function in combination with other claimed
elements as specifically claimed. The description of the present
invention has been presented for purposes of illustration and
description, but is not intended to be exhaustive or limited to the
invention in the form disclosed. Many modifications and variations
will be apparent to those of ordinary skill in the art without
departing from the scope and spirit of the invention. The
embodiment was chosen and described in order to best explain the
principles of the inventive teachings and the practical
application, and to enable others of ordinary skill in the art to
understand the invention for various embodiments with various
modifications as are suited to the particular use contemplated.
[0059] The flow diagrams depicted herein are just one example.
There may be many variations to this diagram or the operations
described therein without departing from the spirit of the
invention. For instance, the operations may be performed in a
differing order or operations may be added, deleted or modified.
All of these variations are considered a part of the claimed
invention.
[0060] While various embodiments have been described, it will be
understood that those skilled in the art, both now and in the
future, may make various modifications which fall within the scope
of the claims which follow. These claims should be construed to
maintain the proper protection for the invention first
described.
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