Jang; Linus

Patent Applications and Registrations

Patent applications and USPTO patent grants for Jang; Linus.The latest application filed is for "devices with chamfer-less vias multi-patterning and methods for forming chamfer-less vias".

Company Profile

2.19.21

Jang; Linus - Portland OR
Jang; Linus - Clifton Park NY
Jang; Linus - Delmar NY US
Jang; Linus - Champaign IL

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Sidewall image transfer process for multiple gate width patterning Grant 10,297,510 - Seo , et al.	2019-05-21
Dummy gate used as interconnection and method of making the same Grant 10,283,505 - Wang , et al.	2019-05-07
Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less vias Grant 10,181,420 - Stephens , et al. Ja	2019-01-15
Devices With Chamfer-less Vias Multi-patterning And Methods For Forming Chamfer-less Vias App 20180226294 - STEPHENS; Jason Eugene ; et al.	2018-08-09
Removal of semiconductor growth defects Grant 9,842,741 - Seo , et al. December 12, 2	2017-12-12
Dummy Gate Used As Interconnection And Method Of Making The Same App 20170141110 - WANG; Wenhui ; et al.	2017-05-18
Freestanding spacer having sub-lithographic lateral dimension and method of forming same Grant 9,653,571 - Chen , et al. May 16, 2	2017-05-16
Replacement metal gate including dielectric gate material Grant 9,653,573 - Jang , et al. May 16, 2	2017-05-16
Removal Of Semiconductor Growth Defects App 20170076954 - Seo; Soon-cheon ; et al.	2017-03-16
Dummy gate used as interconnection and method of making the same Grant 9,595,478 - Wang , et al. March 14, 2	2017-03-14
Freestanding Spacer Having Sub-lithographic Lateral Dimension And Method Of Forming Same App 20160365425 - Chen; Hsueh-Chung ; et al.	2016-12-15
Dummy Gate Used As Interconnection And Method Of Making The Same App 20160365288 - WANG; Wenhui ; et al.	2016-12-15
Lithography Stack And Method App 20160336172 - JANG; Linus ; et al.	2016-11-17
Removal of semiconductor growth defects Grant 9,496,257 - Seo , et al. November 15, 2	2016-11-15
Methods of forming features having differing pitch spacing and critical dimensions Grant 9,449,835 - Jang , et al. September 20, 2	2016-09-20
Methods of forming integrated circuits and multiple critical dimension self-aligned double patterning processes Grant 9,431,264 - Jang , et al. August 30, 2	2016-08-30
Replacement Metal Gate Including Dielectric Gate Material App 20160172467 - Jang; Linus ; et al.	2016-06-16
Methods Of Forming Features Having Differing Pitch Spacing And Critical Dimensions App 20160163555 - Jang; Linus ; et al.	2016-06-09
Methods Of Patterning Features Having Differing Widths App 20160064236 - Jang; Linus ; et al.	2016-03-03
Removal Of Semiconductor Growth Defects App 20150380405 - Seo; Soon-cheon ; et al.	2015-12-31
Methods of patterning features having differing widths Grant 9,214,360 - Jang , et al. December 15, 2	2015-12-15
Replacement Metal Gate Including Dielectric Gate Material App 20150357434 - Jang; Linus ; et al.	2015-12-10
Methods for fabricating integrated circuits including selectively forming and removing fin structures Grant 9,209,037 - Cantone , et al. December 8, 2	2015-12-08
Methods for fabricating integrated circuits using self-aligned quadruple patterning Grant 9,209,038 - Cantone , et al. December 8, 2	2015-12-08
Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices Grant 9,184,263 - Cai , et al. November 10, 2	2015-11-10
Methods For Fabricating Integrated Circuits Using Self-aligned Quadruple Patterning App 20150318181 - Cantone; Jason Richard ; et al.	2015-11-05
Methods For Fabricating Integrated Circuits Including Selectively Forming And Removing Fin Structures App 20150255299 - Cantone; Jason Richard ; et al.	2015-09-10
Replacement Metal Gate Including Dielectric Gate Material App 20150214331 - Jang; Linus ; et al.	2015-07-30
Methods Of Forming Gate Structures For Semiconductor Devices Using A Replacement Gate Technique And The Resulting Devices App 20150187905 - Cai; Xiuyu ; et al.	2015-07-02
Energy-efficient smart window system Grant 9,045,933 - Jain , et al. June 2, 2	2015-06-02
Methods Of Forming Integrated Circuits And Multiple Critical Dimension Self-aligned Double Patterning Processes App 20150064912 - Jang; Linus ; et al.	2015-03-05
Methods Of Patterning Features Having Differing Widths App 20140329388 - Jang; Linus ; et al.	2014-11-06
Methods of forming trench/hole type features in a layer of material of an integrated circuit product Grant 8,871,649 - Jang , et al. October 28, 2	2014-10-28
Methods Of Forming Trench/hole Type Features In A Layer Of Material Of An Integrated Circuit Product App 20140273443 - Jang; Linus ; et al.	2014-09-18
Finfet Formation Using Double Patterning Memorization App 20140141605 - PARK; Chang Seo ; et al.	2014-05-22
FinFET formation using double patterning memorization Grant 8,716,094 - Park , et al. May 6, 2	2014-05-06
Energy-Efficient Smart Window System App 20120307352 - Jain; Kanti ; et al.	2012-12-06
Energy-efficient optoelectronic smart window Grant 7,940,457 - Jain , et al. May 10, 2	2011-05-10
Energy-Efficient Optoelectronic Smart Window App 20090296188 - Jain; Kanti ; et al.	2009-12-03

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.