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name:-0.08068585395813
name:-0.1170539855957
name:-0.031445026397705
Mehta; Sanjay C. Patent Filings

Mehta; Sanjay C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Mehta; Sanjay C..The latest application filed is for "phase change memory cell with a wrap around and ring type of electrode contact and a projection liner".

Company Profile
32.90.84
  • Mehta; Sanjay C. - Niskayuna NY
  • Mehta; Sanjay C - Niskayuna NY US
  • Mehta; Sanjay C. - Poughkeepsie NY
  • Mehta; Sanjay C. - Schenectady NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Phase change memory cell with a wrap around and ring type of electrode contact and a projection liner
Grant 11,456,415 - Ok , et al. September 27, 2
2022-09-27
Phase Change Memory Cell With A Wrap Around And Ring Type Of Electrode Contact And A Projection Liner
App 20220181546 - Ok; Injo ;   et al.
2022-06-09
Approach to bottom dielectric isolation for vertical transport fin field effect transistors
Grant 11,302,797 - Bi , et al. April 12, 2
2022-04-12
Phase change memory device
Grant 11,264,569 - Ok , et al. March 1, 2
2022-03-01
High thermal budget compatible punch through stop integration using doped glass
Grant 11,171,204 - Cheng , et al. November 9, 2
2021-11-09
High thermal budget compatible punch through stop integration using doped glass
Grant 11,152,460 - Cheng , et al. October 19, 2
2021-10-19
Phase Change Memory Device
App 20210135104 - Ok; Injo ;   et al.
2021-05-06
Gate first technique in vertical transport FET using doped silicon gates with silicide
Grant 10,892,339 - Bao , et al. January 12, 2
2021-01-12
Gate tie-down enablement with inner spacer
Grant 10,879,375 - Fan , et al. December 29, 2
2020-12-29
Approach to bottom dielectric isolation for vertical transport fin field effect transistors
Grant 10,840,354 - Bi , et al. November 17, 2
2020-11-17
Selective contact etch for unmerged epitaxial source/drain regions
Grant 10,784,258 - Mehta , et al. Sept
2020-09-22
Self aligned top extension formation for vertical transistors
Grant 10,784,371 - Gluschenkov , et al. Sept
2020-09-22
Gate First Technique In Vertical Transport Fet Using Doped Silicon Gates With Silicide
App 20200295147 - BAO; RUQIANG ;   et al.
2020-09-17
Approach To Bottom Dielectric Isolation For Vertical Transport Fin Field Effect Transistors
App 20200212202 - Bi; Zhenxing ;   et al.
2020-07-02
Protection of high-K dielectric during reliability anneal on nanosheet structures
Grant 10,692,985 - Loubet , et al.
2020-06-23
Self aligned top extension formation for vertical transistors
Grant 10,651,308 - Gluschenkov , et al.
2020-05-12
Device Variation Control Of Vertical Transport Fin Field Effect Transistor Devices By Selective Oxide Deposition For Shallow Tre
App 20200135873 - Wu; Heng ;   et al.
2020-04-30
Approach to bottom dielectric isolation for vertical transport fin field effect transistors
Grant 10,629,702 - Bi , et al.
2020-04-21
High Thermal Budget Compatible Punch Through Stop Integration Using Doped Glass
App 20200083323 - CHENG; KANGGUO ;   et al.
2020-03-12
High Thermal Budget Compatible Punch Through Stop Integration Using Doped Glass
App 20200083322 - CHENG; KANGGUO ;   et al.
2020-03-12
High thermal budget compatible punch through stop integration using doped glass
Grant 10,580,855 - Cheng , et al.
2020-03-03
High thermal budget compatible punch through stop integration using doped glass
Grant 10,580,854 - Cheng , et al.
2020-03-03
Method of forming vertical transistor having dual bottom spacers
Grant 10,529,828 - Gluschenkov , et al. J
2020-01-07
Gate tie-down enablement with inner spacer
Grant 10,522,654 - Fan , et al. Dec
2019-12-31
Self Aligned Top Extension Formation For Vertical Transistors
App 20190386137 - Gluschenkov; Oleg ;   et al.
2019-12-19
Gate Tie-down Enablement With Inner Spacer
App 20190363178 - Fan; Su Chen ;   et al.
2019-11-28
Selective Contact Etch For Unmerged Epitaxial Source/drain Regions
App 20190333916 - Mehta; Sanjay C. ;   et al.
2019-10-31
Air gap spacer formation for nano-scale semiconductor devices
Grant 10,418,277 - Cheng , et al. Sept
2019-09-17
Air Gap Spacer Formation For Nano-scale Semiconductor Devices
App 20190267279 - Cheng; Kangguo ;   et al.
2019-08-29
Selective contact etch for unmerged epitaxial source/drain regions
Grant 10,366,988 - Mehta , et al. July 30, 2
2019-07-30
Spacer formation on semiconductor device
Grant 10,355,109 - Devarajan , et al. July 16, 2
2019-07-16
Gate tie-down enablement with inner spacer
Grant 10,332,977 - Fan , et al.
2019-06-25
Protection Of High-k Dielectric During Reliability Anneal On Nanosheet Structures
App 20190189766 - Loubet; Nicolas J. ;   et al.
2019-06-20
Method Of Forming Vertical Transistor Having Dual Bottom Spacers
App 20190172928 - Gluschenkov; Oleg ;   et al.
2019-06-06
Protection of high-K dielectric during reliability anneal on nanosheet structures
Grant 10,304,936 - Loubet , et al.
2019-05-28
Vertical transistor top epitaxy source/drain and contact structure
Grant 10,269,652 - Gluschenkov , et al.
2019-04-23
Vertical transistor top epitaxy source/drain and contact structure
Grant 10,262,904 - Gluschenkov , et al.
2019-04-16
Method of forming vertical transistor having dual bottom spacers
Grant 10,236,360 - Gluschenkov , et al.
2019-03-19
Pure boron for silicide contact
Grant 10,229,982 - Chen , et al.
2019-03-12
Fabrication of vertical doped fins for complementary metal oxide semiconductor field effect transistors
Grant 10,170,479 - Cheng , et al. J
2019-01-01
Gate Tie-down Enablement With Inner Spacer
App 20180374932 - Fan; Su Chen ;   et al.
2018-12-27
Self Aligned Top Extension Formation For Vertical Transistors
App 20180331216 - Gluschenkov; Oleg ;   et al.
2018-11-15
Gate tie-down enablement with inner spacer
Grant 10,128,352 - Fan , et al. November 13, 2
2018-11-13
Air gap spacer formation for nano-scale semiconductor devices
Grant 10,115,629 - Cheng , et al. October 30, 2
2018-10-30
Vertical Transistor Top Epitaxy Source/drain And Contact Structure
App 20180277446 - Gluschenkov; Oleg ;   et al.
2018-09-27
Vertical Transistor Top Epitaxy Source/drain And Contact Structure
App 20180277445 - Gluschenkov; Oleg ;   et al.
2018-09-27
Self aligned top extension formation for vertical transistors
Grant 10,079,299 - Gluschenkov , et al. September 18, 2
2018-09-18
Air Gap Spacer Formation For Nano-scale Semiconductor Devices
App 20180261494 - Cheng; Kangguo ;   et al.
2018-09-13
Modulating transistor performance
Grant 10,056,382 - Guo , et al. August 21, 2
2018-08-21
Approach To Bottom Dielectric Isolation For Vertical Transport Fin Field Effect Transistors
App 20180226489 - Bi; Zhenxing ;   et al.
2018-08-09
Approach To Bottom Dielectric Isolation For Vertical Transport Fin Field Effect Transistors
App 20180226491 - Bi; Zhenxing ;   et al.
2018-08-09
Method Of Forming Vertical Transistor Having Dual Bottom Spacers
App 20180190794 - GLUSCHENKOV; OLEG ;   et al.
2018-07-05
Field effect transistor device spacers
Grant 10,014,299 - Cai , et al. July 3, 2
2018-07-03
Gate Tie-down Enablement With Inner Spacer
App 20180151433 - Fan; Su Chen ;   et al.
2018-05-31
High thermal budget compatible punch through stop integration using doped glass
Grant 9,985,096 - Cheng , et al. May 29, 2
2018-05-29
Bottom Spacer Formation For Vertical Transistor
App 20180114860 - Gluschenkov; Oleg ;   et al.
2018-04-26
Self Aligned Top Extension Formation For Vertical Transistors
App 20180114859 - Gluschenkov; Oleg ;   et al.
2018-04-26
Effective device formation for advanced technology nodes with aggressive fin-pitch scaling
Grant 9,953,976 - Ok , et al. April 24, 2
2018-04-24
Bottom spacer formation for vertical transistor
Grant 9,954,103 - Gluschenkov , et al. April 24, 2
2018-04-24
Modulating Transistor Performance
App 20180108661 - Guo; Dechao ;   et al.
2018-04-19
Gate tie-down enablement with inner spacer
Grant 9,941,163 - Fan , et al. April 10, 2
2018-04-10
Method of forming vertical transistor having dual bottom spacers
Grant 9,941,391 - Gluschenkov , et al. April 10, 2
2018-04-10
Gate tie-down enablement with inner spacer
Grant 9,929,049 - Fan , et al. March 27, 2
2018-03-27
Pure boron for silicide contact
Grant 9,923,074 - Chen , et al. March 20, 2
2018-03-20
Spacer Formation On Semiconductor Device
App 20180076302 - Devarajan; Thamarai Selvi ;   et al.
2018-03-15
Spacer formation on semiconductor device
Grant 9,911,831 - Devarajan , et al. March 6, 2
2018-03-06
POC process flow for conformal recess fill
Grant 9,911,823 - Greene , et al. March 6, 2
2018-03-06
High Thermal Budget Compatible Punch Through Stop Integration Using Doped Glass
App 20180061940 - CHENG; KANGGUO ;   et al.
2018-03-01
Gate tie-down enablement with inner spacer
Grant 9,899,259 - Fan , et al. February 20, 2
2018-02-20
Air Gap Spacer Formation For Nano-scale Semiconductor Devices
App 20180047617 - Cheng; Kangguo ;   et al.
2018-02-15
Air Gap Spacer Formation For Nano-scale Semiconductor Devices
App 20180047615 - Cheng; Kangguo ;   et al.
2018-02-15
Method Of Forming Vertical Transistor Having Dual Bottom Spacers
App 20180047828 - GLUSCHENKOV; OLEG ;   et al.
2018-02-15
Air gap spacer formation for nano-scale semiconductor devices
Grant 9,892,961 - Cheng , et al. February 13, 2
2018-02-13
High Thermal Budget Compatible Punch Through Stop Integration Using Doped Glass
App 20180040692 - CHENG; KANGGUO ;   et al.
2018-02-08
Fabrication of vertical doped fins for complementary metal oxide semiconductor field effect transistors
Grant 9,871,041 - Cheng , et al. January 16, 2
2018-01-16
Fabrication Of Vertical Doped Fins For Complementary Metal Oxide Semiconductor Field Effect Transistors
App 20180006036 - Cheng; Kangguo ;   et al.
2018-01-04
Fabrication Of Vertical Doped Fins For Complementary Metal Oxide Semiconductor Field Effect Transistors
App 20180006037 - Cheng; Kangguo ;   et al.
2018-01-04
Gate Tie-down Enablement With Inner Spacer
App 20170372959 - Fan; Su Chen ;   et al.
2017-12-28
High thermal budget compatible punch through stop integration using doped glass
Grant 9,847,388 - Cheng , et al. December 19, 2
2017-12-19
Protection Of High-k Dielectric During Reliability Anneal On Nanosheet Structures
App 20170323949 - Loubet; Nicolas J. ;   et al.
2017-11-09
Pure Boron For Silicide Contact
App 20170288035 - Chen; Chia-Yu ;   et al.
2017-10-05
Pure Boron For Silicide Contact
App 20170288036 - Chen; Chia-Yu ;   et al.
2017-10-05
Gate Tie-down Enablement With Inner Spacer
App 20170278753 - Fan; Su Chen ;   et al.
2017-09-28
Bottom spacer formation for vertical transistor
Grant 9,773,901 - Gluschenkov , et al. September 26, 2
2017-09-26
Self aligned top extension formation for vertical transistors
Grant 9,748,382 - Gluschenkov , et al. August 29, 2
2017-08-29
Vertical transistor bottom spacer formation
Grant 9,748,359 - Gluschenkov , et al. August 29, 2
2017-08-29
Pure boron for silicide contact
Grant 9,741,813 - Chen , et al. August 22, 2
2017-08-22
Pure boron for silicide contact
Grant 9,735,248 - Chen , et al. August 15, 2
2017-08-15
Gate tie-down enablement with inner spacer
Grant 9,735,054 - Fan , et al. August 15, 2
2017-08-15
Gate Tie-down Enablement With Inner Spacer
App 20170170070 - Fan; Su Chen ;   et al.
2017-06-15
Spacer Formation On Semiconductor Device
App 20170170301 - Devarajan; Thamarai Selvi ;   et al.
2017-06-15
Gate Tie-down Enablement With Inner Spacer
App 20170162438 - Fan; Su Chen ;   et al.
2017-06-08
Poc Process Flow For Conformal Recess Fill
App 20170148895 - Greene; Andrew M. ;   et al.
2017-05-25
Effective Device Formation For Advanced Technology Nodes With Aggressive Fin-pitch Scaling
App 20170148789 - Ok; Injo ;   et al.
2017-05-25
Replacement metal gate including dielectric gate material
Grant 9,653,573 - Jang , et al. May 16, 2
2017-05-16
Wafer bonding using boron and nitrogen based bonding stack
Grant 9,640,514 - Lin , et al. May 2, 2
2017-05-02
POC process flow for conformal recess fill
Grant 9,634,110 - Greene , et al. April 25, 2
2017-04-25
Gate tie-down enablement with inner spacer
Grant 9,627,257 - Fan , et al. April 18, 2
2017-04-18
Field Effect Transistor Device Spacers
App 20170092645 - Cai; Xiuyu ;   et al.
2017-03-30
Hydrogen-free silicon-based deposited dielectric films for nano device fabrication
Grant 9,607,825 - Canaperi , et al. March 28, 2
2017-03-28
Poc Process Flow For Conformal Recess Fill
App 20170084712 - Greene; Andrew M. ;   et al.
2017-03-23
High Thermal Budget Compatible Punch Through Stop Integration Using Doped Glass
App 20170062557 - CHENG; KANGGUO ;   et al.
2017-03-02
High Thermal Budget Compatible Punch Through Stop Integration Using Doped Glass
App 20170062566 - CHENG; KANGGUO ;   et al.
2017-03-02
Solid state diffusion doping for bulk finFET devices
Grant 9,583,489 - Anderson , et al. February 28, 2
2017-02-28
POC process flow for conformal recess fill
Grant 9,576,954 - Greene , et al. February 21, 2
2017-02-21
Selective Contact Etch For Unmerged Epitaxial Source/drain Regions
App 20170047325 - Mehta; Sanjay C. ;   et al.
2017-02-16
Gate Tie-down Enablement With Inner Spacer
App 20170047254 - Fan; Su Chen ;   et al.
2017-02-16
Gate Tie-down Enablement With Inner Spacer
App 20170047252 - Fan; Su Chen ;   et al.
2017-02-16
Effective device formation for advanced technology nodes with aggressive fin-pitch scaling
Grant 9,564,370 - Ok , et al. February 7, 2
2017-02-07
Pure Boron For Silicide Contact
App 20170033193 - Chen; Chia-Yu ;   et al.
2017-02-02
Pure Boron For Silicide Contact
App 20170033188 - Chen; Chia-Yu ;   et al.
2017-02-02
Hydrogen-free silicon-based deposited dielectric films for nano device fabrication
Grant 9,558,935 - Canaperi , et al. January 31, 2
2017-01-31
Hydrogen-free silicon-based deposited dielectric films for nano device fabrication
Grant 9,558,934 - Canaperi , et al. January 31, 2
2017-01-31
Field effect transistor device spacers
Grant 9,536,981 - Cai , et al. January 3, 2
2017-01-03
Hydrogen-free silicon-based deposited dielectric films for nano device fabrication
Grant 9,536,733 - Canaperi , et al. January 3, 2
2017-01-03
Replacement metal gate finFET
Grant 9,530,651 - Jagannathan , et al. December 27, 2
2016-12-27
Pure boron for silicide contact
Grant 9,484,431 - Chen , et al. November 1, 2
2016-11-01
Pure boron for silicide contact
Grant 9,484,256 - Chen , et al. November 1, 2
2016-11-01
Replacement metal gate FinFET
Grant 9,472,407 - Jagannathan , et al. October 18, 2
2016-10-18
Hydrogen-free silicon-based deposited dielectric films for nano device fabrication
Grant 9,449,812 - Canaperi , et al. September 20, 2
2016-09-20
Spacer formation on semiconductor device
Grant 9,443,855 - Devarajan , et al. September 13, 2
2016-09-13
Replacement metal gate FinFET
Grant 9,437,436 - Jagannathan , et al. September 6, 2
2016-09-06
Field effect transistor device spacers
Grant 9,425,292 - Cai , et al. August 23, 2
2016-08-23
POC process flow for conformal recess fill
Grant 9,406,767 - Greene , et al. August 2, 2
2016-08-02
Gate tie-down enablement with inner spacer
Grant 9,397,049 - Fan , et al. July 19, 2
2016-07-19
Spacer replacement for replacement metal gate semiconductor devices
Grant 9,373,697 - Mehta , et al. June 21, 2
2016-06-21
Replacement Metal Gate Including Dielectric Gate Material
App 20160172467 - Jang; Linus ;   et al.
2016-06-16
Wafer backside particle mitigation
Grant 9,318,347 - Bergendahl , et al. April 19, 2
2016-04-19
Hydrogen-free Silicon-based Deposited Dielectric Films For Nano Device Fabrication
App 20160064509 - Canaperi; Donald Francis ;   et al.
2016-03-03
Hydrogen-free Silicon-based Deposited Dielectric Films For Nano Device Fabrication
App 20160056111 - Canaperi; Donald Francis ;   et al.
2016-02-25
Wafer Backside Particle Mitigation
App 20160049311 - Bergendahl; Marc A. ;   et al.
2016-02-18
Hydrogen-free Silicon-based Deposited Dielectric Films For Nano Device Fabrication
App 20160047038 - Canaperi; Donald Francis ;   et al.
2016-02-18
Replacement Metal Gate Including Dielectric Gate Material
App 20150357434 - Jang; Linus ;   et al.
2015-12-10
Wafer backside particle mitigation
Grant 9,184,042 - Bergendahl , et al. November 10, 2
2015-11-10
Spacer replacement for replacement metal gate semiconductor devices
Grant 9,171,927 - Mehta , et al. October 27, 2
2015-10-27
Method to enhance strain in fully isolated finFET structures
Grant 9,166,049 - Loubet , et al. October 20, 2
2015-10-20
Hydrogen-free Silicon-based Deposited Dielectric Films For Nano Device Fabrication
App 20150287593 - Canaperi; Donald Francis ;   et al.
2015-10-08
Replacement metal gate FinFET
Grant 9,153,447 - Jagannathan , et al. October 6, 2
2015-10-06
Method To Enhance Strain In Fully Isolated Finfet Structures
App 20150255605 - Loubet; Nicolas ;   et al.
2015-09-10
Replacement Metal Gate Including Dielectric Gate Material
App 20150214331 - Jang; Linus ;   et al.
2015-07-30
Replacement metal gate FinFET
Grant 9,093,376 - Jagannathan , et al. July 28, 2
2015-07-28
Replacement Metal Gate Finfet
App 20150137245 - Jagannathan; Hemanth ;   et al.
2015-05-21
Replacement Metal Gate Finfet
App 20150137243 - Jagannathan; Hemanth ;   et al.
2015-05-21
Replacement Metal Gate Finfet
App 20150137244 - Jagannathan; Hemanth ;   et al.
2015-05-21
Spacer Replacement For Replacement Metal Gate Semiconductor Devices
App 20150024568 - Mehta; Sanjay C. ;   et al.
2015-01-22
Method to enable compressively strained pFET channel in a FinFET structure by implant and thermal diffusion
Grant 8,900,973 - Berliner , et al. December 2, 2
2014-12-02
Spacer Replacement For Replacement Metal Gate Semiconductor Devices
App 20140295637 - Mehta; Sanjay C. ;   et al.
2014-10-02
Replacement Metal Gate Finfet
App 20140110784 - Jagannathan; Hemanth ;   et al.
2014-04-24
Replacement Metal Gate Finfet
App 20140110785 - Jagannathan; Hemanth ;   et al.
2014-04-24
Cmos Transistors Having Differentially Stressed Spacers
App 20130134523 - ADAM; LAHIR S. ;   et al.
2013-05-30
Method To Enable Compressively Strained Pfet Channel In A Finfet Structure By Implant And Thermal Diffusion
App 20130052801 - Berliner; Nathaniel C. ;   et al.
2013-02-28
Insulating Region For A Semiconductor Substrate
App 20130049172 - Loubet; Nicolas ;   et al.
2013-02-28
Fabrication of CMOS transistors having differentially stressed spacers
Grant 8,372,705 - Adam , et al. February 12, 2
2013-02-12
Fabrication Of Cmos Transistors Having Differentially Stressed Spacers
App 20120187482 - Adam; Lahir S. ;   et al.
2012-07-26
Insulating Region For A Semiconductor Substrate
App 20120146175 - Loubet; Nicolas ;   et al.
2012-06-14
Reliable BEOL integration process with direct CMP of porous SiCOH dielectric
Grant 7,948,083 - Dimitrakopoulos , et al. May 24, 2
2011-05-24
Structure and method of chemically formed anchored metallic vias
Grant 7,517,736 - Mehta , et al. April 14, 2
2009-04-14
Hardmask for improved reliability of silicon based dielectrics
Grant 7,485,582 - Nguyen , et al. February 3, 2
2009-02-03
Method For Fabricating A Microelectronic Conductor Structure
App 20080160754 - Fitzsimmons; John A. ;   et al.
2008-07-03
Hardmask For Improved Reliability Of Silicon Based Dielectrics
App 20080132055 - Nguyen; Son Van ;   et al.
2008-06-05
Hardmask For Improved Reliability Of Silicon Based Dielectrics
App 20080118717 - Nguyen; Son Van ;   et al.
2008-05-22
METHOD OF FABRICATING A WIRE BOND PAD WITH Ni/Au METALLIZATION
App 20080073790 - Burrell; Lloyd G. ;   et al.
2008-03-27
Hardmask for reliability of silicon based dielectrics
Grant 7,335,980 - Nguyen , et al. February 26, 2
2008-02-26
Structure And Method Of Chemically Formed Anchored Metallic Vias
App 20080012142 - Mehta; Sanjay C. ;   et al.
2008-01-17
Method of fabricating a wire bond pad with Ni/Au metallization
Grant 7,294,565 - Burrell , et al. November 13, 2
2007-11-13
RELIABLE BEOL INTEGRATION PROCESS WITH DIRECT CMP OF POROUS SiCOH DIELECTRIC
App 20070228570 - Dimitrakopoulos; Christos D. ;   et al.
2007-10-04
Reliable BEOL integration process with direct CMP of porous SiCOH dielectric
Grant 7,253,105 - Dimitrakopoulos , et al. August 7, 2
2007-08-07
Preventing Damage To Interlevel Dielectric
App 20070072412 - Dunn; Derren N. ;   et al.
2007-03-29
Reliable BEOL integration process with direct CMP of porous SiCOH dielectric
App 20060189133 - Dimitrakopoulos; Christos D. ;   et al.
2006-08-24
Hardmask for improved reliability of silicon based dielectrics
App 20060091559 - Nguyen; Son Van ;   et al.
2006-05-04
Novel integration of wire bond pad with Ni/Au metallization
App 20050074959 - Burrell, Lloyd G. ;   et al.
2005-04-07

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