U.S. patent application number 13/921032 was filed with the patent office on 2013-10-24 for through via process.
The applicant listed for this patent is Taiwan Semiconductor Manufacturing Co., Ltd.. Invention is credited to Wen-Chih CHIOU, Jung-Chih HU, Weng-Jin WU, Chen-Hua YU.
Application Number | 20130277844 13/921032 |
Document ID | / |
Family ID | 41052770 |
Filed Date | 2013-10-24 |
United States Patent
Application |
20130277844 |
Kind Code |
A1 |
CHIOU; Wen-Chih ; et
al. |
October 24, 2013 |
THROUGH VIA PROCESS
Abstract
A semiconductor component having a semiconductor substrate
including an integrated circuit (IC) component, an interlayer
dielectric (ILD) layer formed on the semiconductor substrate, a
contact plug formed in the ILD layer and electrically connected to
the IC component, a via plug formed in the ILD layer and extending
through a portion of the semiconductor substrate, wherein the top
surfaces of the ILD layer, the via plug and the contact plug are
leveled off, and an interconnection structure comprising a
plurality of metal layers formed in a plurality of inter-metal
dielectric (IMD) layers, wherein a lowermost metal layer of the
interconnection structure is electrically connected to the exposed
portions of the contact plug and the via plug.
Inventors: |
CHIOU; Wen-Chih; (Toufen
Township, TW) ; YU; Chen-Hua; (Hsinchu City, TW)
; WU; Weng-Jin; (Hsinchu City, TW) ; HU;
Jung-Chih; (Yangmei Township, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Taiwan Semiconductor Manufacturing Co., Ltd. |
Hsin-Chu |
|
TW |
|
|
Family ID: |
41052770 |
Appl. No.: |
13/921032 |
Filed: |
June 18, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12044008 |
Mar 7, 2008 |
8486823 |
|
|
13921032 |
|
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Current U.S.
Class: |
257/758 |
Current CPC
Class: |
H01L 25/50 20130101;
H01L 2924/3011 20130101; H01L 23/481 20130101; H01L 2924/0002
20130101; H01L 2225/06513 20130101; H01L 2924/00 20130101; H01L
2225/06541 20130101; H01L 2924/0002 20130101; H01L 21/76898
20130101 |
Class at
Publication: |
257/758 |
International
Class: |
H01L 23/48 20060101
H01L023/48 |
Claims
1. A semiconductor component, comprising: a semiconductor substrate
including an integrated circuit (IC) component, an interlayer
dielectric (ILD) layer formed on said semiconductor substrate; a
contact plug formed in said ILD layer and electrically connected to
said IC component; a via plug formed in said ILD layer and
extending through a portion of said semiconductor substrate,
wherein the top surfaces of said ILD layer, said via plug and said
contact plug are leveled off; and an interconnection structure
comprising a plurality of metal layers formed in a plurality of
inter-metal dielectric (IMD) layers, wherein a lowermost metal
layer of said interconnection structure is electrically connected
to the exposed portions of said contact plug and said via plug.
2. The semiconductor component of claim 1, wherein said via plug
comprises copper or copper-based alloy.
3. The semiconductor component of claim 1, wherein said contact
plug is formed of tungsten or tungsten-based alloy.
4. The semiconductor component of claim 1, further comprising a
passivation layer lining the bottom and sidewalls of said via
plug.
5. The semiconductor component of claim 4, where said passivation
layer comprises silicon oxide, silicon nitride, or combinations
thereof.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a Divisional of application Ser. No.
12/044,008, filed on Mar. 7, 2008, the entirety of which is
incorporated by reference herein.
TECHNICAL FIELD
[0002] The present invention relates to stacked integrated
circuits, and particularly to a through via process for wafer-level
stacking technology.
BACKGROUND
[0003] Three-dimensional (3D) wafer-to-wafer vertical stack
technology seeks to achieve the long-awaited goal of vertically
stacking many layers of active IC devices such as processors,
programmable devices and memory devices inside a single chip to
shorten average wire lengths, thereby reducing interconnect RC
delay and increasing system performance. One major challenge of 3D
interconnects on a single wafer or in a wafer-to-wafer vertical
stack is through-via that provides a signal path for high impedance
signals to traverse from one side of the wafer to the other.
Through silicon via (TSV) is typically fabricated to provide the
through-via filled with a conducting material that pass completely
through the layer to contact and connect with the other TSVs and
conductors of the bonded layers. Examples of methods forming TSVs
after the first interconnect metallization process are described in
U.S. Pat. No. 6,642,081 to Patti and U.S. Pat. No. 6,897,125 to
Morrow, et al. One disadvantage is that the density of the via is
typically less because of etch and design limitations, potentially
creating connection, contact, and reliability problems. An
additional limitation to current TSV systems and methods is the
limited availability for thermal dissipation. Therefore, should
there be a desire to design TSVs for thermal dissipation, those
TSVs will typically occupy the area for normal design, since the
contact and metallization layers are already in place. The article
entitled: "Three-Dimensional Integrated Circuits and the Future of
System-on-Chip Designs", by Robert S. Patti, Proceedings of the
IEEE, pp. 1214-1224, Vol. 94, No. 6, June 2006, (incorporated
herein by reference), presents examples of super-contact processes
forming tungsten-filled TSVs before the contact process. The
super-contact process may impact precision in photolithography and
deposition during the subsequent contact process due to stress
induced by the huge tungsten-filled TSV.
SUMMARY OF THE INVENTION
[0004] Embodiments of the present invention include a through via
process performed after a contact process before a first-level
interconnection process.
[0005] In one aspect, the present invention provides a
semiconductor component including a semiconductor substrate with an
integrated circuit (IC) component formed thereon, an interlayer
dielectric (ILD) layer formed on the semiconductor substrate, a
contact plug formed in the ILD layer and electrically connected to
the IC component, a via plug formed in the ILD layer and extending
through a portion of the semiconductor substrate, and an
interconnection structure comprising a plurality of metal layers
formed in a plurality of inter-metal dielectric (IMD) layers. The
top surfaces of the ILD layer, the via plug and the contact plug
are leveled off. A lowermost metal layer of the interconnection
structure is electrically connected to the exposed portions of the
contact plug and the via plug.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] The aforementioned objects, features and advantages of this
invention will become apparent by referring to the following
detailed description of the preferred embodiments with reference to
the accompanying drawings, wherein:
[0007] FIGS. 1.about.10 are cross-sectional diagrams illustrating
an exemplary embodiment of a portion of a semiconductor device at
stages in an integrated circuit manufacturing process.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
[0008] Preferred embodiments of the present invention provide a
through via process performed after a contact process before a
first-level interconnection process. As used throughout this
disclosure, the term "through via" refers to a metal-filled via
passing through at least a part of a semiconductor substrate. The
through via process of the present invention can be called a
through-silicon via (TSV) process when the process is directed to
form a metal-filled via passing through a part of a
silicon-containing semiconductor substrate. The term "first-level
interconnection" refers to a lowermost metal layer patterned in a
lowermost inter-metal dielectric (IMD) layer overlying contact
structures and transistors.
[0009] Reference will now be made in detail to the present
embodiments, examples of which are illustrated in the accompanying
drawings. Wherever possible, the same reference numbers are used in
the drawings and the description to refer to the same or like
parts. In the drawings, the shape and thickness of one embodiment
may be exaggerated for clarity and convenience. This description
will be directed in particular to elements forming part of, or
cooperating more directly with, apparatus in accordance with the
present invention. It is to be understood that elements not
specifically shown or described may take various forms well known
to those skilled in the art. Further, when a layer is referred to
as being on another layer or "on" a substrate, it may be directly
on the other layer or on the substrate, or intervening layers may
also be present.
[0010] In an exemplary embodiment, FIGS. 1.about.10 show
cross-sectional views of a portion of a semiconductor device at
stages in an integrated circuit manufacturing process. With
reference now to FIG. 1, there is shown a cross-sectional diagram
of a wafer 100 comprising a semiconductor substrate 10, an IC
component 200 processed from the substrate 10, an inter-layer
dielectric (ILD) layer 12 overlying the semiconductor substrate 10,
and a contact plug 14 formed in the dielectric layer 12
electrically connected with the IC component 200. In detail, the
substrate 10 is typically silicon (Si), for example, a silicon
substrate with or without an epitaxial layer, or a
silicon-on-insulator substrate containing a buried insulator layer.
The substrate 10 may also be made of gallium arsenide (GaAs),
gallium arsenide-phosphide (GaAsP), indium phosphide (InP), gallium
aluminum arsenic (GaAlAs), indium gallium phosphide (InGaP). The IC
component 200 may comprise multiple individual circuit elements
such as transistors, diodes, resistors, capacitors, inductors, and
other active and passive semiconductor devices formed by
conventional processes known in the integrated circuit
manufacturing art.
[0011] The ILD layer 12 is formed on the substrate 10 so as to
isolate the IC component 200 from a subsequent formation of an
interconnection structure. The ILD layer 12 may be a single layer
or a multi-layered structure. The ILD layer 12 may be a silicon
oxide containing layer formed of doped or undoped silicon oxide by
a thermal CVD process or high-density plasma (HDP) process, e.g.,
undoped silicate glass (USG), phosphorous doped silicate glass
(PSG) or borophosphosilicate glass (BPSG). Alternatively, the ILD
layer 12 may be formed of doped or P-doped spin-on-glass (SOG),
PTEOS, or BPTEOS. Following a dry etching process carried out, a
contact hole is formed in the ILD layer 12, and a conductive
material layer is deposited to fill the contact hole, forming a
contact plug 14. The contact plug 14 may be formed of tungsten,
tungsten-based alloy, copper, or copper-based alloy.
[0012] Referring to FIGS. 2.about.4, following planarization, e.g.,
chemical mechanical planarization (CMP) on the ILD layer 12, a
lithographically patterned photoresist layer 16 is provided. A dry
etching process is then carried out to form at least one via hole
18 that passes through the ILD layer 12 and extends to reach a
predetermined depth of the substrate 10. Then the patterned
photoresist layer 16 is stripped.
[0013] Referring to FIG. 5, a passivation layer 20 is conformally
deposited on the wafer 100 to line the sidewalls and bottom of the
via holes 18 in order to prevent any conducting material from
leaching into any active portions of the circuitry of the wafer
100. The passivation layer 20 may be formed of silicon oxide,
silicon nitride, combinations thereof, or the like. A conductive
material layer 22 is then deposited on the passivation layer 20 of
the wafer 100, as shown in FIG. 6, to fill the via holes 18. The
conductive material layer 22 may include a diffusion barrier layer
and a metal layer. For example, a diffusion barrier layer is
conformally deposited along the bottom and sidewalls of the via
hole 18 followed by a metal-fill process, thus providing both an
excellent diffusion barrier in combination with good conductivity.
The diffusion barrier layer may include, but is not limited to, a
refractory material, TiN, TaN, Ta, Ti, TiSN, TaSN, W, WN, Cr, Nb,
Co, Ni, Pt, Ru, Pd, Au, CoP, CoWP, NiP, NiWP, mixtures thereof, or
other materials that can inhibit diffusion of copper into the ILD
layer 12 by means of PVD, CVD, ALD or electroplating. The metal
layer may include a low resistivity conductor material selected
from the group of conductor materials including, but is not limited
to, copper and copper-based alloy. For example, a copper-fill
process includes metal seed layer deposition and copper
electrochemical plating. Alternatively, the metal layer may
comprise various materials, such as tungsten, aluminum, gold,
silver, and the like.
[0014] Referring to FIG. 7, after removing the excess portions of
the conductive material layer 22 and the passivation layer 20
outside the via holes 18, either through etching, chemical
mechanical polishing (CMP), or the like, the wafer 100 now
comprises via plugs 22a passing through the ILD layer 12 and
extending through a portion of the substrate 10.
[0015] Next, back-end-of-line (BEOL) interconnection technologies
are processed on the wafer 100 to fabricate an interconnection
structure including a plurality of interconnection layers and
inter-metal dielectric (IMD) layers. As illustrated in FIG. 8, a
first-level interconnection layer 26 is formed in an IMD layer 24
to electrically connect with the contact plug 14 and the via plugs
22a respectively. Thereafter, another level interconnection layers
and IMD layers are fabricated on the first-level interconnection
layer 26, which are omitted in the drawings for clarity and
convenience. Embodiments of the present invention use copper-based
conductive materials for forming the interconnection layers. The
copper-based conductive material is intended to include
substantially pure elemental copper, copper containing unavoidable
impurities, and copper alloys containing minor amounts of elements
such as tantalum, indium, tin, zinc, manganese, chromium, titanium,
germanium, strontium, platinum, magnesium, aluminum or zirconium. A
standard damascene process may be used with the copper BEOL
interconnection. Although the embodiments of the present invention
illustrate copper interconnection patterns, the present invention
also provides value when using metallic materials excluding copper
for BEOL interconnection.
[0016] Referring to FIG. 9, bonding contacts 28 are formed in an
insulating layer 30 overlying a completed top-level interconnect
layer and a top-level IMD layer. The insulating layer 30 may be
removed or etched to reveal the bonding contacts 28 slightly
elevated above the top of insulating layer 30. The bonding contacts
28 may be formed of copper-based conductive materials. The
insulating layer 30 can insulate the IC component 200 from any
other circuitry or devices in any wafers bonded to the wafer
100.
[0017] FIG. 10 illustrates the cross-section of the wafer 100
stacked and bonded to another wafer 300. The wafer 300 comprises a
substrate 40, an insulating layer 42, an IMD layer 44 and bonding
pads 46. The wafers 100 and 300 are bonded together at the bonding
contacts 28 and the bonding pads 46 to form a three-dimensional
stacked wafer. It should be noted that any number of different
devices, components, connectors, and the like, might be integrated
into the wafers 100 and 300. The specific devices or lack of
devices that may be illustrated herein are not intended to limit
the embodiments of the present invention in any way.
[0018] Compared with existing methods for forming TSV in
semiconductor devices, the through via process according to the
embodiment of the present invention eliminates the impact on
precision of photolithography, etching and deposition during the
contact process, and results in advantages of lower through-via Rc,
higher through-via density, a minimum need for keep-out zone,
routing freedom for interconnection metal layers and better
yields.
[0019] Although the present invention has been described in its
preferred embodiments, it is not intended to limit the invention to
the precise embodiments disclosed herein. Those skilled in this
technology can still make various alterations and modifications
without departing from the scope and spirit of this invention.
Therefore, the scope of the present invention shall be defined and
protected by the following claims and their equivalents.
* * * * *