U.S. patent application number 13/245181 was filed with the patent office on 2012-01-19 for packaging structure and method.
This patent application is currently assigned to STATS CHIPPAC, LTD.. Invention is credited to Nazir Ahmad, Kyung-Moon Kim, Young-Do Kwon, Rajendra D. Pendse, Samuel Tam.
Application Number | 20120013005 13/245181 |
Document ID | / |
Family ID | 26884224 |
Filed Date | 2012-01-19 |
United States Patent
Application |
20120013005 |
Kind Code |
A1 |
Ahmad; Nazir ; et
al. |
January 19, 2012 |
Packaging Structure and Method
Abstract
A method of making a semiconductor device includes providing a
substrate and forming a conductive layer on the substrate. The
conductive layer includes a first metal. A semiconductor die is
provided. A bump is formed on the semiconductor die. The bump
includes a second metal. The semiconductor die is positioned
proximate to the substrate to contact the bump to the conductive
layer and form a bonding interface. The bump and the conductive
layer are metallurgically reacted at a melting point of the first
metal to dissolve a portion of the second metal from an end of the
bump. The bonding interface is heated to the melting point of the
first metal for a time sufficient to melt a portion of the first
metal from the conductive layer. A width of the conductive layer is
no greater than a width of the bump.
Inventors: |
Ahmad; Nazir; (San Jose,
CA) ; Kwon; Young-Do; (Cupertino, CA) ; Tam;
Samuel; (Daly City, CA) ; Kim; Kyung-Moon;
(Kyoung ki-do, KR) ; Pendse; Rajendra D.;
(Fremont, CA) |
Assignee: |
STATS CHIPPAC, LTD.
Singapore
SG
|
Family ID: |
26884224 |
Appl. No.: |
13/245181 |
Filed: |
September 26, 2011 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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12472083 |
May 26, 2009 |
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13245181 |
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Current U.S.
Class: |
257/737 ;
257/E21.506; 257/E23.021; 438/615 |
Current CPC
Class: |
H01L 2924/01033
20130101; H01L 2224/81801 20130101; H01L 2224/83194 20130101; H01L
2924/07802 20130101; H01L 2224/16145 20130101; H01L 2924/01029
20130101; H01L 2224/2919 20130101; H01L 2924/01006 20130101; H01L
2224/16225 20130101; H01L 2924/0132 20130101; H01L 2924/00
20130101; H01L 2924/00012 20130101; H01L 2924/01079 20130101; H01L
2224/13144 20130101; H01L 2924/01028 20130101; H01L 2924/0105
20130101; H01L 2224/13147 20130101; H01L 2924/00 20130101; H01L
2924/0105 20130101; H01L 2924/00 20130101; H01L 2924/00 20130101;
H01L 2924/00014 20130101; H01L 2924/01079 20130101; H01L 2924/01076
20130101; H01L 2224/16225 20130101; H01L 2224/13147 20130101; H01L
2924/181 20130101; H01L 2224/81203 20130101; H01L 2924/0105
20130101; H01L 2224/1134 20130101; H01L 24/81 20130101; H01L
2924/01079 20130101; H01L 2224/2919 20130101; H01L 2924/014
20130101; H01L 2224/73203 20130101; H01L 2924/0132 20130101; H01L
2924/01058 20130101; H01L 2924/07802 20130101; H01L 21/563
20130101; H01L 2224/29144 20130101; H01L 2224/10135 20130101; H01L
2224/83102 20130101; H01L 2224/29111 20130101; H01L 2224/83191
20130101; H01L 2924/181 20130101; H01L 2224/92125 20130101; H01L
2924/0132 20130101; H01L 2224/81139 20130101; H01L 2224/29144
20130101; H01L 24/29 20130101; H01L 2224/13144 20130101; H01L
2924/01082 20130101; H01L 2224/16225 20130101 |
Class at
Publication: |
257/737 ;
438/615; 257/E23.021; 257/E21.506 |
International
Class: |
H01L 23/48 20060101
H01L023/48; H01L 21/60 20060101 H01L021/60 |
Claims
1. A method of making a semiconductor device, comprising: providing
a substrate; forming a conductive layer on the substrate, the
conductive layer including a first metal; providing a semiconductor
die; forming a bump on the semiconductor die, the bump including
gold; positioning the semiconductor die proximate to the substrate
to contact the bump to the conductive layer and form a bonding
interface; heating the bonding interface to a melting point of the
first metal for a time sufficient to melt a portion of the first
metal from the conductive layer; metallurgically reacting the bump
and the conductive layer at the melting point of the first metal to
dissolve a portion of the gold from an end of the bump; and forming
a bonding phase at the bonding interface by mixing a dissolved
portion of the gold from the end of the bump with a molten portion
of the first metal.
2. The method of claim 1, wherein the first metal includes tin.
3. The method of claim 2, wherein forming the bonding phase further
includes mixing the dissolved portion of the gold with the molten
portion of the tin to create a Au/Sn alloy composition of about
4:1.
4. The method of claim 1, wherein metallurgically reacting the bump
and the conductive layer includes increasing a temperature at the
bonding interface above the melting point of the first metal.
5. The method of claim 1, further including forming the bump such
that a width of the bump is greater than a width of the conductive
layer.
6. The method of claim 1, wherein metallurgically reacting the bump
and the conductive layer includes increasing the temperature at the
bonding phase.
7. A method of making a semiconductor device, comprising: providing
a substrate; forming a conductive layer on the substrate, the
conductive layer including a first metal; providing a semiconductor
die; forming a bump on the semiconductor die, the bump including a
second metal; positioning the semiconductor die proximate to the
substrate to contact the bump to the conductive layer and form a
bonding interface; metallurgically reacting the bump and the
conductive layer at a melting point of the first metal to dissolve
a portion of the second metal from an end of the bump; and forming
a bonding phase at the bonding interface by mixing a dissolved
portion of the second metal from the end of the bump with a molten
portion of the first metal.
8. The method of claim 7, further including heating the bonding
interface to the melting point of the first metal for a time
sufficient to melt a portion of the first metal from the conductive
layer.
9. The method of claim 8, wherein the second metal is gold.
10. The method of claim 9, wherein the first metal is tin.
11. The method of claim 10, wherein heating the bonding interface
includes heating to a temperature of about 232 degrees C. for a
duration of 1 to 2 seconds.
12. The method of claim 11, wherein metallurgically reacting the
first and second metals includes mixing the first metal with the
second metal in the bonding interface to create a 4:1 alloy
composition.
13. A method of making a semiconductor device, comprising:
providing a substrate; forming a conductive layer on the substrate,
the conductive layer including a first metal; providing a
semiconductor die; forming a bump on the semiconductor die, the
bump including a second metal; positioning the semiconductor die
proximate to the substrate to contact the bump to the conductive
layer and form a bonding interface; and metallurgically reacting
the bump and the conductive layer at a melting point of the first
metal to dissolve a portion of the second metal from an end of the
bump.
14. The method of claim 13, further including heating the bonding
interface to the melting point of the first metal for a time
sufficient to melt a portion of the first metal from the conductive
layer.
15. The method of claim 14, further including forming a bonding
phase at the bonding interface by mixing a dissolved portion of the
second metal from the end of the bump with a molten portion of the
first metal.
16. The method of claim 15, wherein forming the bonding phase
further includes mixing a dissolved portion of the second metal
with a molten portion of the first metal.
17. The method of claim 16, wherein mixing the dissolved portion of
the second metal with the molten portion of the first metal
includes forming an alloy of the first and second metals at the
bonding interface.
18. The method of claim 16, wherein heating the bonding interface
to the melting point of the first metal includes heating to a
temperature of about 232 degrees C. for a duration of 1 to 2
seconds.
19. The method of claim 18, wherein the alloy comprises gold and
tin.
20. The method of claim 13, wherein a width of the conductive layer
is no greater than a width of the bump.
21. A semiconductor device, comprising: a substrate; a conductive
layer formed on the substrate, the conductive layer including a
first metal; a bump connected to the conductive layer by a bonding
phase disposed between the bump and the conductive layer, the bump
including a second metal, the bonding phase characterized as an
alloy of the first metal and the second metal, wherein the alloy is
formed by metallurgically reacting the bump and the conductive
layer at a melting point of the first metal to dissolve a portion
of the second metal from an end of the bump; and a semiconductor
die that is coupled to an end of the bump opposite the bonding
phase.
22. The semiconductor device of claim 21, wherein one of the first
and second metals is gold (Au).
23. The semiconductor device of claim 22, wherein another one of
the first and second metals is tin (Sn).
24. The semiconductor device of claim 23, wherein a composition of
the alloy is about 4:1 Au/Sn.
25. The semiconductor device of claim 21, wherein the bonding phase
abuts the bump and the conductive layer.
Description
CLAIM TO DOMESTIC PRIORITY
[0001] The present application is a division of U.S. application
Ser. No. 12/472,083, filed May 26, 2009, and claims priority to the
foregoing parent application pursuant to 35 U.S.C. .sctn.120.
FIELD OF THE INVENTION
[0002] This invention relates to flip chip packaging and, more
particularly, to providing a Au/Sn alloy interconnection between a
chip and a substrate.
BACKGROUND OF THE INVENTION
[0003] Conventional methods for interconnecting a flip chip to a
substrate include an Anisotropic Conductive Film (ACF) with Ni or
Ni/Au coated polymer particles in which a contact type
interconnection is made. Fragments of the polymer film which remain
trapped at the interconnection point often lead to poor electrical
contact and reduced reliability of the package. Additionally, the
polymer film reduces the reliability of the bonding interface
during the chip bonding process. Conventional flip chip techniques
that use either ACF, Non-Conductive Adhesive (NCA) or Non
Conductive Polymer (NCP) also suffer from problems in curing the
adhesive on adjacent bonding sites on a substrate during the chip
bonding process.
SUMMARY OF THE INVENTION
[0004] What is needed is a flip chip structure and method that
provides for metallurgical interconnection between the flip chip
and the substrate and that further provides for improved bonding
between the chip and the substrate. Accordingly, in one embodiment,
the present invention is a method of making a semiconductor device
comprising the steps of providing a substrate, and forming a
conductive layer on the substrate. The conductive layer includes a
first metal. A semiconductor die is provided. A bump is formed on
the semiconductor die. The bump includes gold. The semiconductor
die is positioned proximate to the substrate to contact the bump to
the conductive layer and form a bonding interface. The bonding
interface is heated to a melting point of the first metal for a
time sufficient to melt a portion of the first metal from the
conductive layer. The bump and the conductive layer are
metallurgically reacted at the melting point of the first metal to
dissolve a portion of the gold from an end of the bump. A bonding
phase is formed at the bonding interface by mixing a dissolved
portion of the gold from the end of the bump with a molten portion
of the first metal.
[0005] In another embodiment, the present invention is a method of
making a semiconductor device comprising the steps of providing a
substrate, and forming a conductive layer on the substrate. The
conductive layer includes a first metal. A semiconductor die is
provided. A bump is formed on the semiconductor die. The bump
includes a second metal. The semiconductor die is positioned
proximate to the substrate to contact the bump to the conductive
layer and form a bonding interface. The bump and the conductive
layer are metallurgically reacted at a melting point of the first
metal to dissolve a portion of the second metal from an end of the
bump. A bonding phase is formed at the bonding interface by mixing
a dissolved portion of the second metal from the end of the bump
with a molten portion of the first metal.
[0006] In another embodiment, the present invention is method of
making a semiconductor device comprising the steps of providing a
substrate, and forming a conductive layer on the substrate. The
conductive layer includes a first metal. A semiconductor die is
provided. A bump is formed on the semiconductor die. The bump
includes a second metal. The semiconductor die is positioned
proximate to the substrate to contact the bump to the conductive
layer and form a bonding interface. The bump and the conductive
layer are metallurgically reacted at a melting point of the first
metal to dissolve a portion of the second metal from an end of the
bump.
[0007] In another embodiment, the present invention is a
semiconductor device comprising a substrate and a conductive layer
formed on the substrate. The conductive layer includes a first
metal. A bump is connected to the conductive layer by a bonding
phase disposed between the bump and the conductive layer. The bump
includes a second metal. The bonding phase is characterized as an
alloy of the first metal and the second metal. The alloy is formed
by metallurgically reacting the bump and the conductive layer at a
melting point of the first metal to dissolve a portion of the
second metal from an end of the bump. A semiconductor die is
coupled to an end of the bump opposite the bonding phase.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIGS. 1A and 1B are diagrammatic sketches in a sectional
view showing an illustrative embodiment of stages according to the
invention for making a packaging structure according to the
invention.
DETAILED DESCRIPTION OF THE DRAWINGS
[0009] A description of an exemplary embodiment of the invention
follows. Using the disclosure herein, substantially conventional
apparatus can be modified for use in the process of the
invention.
[0010] In one general aspect the invention features a method for
providing metallurgic connection between a flip chip and a
substrate, by providing a chip having a set of bumps formed on a
bump side thereof, providing a substrate having a set of
interconnect points on a metallization thereon, providing a
measured quantity of a polymer adhesive in a middle region of the
chip on the bump side, aligning the chip with the substrate so that
the set of bumps aligns with the set of interconnect points,
pressing the chip and the substrate toward one another so that a
portion of the polymer adhesive contacts the substrate and the
bumps contact the interconnect points, and heating the bumps to a
temperature sufficiently high to form a metallurgical connection
between the bumps and the interconnect points.
[0011] In some embodiments the bumps are stud bumps, and are formed
of gold; and the interconnect points include spots of tin,
preferably pure tin, on the metallization. In other embodiments the
bumps are formed of a metal such as, for example, copper plated
with Au or with Ni/Au or electroless Ni/Au; and the interconnect
points also may include such materials. In embodiments in which the
stud bumps are made of Au and the interconnect points are spots of
Sn, the heating step raises the temperature of the bumps
sufficiently to create an alloy between the Au and the Sn in a
bonding phase at the interface; in preferred embodiments the
bonding phase comprises a 80:20 Au:Sn alloy. For such an alloy the
bumps may be sufficiently heated by heating the die to a
temperature greater than about 200.degree. C., preferably about
232.degree. C.
[0012] In some embodiments the method further includes underfilling
with a polymer.
[0013] In another general aspect the invention features a chip
package structure made according to the method.
[0014] In another general aspect the invention features a chip
package structure including a chip having a bumps formed thereon
and a substrate having interconnect points on a metallization
thereon, the bumps forming contacts with the interconnect points,
in which an alloy is formed at an interface between the material of
each bump and the material of the interconnect in contact with the
bump.
[0015] In some embodiments a cured adhesive polymer is situated in
a middle region between the bump surface of the chip and the
surface of the substrate.
[0016] In some embodiments the bump material is gold or is a metal
such as copper plated with gold or with Ni/Au or with electroless
Ni/Au; and the interconnect points also include such materials. In
some embodiments the alloy at the interface is an alloy of Au and
Sn, and preferably the alloy is a 20:80 Sn:Au alloy.
[0017] With reference to the Figs., there are shown in FIG. 1A a
chip and a substrate in alignment prior to forming the interconnect
according to the invention, and in FIG. 1B a completed
interconnect. The flip chip configuration, shown generally at 10,
includes a plurality of bumps, e.g. 14, formed on the chip 12, the
bumps preferably being gold (Au) stud bumps. The corresponding
interconnection points, on a standard substrate 16 metallization
are provided with a plurality of preferably pure tin (Sn) spots 18.
A central area 20 of the chip on a bump side 22 further includes a
spot of adhesive 24 small enough that it does not spread to the
gold studs and the interconnection area during a subsequent bonding
process. As the chip is connected to the substrate in the flip chip
format, the adhesive holds the chip to the substrate and the ends
of the stud bumps 14 react with the pure tin spots 18 on the
substrate to make metallurgical interconnections 26.
[0018] A substrate strip populated with a row or an array of chips
assembled in this manner can be molded using simple tooling,
readily adapted from conventional equipment. The molding preferably
provides die underfilling and molding compound along the perimeters
of the die simultaneously. Solder balls can then be attached and
the completed chips can be singularized by, for example, sawing the
substrate.
[0019] The flip chip is aligned with the substrate in such a manner
that the gold stud bumps on the chip align with the tin spots on
the substrate. After alignment and contact between the Sn spots and
the Au stud bumps, the die is heated to a temperature and for a
time sufficient to give a metallurgical reaction at the interface
between the bumps and the spots, preferably in excess of about
200.degree. C. For an Au--Sn junction, a suitable temperature is
about 232.degree. C., and a suitable time is 1-2 seconds. At this
temperature, the Sn spots melt and the temperature at the bonding
interface increases significantly, thereby dissolving some Au from
both a metallization layer on the substrate and the stud bumps to
create a bonding phase at the interface between the Sn spots and
the Au stud bumps. Preferably a 80%:20% Au:Sn alloy composition is
formed at the interface. Such an alloy provides both reliable
electrical contact and advantageous mechanical properties.
[0020] As the Sn/Au interconnection is made the adhesive spot cures
to hold the die in space. A subsequent underfilling process of the
structure is thereby facilitated as the center region of the chip
is already filled with the adhesive polymer. Overmolding fills the
remaining space under the die and the space between the chips,
resulting in a robust structure.
[0021] An alternative embodiment provides for direct contact
between the gold stud bumps and a standard metallization on the
substrate. A metallization bondable to withstand the stresses of
subsequent processing is thereby formed as there is no interposing
polymer at the bonding interface during the chip bonding
process.
[0022] To achieve wafer scale packaging, a wafer having stud bumps
thereon is placed face up on a heating stage. Substrate pieces,
inspected and singulated, with appropriate amounts of adhesive are
then picked, aligned, placed and bonded to wafer sites applying
conventional process conditions of temperature and pressure.
Ultrasonic scrubbing may be employed to clean the substrate site
before thermal compression bonding. The disclosed process provides
for little waste of substrate material as only particular rejected
sites will be discarded, rather than the entire substrate strip.
Additionally, it is not necessary to bond to the rejected dies on
the wafer. After fully populating the wafer, the wafer is molded
for underfilling and interchip space filling. Dicing the wafer then
follows the molding and solder ball mounting steps to singulate the
dies.
[0023] In alternative embodiments the stud bumps include Cu plated
with Ni and Au, plated Au or electroless Ni/Au, and these materials
may be also provided on the bonding sites of the substrate. With
the advances in Cu terminal metallurgy, the bonding sites may be
finished with Ni and heavy soft Au, thereby providing for
interconnections between the wafer and substrate I/Os either by
thermal compression bonding utilizing Au or by fusion at low
temperatures utilizing Sn like metals to form suitable bonding
phases. Once metallurgical contacts are formed, the structure is
underfilled and transfer molded simultaneously.
[0024] Other embodiments are within the following claims.
* * * * *