U.S. patent application number 13/064878 was filed with the patent office on 2011-08-18 for method of manufacturing wafer level package including coating resin over the dicing lines.
This patent application is currently assigned to SAMSUNG ELECTRO-MECHANICS CO., LTD.. Invention is credited to Hyung Jin Jeon, Jin Gu Kim, Young Do Kweon, Hee Kon Lee, Seon Hee Moon, Seung Wook Park.
Application Number | 20110201156 13/064878 |
Document ID | / |
Family ID | 42266723 |
Filed Date | 2011-08-18 |
United States Patent
Application |
20110201156 |
Kind Code |
A1 |
Kim; Jin Gu ; et
al. |
August 18, 2011 |
Method of manufacturing wafer level package including coating resin
over the dicing lines
Abstract
A method of manufacturing a wafer level package including:
preparing a substrate wafer including a plurality of pads formed on
a bottom surface, a plurality of chips positioned on a top surface,
and dicing lines for dividing the chips; forming external
connection units on the pads; coating resin on the dicing lines by
positioning masks on the substrate wafer to expose only the dicing
lines; removing the masks; encapsulating the chips positioned
between the resin by coating the chips with encapsulant and cutting
a wafer level package along the dicing lines coated with the resin
into units.
Inventors: |
Kim; Jin Gu; (Suwon-si,
KR) ; Kweon; Young Do; (Seoul, KR) ; Jeon;
Hyung Jin; (Gunpo-si, KR) ; Park; Seung Wook;
(Seoul, KR) ; Lee; Hee Kon; (Hwaseong-si, KR)
; Moon; Seon Hee; (Seoul, KR) |
Assignee: |
SAMSUNG ELECTRO-MECHANICS CO.,
LTD.
Suwon
KR
|
Family ID: |
42266723 |
Appl. No.: |
13/064878 |
Filed: |
April 22, 2011 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12453273 |
May 5, 2009 |
7947530 |
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13064878 |
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Current U.S.
Class: |
438/114 ;
257/E21.499 |
Current CPC
Class: |
H01L 2924/09701
20130101; H01L 23/3121 20130101; H01L 23/24 20130101; H01L 2924/181
20130101; H01L 21/561 20130101; H01L 24/94 20130101; H01L 2924/00
20130101; H01L 2924/3511 20130101; H01L 2924/181 20130101 |
Class at
Publication: |
438/114 ;
257/E21.499 |
International
Class: |
H01L 21/50 20060101
H01L021/50 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 19, 2008 |
KR |
10-2008-0130219 |
Claims
1. A method of manufacturing a wafer level package comprising:
preparing a substrate wafer including a plurality of pads formed on
a bottom surface, a plurality of chips positioned on a top surface,
and dicing lines for dividing the chips; forming external
connection units on the pads; coating resin on the dicing lines by
positioning masks on the substrate wafer to expose only the dicing
lines; removing the masks; encapsulating the chips positioned
between the resin by coating the chips with encapsulant; and
cutting a wafer level package along the dicing lines coated with
the resin into units.
2. The method of claim 1, wherein the resin is formed of any one of
transparent photocurable, thermosetting, and thermoplastic resin in
the coating the resin on the dicing lines.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a U.S. divisional application filed
under 37 USC 1.53(b) claiming priority benefit of U.S. Ser. No.
12/453,273 filed in the United States on May 5, 2009, which claims
earlier priority benefit to Korean Patent Application No.
10-2008-0130219 filed with the Korean Intellectual Property Office
on Dec. 19, 2008, the disclosures of which are incorporated herein
by reference.
BACKGROUND
[0002] 1. Field
[0003] The present invention relates to a method of manufacturing a
wafer level package; and, more particularly, to a method of
manufacturing a wafer level package to coat resin on a dicing line
formed on a substrate wafer.
[0004] 2. Description of the Related Art
[0005] A conventional package is manufactured by cutting a wafer
having a plurality of chips along dicing lines to be divided into
individual chips and then performing a packaging process for each
of the individual chips.
[0006] However, because the packaging process includes a lot of
unit processes, e.g., chip attaching, wire bonding, molding,
trimming/forming or the like, a conventional method of
manufacturing the package to perform the packaging process by each
of the chips has a disadvantage of needing a very long time for
packaging all of the chips when considering the number of the chips
obtained from one wafer.
[0007] Therefore, recently, there has been suggested a wafer level
package method of manufacturing an individual package by firstly
performing the packaging process in a wafer level and then cutting
a wafer level package along dicing lines of a wafer.
[0008] In the wafer level package, it is general that after a
molding process is performed on the wafer provided with a chip or
the like by using molding resin such as EMC(Epoxy Mold Compound),
the surface of the molding resin is formed to be flat. However, if
the molding resin has the flat surface, the CTE(Coefficient of
Thermal Expansion) of the molding resin is more than double to ten
times the CTE of the wafer and so the molding resin may be
considerably contracted due to heat generated in the molding
process, which causes a warpage phenomenon where the wafer is
rolled and makes the dicing lines unseen.
SUMMARY
[0009] The present invention has been invented in order to overcome
the above-described problems and it is, therefore, an object of the
present invention to provide a method of manufacturing a wafer
level package capable of preventing a warpage phenomenon where a
wafer is rolled in an encapsulation process by coating resin on
dicing lines formed on a substrate wafer and of smoothly performing
dicing work by cutting a wafer level package along dicing lines
exposed by removing the resin.
[0010] In accordance with one aspect of the present invention to
achieve the object, there is provided a method of manufacturing a
wafer level package including the steps of: preparing a substrate
wafer including a plurality of pads formed on a bottom surface, a
plurality of chips positioned on a top surface, and dicing lines
for dividing the chips; forming external connection units on the
pads; coating resin on the dicing lines by positioning masks on the
substrate wafer to expose only the dicing lines; removing the
masks; encapsulating the chips positioned between the resin by
coating the chips with encapsulant; removing the resin coated on
the dicing lines; and cutting a wafer level package along the
dicing lines exposed by removing the resin into units.
[0011] Further, the resin can be formed of any one of transparent,
translucent, or opaque photocurable, thermosetting, and
thermoplastic resin in the step of coating the resin on the dicing
lines.
[0012] Further, the method further includes a step of: curing the
resin after the step of coating the resin on the dicing lines.
[0013] Further, the encapsulant can be formed of liquid resin or
solid epoxy mold compound in the step of encapsulating the chips on
the substrate with the encapsulant.
[0014] Further, the encapsulant can be coated by any one of
printing, dispensing, dipping, spin coating, compression molding,
and transfer molding in the step of encapsulating the chips on the
substrate with the encapsulant.
[0015] Further, the resin can be removed by a wet method or a
plasma method in the step of removing the resin coated on the
dicing lines.
[0016] In accordance with another aspect of the present invention
to achieve the object, there is provided a method of manufacturing
a wafer level package including the steps of: preparing a substrate
wafer including a plurality of pads formed on a bottom surface, a
plurality of chips positioned on a top surface, and dicing lines
for dividing the chips; forming external connection units on the
pads; coating resin on the dicing lines by positioning masks on the
substrate wafer to expose only the dicing lines; removing the
masks; encapsulating the chips positioned between the resin by
coating the chips with encapsulant; and cutting a wafer level
package along the dicing lines coated with the resin into
units.
[0017] Further, the resin can be formed of any one of transparent
photocurable, thermosetting, and thermoplastic resin in the step of
coating the resin on the dicing lines.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] These and/or other aspects and advantages of the present
general inventive concept will become apparent and more readily
appreciated from the following description of the embodiments,
taken in conjunction with the accompanying drawings of which:
[0019] FIGS. 1 to 8 are cross-sectional views sequentially
illustrating a method of manufacturing a wafer level package in
accordance with an embodiment of the present invention; and
[0020] FIG. 9 is a cross-sectional view illustrating a method of
manufacturing a wafer level package in accordance with another
embodiment of the present invention.
DESCRIPTION OF EMBODIMENTS
[0021] Hereinafter, a matter regarding to an operation effect
including a technical configuration for a method of manufacturing a
wafer level package in accordance with the present invention will
be appreciated clearly through the following detailed description
with reference to the accompanying drawings illustrating preferable
embodiments of the present invention.
[0022] Methods of manufacturing wafer level packages in accordance
with embodiments of the present invention will be described in
detail with reference to FIGS. 1 to 9.
[0023] FIGS. 1 to 8 are cross-sectional views sequentially
illustrating a method of manufacturing a wafer level package in
accordance with an embodiment of the present invention and FIG. 9
is a cross-sectional view illustrating a method of manufacturing a
wafer level package in accordance with another embodiment of the
present invention.
[0024] At first, as shown in FIG. 1, there is prepared a substrate
wafer 110 including a plurality of pads 113 formed on a bottom
surface, a plurality of chips 115 positioned on a top surface, and
dicing lines for dividing the chips 115.
[0025] At this time, the dicing lines are formed at equal intervals
in a row direction and a column direction in which the chips 115
are positioned and can be processed by any one of a sanding process
where the surface of the substrate wafer 110 is slightly cut or
carved, an etching process as a surface processing method applying
erosive action of chemical agents or an ultrasound process as
another surface processing method using ultrasound vibration.
[0026] And, inside the substrate wafer 110, there can be further
formed via holes(not shown in the drawings) for electrical
connection between the chips 115 and external connection units 120
to be formed on the pads 113 later.
[0027] Herein, material of the substrate wafer 110 as a substrate
used in a semiconductor process can be silicon, ceramic, glass,
polymer, and so on.
[0028] Then, as illustrated in FIG. 2, the external connection
units 120 are formed on the pads 113 of the substrate wafer 110.
The external connection units 120 can be solder balls which are
electrically connected through the medium of the pads 113. At this
time, the external connection units 120 can be formed of solder
bumps with another shape other than the solder balls.
[0029] Then, as shown in FIG. 3, resin 140a is coated on the dicing
lines after positioning masks 130 on the substrate wafer 110 to
expose only the dicing lines. At this time, the resin 140a coated
on the surfaces of the masks 130 is pushed in the dicing lines with
a squeeze 142 to be uniformly coated. And, any one of a mask
patterned by photoresist or a screen printing mask can be used as
the mask. Further, it is preferable that the resin 140a and 140b is
formed of any one of transparent, translucent, or opaque
photocurable, thermosetting, and thermoplastic resin.
[0030] Then, as illustrated in FIGS. 4 and 5, after curing the
resin 140a for a predetermined time, the masks 130 are removed. At
this time, the resin 140a is cured by irradiating ultraviolet rays
through a UV curing system or applying heat at more than a
predetermined temperature. Therefore, the resin 140a is firmly
fixed between the chips 115 positioned on the substrate wafer 110,
i.e., on the dicing lines for dividing the chips 115.
[0031] Then, as shown in FIG. 6, the chips 115 positioned between
the resin 140a are encapsulated by being coated with encapsulant
150 in order to finish a wafer level package. The encasulant 150
can be made of liquid resin, solid epoxy mold compound, or the like
and the encapsulant can be coated by any one of printing,
dispensing, dipping, spin coating, compression molding, and
transfer molding.
[0032] At this time, the resin 140a formed on the dicing lines for
dividing the chips 115 narrows a region where stress generated due
to a CTE(Coefficient of Thermal Expansion) difference between the
encapsulant 150 and the substrate wafer 110 is transmitted in order
to reduce the stress so that power contracting the substrate wafer
110 in an encapsulation process can be distributed. Therefore, it
is possible to improve a warpage phenomenon of the substrate wafer
110.
[0033] Then, as shown in FIG. 7, the resin 140a is removed. At this
time, the resin 140a can be removed by a wet method using chemical
agents such as permanganate or a plasma method using plasma as an
aggregate of particles consisting of ion-nuclei and free electrons,
which is formed by continuing to apply heat to material of a
gaseous state in order to increase a temperature.
[0034] However, in case that the resin 140b is coated on the dicing
lines by using any one of the transparent photocurable,
thermosetting, and thermoplastic resin in a step of coating the
resin on the dicing lines, dicing work can be performed along the
dicing lines coated with the resins 140 without removing the resin
140b as shown in FIG. 9. In this case, a process before the step of
coating the resin 140b on the dicing lines is performed similarly,
while a step of removing the resins 140b is omitted, thereby
enhancing workability and productivity.
[0035] Then, as shown in FIG. 8, the wafer level package is cut
along the dicing lines exposed by removing the resins 140a into
units. Accordingly, dicing work can be smoothly accomplished by
cutting it along the exposed dicing lines.
[0036] And, the dicing work of the wafer level package is performed
with a dicing blade(not shown in the drawings), wherein the dicing
blade is a semiconductor wafer processing device capable of exactly
cutting a subject at a high speed without attaching shavings to a
cutting surface. As described above, if the wafer level package is
diced along the exposed dicing lines, a region to be diced by the
dicing blade is reduced in order to reduce pressure applied to the
dicing blade, thereby increasing durability and wear resistance of
the dicing blade.
[0037] As described above, the method of manufacturing the wafer
level package in accordance with the present invention can narrow
the region where the stress generated due to the CTE difference
between the encapsulant 150 and the substrate wafer 110 is
transmitted in the encapsulation process in order to reduce the
stress by coating the resin 140a and 140b on the dicing lines
formed on the substrate wafer 110, so that the power by which the
substrate wafer 110 is contracted can be distributed in order to
improve the warpage phenomenon of the substrate wafer 110.
[0038] Further, thereafter, in case that the resin 140a is removed,
the dicing work can be smoothly accomplished by cutting it along
the exposed dicing lines, thereby remarkably enhancing quality and
yield of the wafer level package. Consequently, the workability and
the productivity of the wafer level package can be enhanced.
[0039] As described above, although the preferable embodiments of
the present invention have been shown and described, it will be
appreciated by those skilled in the art that substitutions,
modifications and changes may be made in this embodiment without
departing from the principles and spirit of the general inventive
concept, the scope of which is defined in the appended claims and
their equivalents.
* * * * *