U.S. patent application number 12/151483 was filed with the patent office on 2008-09-04 for reducing oxidation under a high k gate dielectric.
Invention is credited to Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Jack Kavalieros, Matthew V. Metz, Uday Shah, Robert B. Turkot.
Application Number | 20080211033 12/151483 |
Document ID | / |
Family ID | 36034597 |
Filed Date | 2008-09-04 |
United States Patent
Application |
20080211033 |
Kind Code |
A1 |
Turkot; Robert B. ; et
al. |
September 4, 2008 |
Reducing oxidation under a high K gate dielectric
Abstract
A metal layer is formed on a dielectric layer, which is formed
on a substrate. After forming a masking layer on the metal layer,
the exposed sides of the dielectric layer are covered with a
polymer diffusion barrier.
Inventors: |
Turkot; Robert B.;
(Hillsboro, OR) ; Brask; Justin K.; (Portland,
OR) ; Kavalieros; Jack; (Portland, OR) ;
Doczy; Mark L.; (Beaverton, OR) ; Metz; Matthew
V.; (Hillsboro, OR) ; Shah; Uday; (Portland,
OR) ; Datta; Suman; (Beaverton, OR) ; Chau;
Robert S.; (Beaverton, OR) |
Correspondence
Address: |
TROP PRUNER & HU, PC
1616 S. VOSS ROAD, SUITE 750
HOUSTON
TX
77057-2631
US
|
Family ID: |
36034597 |
Appl. No.: |
12/151483 |
Filed: |
May 7, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10939227 |
Sep 10, 2004 |
7387927 |
|
|
12151483 |
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Current U.S.
Class: |
257/369 ;
257/E21.202; 257/E21.623; 257/E21.637; 257/E27.064; 257/E29.158;
257/E29.159 |
Current CPC
Class: |
H01L 21/28194 20130101;
H01L 29/517 20130101; H01L 21/82345 20130101; H01L 29/495 20130101;
H01L 21/28079 20130101; H01L 29/4966 20130101; H01L 21/823842
20130101; H01L 21/28088 20130101; H01L 29/4958 20130101 |
Class at
Publication: |
257/369 ;
257/E27.064 |
International
Class: |
H01L 27/092 20060101
H01L027/092 |
Claims
1. A semiconductor structure comprising: a substrate; a stack
formed on said substrate, said stack including a polysilicon layer
over a dielectric layer; and a polymer diffusion barrier covering
the sides of said dielectric layer.
2. The structure of claim 1 wherein said structure in the
complementary metal oxide semiconductor structure including an NMOS
transistor and a PMOS transistor, each of said transistors
including a dielectric layer whose sides are covered by a polymer
diffusion layer.
3. The structure of claim 1 wherein said dielectric layer has a
dielectric constant greater than 10.
4. The structure of claim 1 wherein said polymer diffusion barrier
is formed of fluorocarbon etch residue.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional of U.S. patent application
Ser. No. 10/939,227, filed Sep. 10, 2004.
BACKGROUND
[0002] The present invention relates to methods for making
semiconductor devices, in particular, semiconductor devices that
include high K gate dielectrics.
[0003] Metal oxide semiconductor (MOS) field-effect transistors
with very thin gate dielectrics made from silicon dioxide may
experience unacceptable gate leakage currents. Forming the gate
dielectric from certain high dielectric constant dielectric (k)
materials, instead of silicon dioxide, can reduce gate leakage.
Because such a dielectric may not be compatible with polysilicon,
it may be desirable to use metal gate electrodes in devices that
include high-k gate dielectrics.
[0004] A metal gate electrode may be formed on a high-k dielectric
layer by depositing a metal layer on the dielectric layer, masking
the metal layer, and then removing the exposed part of that layer.
A patterned polysilicon layer may be used to mask the metal layer,
and a dry etch process may be used to remove the exposed part of
that layer.
[0005] During subsequent high temperature steps in the presence of
oxygen, the high-k dielectric layer transports oxygen laterally,
oxidizing the underlying silicon. This lateral oxidation may result
in oxide encroachment under the high-k dielectric. This
encroachment increases the effective electrical gate thickness,
reducing transistor performance.
[0006] Thus, there is a need for better ways to make metal
gate/high K transistors.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIGS. 1a-1c represent cross-sections of structures that may
be formed when carrying out an embodiment of the method of the
present invention.
[0008] FIGS. 2a-2h represent cross-sections of structures that may
be formed when carrying out a second embodiment of the method of
the present invention; and
[0009] FIG. 3 represents a cross-section of a structure in
accordance with a third embodiment of the present invention.
[0010] Features shown in these figures are not intended to be drawn
to scale.
DETAILED DESCRIPTION
[0011] After forming a dielectric layer on a substrate, a metal
layer may be formed on the dielectric layer. After forming a
masking layer on the metal layer, the sides of the dielectric layer
are sealed with a diffusion barrier. In the following description,
a number of details are set forth to provide a thorough
understanding of the present invention. It will be apparent to
those skilled in the art, however, that the invention may be
practiced in many ways other than those expressly described here.
The invention is thus not limited by the specific details disclosed
below.
[0012] FIGS. 1a-1c illustrate structures that may be formed, when
carrying out an embodiment of the method of the present invention.
Initially, dielectric layer 101 is formed on substrate 100, metal
layer 102 is formed on dielectric layer 101, and masking layer 103
is formed on metal layer 102, generating the FIG. 1a structure.
Substrate 100 may comprise a bulk silicon or silicon-on-insulator
substructure. Alternatively, substrate 100 may comprise other
materials--which may or may not be combined with silicon--such as:
germanium, indium antimonide, lead telluride, indium arsenide,
indium phosphide, gallium arsenide, or gallium antimonide. Although
a few examples of materials from which substrate 100 may be formed
are described here, any material that may serve as a foundation
upon which a semiconductor device may be built falls within the
spirit and scope of the present invention.
[0013] Dielectric layer 101 preferably comprises a high-k gate
dielectric layer. By high-k it is intended to refer to dielectric
materials having dielectric constants greater than 10. Some of the
materials that may be used to make high-k gate dielectrics include:
hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium
oxide, zirconium silicon oxide, tantalum oxide, titanium oxide,
barium strontium titanium oxide, barium titanium oxide, strontium
titanium oxide, yttrium oxide, aluminum oxide, lead scandium
tantalum oxide, and lead zinc niobate. Particularly preferred are
hafnium oxide, zirconium oxide, and aluminum oxide. Although a few
examples of materials that may be used to form dielectric layer 101
are described here, that layer may be made from other materials
that serve to reduce gate leakage.
[0014] Dielectric layer 101 may be formed on substrate 100 using a
conventional deposition method, e.g., a conventional chemical vapor
deposition ("CVD"), low pressure CVD, or physical vapor deposition
("PVD") process. Preferably, a conventional atomic layer CVD
process is used. In such a process, a metal oxide precursor (e.g.,
a metal chloride) and steam may be fed at selected flow rates into
a CVD reactor, which is then operated at a selected temperature and
pressure to generate an atomically smooth interface between
substrate 100 and dielectric layer 101. The CVD reactor should be
operated long enough to form a layer with the desired thickness.
The dielectric layer 101 may be less than about 60 Angstroms thick,
for example, between about 5 Angstroms and about 40 Angstroms thick
in one embodiment.
[0015] Although not shown in FIG. 1a, it may be desirable to form a
capping layer, which may be no more than about five monolayers
thick, on dielectric layer 101. Such a capping layer may be formed
by sputtering one to five monolayers of silicon, or another
material, onto the surface of dielectric layer 101. The capping
layer may then be oxidized, e.g., by using a plasma enhanced
chemical vapor deposition ("PECVD") process or a solution that
contains an oxidizing agent, to form a capping dielectric
oxide.
[0016] Although in some embodiments it may be desirable to form a
capping layer on dielectric layer 101, in the illustrated
embodiment metal layer 102 is formed directly on dielectric layer
101. Metal layer 102 may comprise any conductive material from
which a metal gate electrode may be derived, and may be formed on
dielectric layer 101 using well known PVD or CVD processes.
Examples of n-type materials that may be used to form metal layer
102 include: hafnium, zirconium, titanium, tantalum, aluminum, and
metal carbides that include these elements, i.e., titanium carbide,
zirconium carbide, tantalum carbide, hafnium carbide and aluminum
carbide. Examples of p-type metals that may be used to form metal
layer 102 include: ruthenium, palladium, platinum, cobalt, nickel,
and conductive metal oxides, e.g., ruthenium oxide. Although a few
examples of materials that may be used to form metal layer 102 are
described here, those layers may be made from many other
materials.
[0017] Metal layer 102 may be thick enough to ensure that any
material formed on it will not significantly impact its
workfunction. The metal layer 102 may, for example, be between
about 25 Angstroms and about 300 Angstroms thick, and, in one
embodiment, may be between about 25 Angstroms and about 200
Angstroms thick. When metal layer 102 comprises an n-type material,
layer 102 may have a workfunction that is between about 3.9 eV and
about 4.2 eV. When metal layer 102 comprises a p-type material,
layer 102 may have a workfunction that is between about 4.9 eV and
about 5.2 eV.
[0018] After depositing metal layer 102 over dielectric layer 101,
masking layer 103 is formed on metal layer 102. Masking layer 103
may be formed by depositing a polysilicon layer on metal layer 102
and then patterning the polysilicon layer to generate a patterned
polysilicon layer. Such a polysilicon layer may be undoped or doped
with either n-type or p-type impurities, may be deposited using
conventional methods, and may be between about 500 Angstroms and
about 2,000 Angstroms thick in one embodiment.
[0019] A patterned polysilicon layer may be created by first
forming a hard mask that covers part of the polysilicon layer, and
leaves part of that layer exposed. Such a hard mask may comprise
silicon nitride, silicon dioxide, silicon oxynitride, or a nitrided
silicon dioxide. The hard mask may be between about 100 Angstroms
and about 500 Angstroms thick, and may be deposited and patterned
using conventional techniques. The exposed parts of the polysilicon
layer 103, layer 102, and layer 101 may then be removed using a dry
etch process.
[0020] Hard mask 110 may be retained after masking layer 103 is
formed to protect masking layer 103 during subsequent etching
operations. After etching to form the FIG. 1a structure, first side
104 and second side 105 of masking layer 103 are covered with a
polymer diffusion barrier 106, generating the FIG. 1b structure.
Masking layer 103 is covered with such a layer to reduce oxidation
of the layer 101 during subsequent temperature steps above
450.degree. C. The layer 106 is formed on the metal layer 102, hard
mask 110, and sides 104, 105 of masking layer 103 as the result of
the deposition of etch by-products when the stack is etched. The
film 106 is left behind as a result of the etch process. For
example, a poly etch may include Cl.sub.2, HBr, and O.sub.2
containing gases, such as CH.sub.3F, CF.sub.4, and C.sub.4F.sub.8.
Traditionally, the etch processes are tuned to deposited polymer
films intentionally for the polymer diffusion barrier 106 as a
diffusion barrier, the etching condition, in this case. The make-up
of the barrier 106 is dependent upon the etch process gases and
materials being etched. For a polysilicon stack, a generic mixture
of primarily Si, O, C, and miscellaneous material dependent upon
the etch gases is left behind. Layer 106 may be deposited onto
metal layer 102, hard mask 110 and sides 104, 105, using a
conventional CVD process. In one embodiment, layer 106 may have a
thickness of between about 10 Angstroms and about 100 Angstroms.
The layer 106 may be formed in situ in the dry etch chamber used to
etch the stack shown in FIG. 1a.
[0021] After layer 106 is deposited, an anisotropic plasma dry etch
process may be applied to remove a portion of the sacrificial
diffusion barrier 106 from substrate 100 and the top of the hard
mask 110, generating the FIG. 1c structure.
[0022] Process steps for completing the device, e.g., forming
sidewall spacers on the gate electrode stack, source and drain
regions and the device's contacts, are well known to those skilled
in the art and will not be described in more detail here. In this
regard, using dummy doped polysilicon layers for masking layer 103
may enable one to apply commonly used nitride spacer, source/drain,
and silicide formation techniques, when completing the structure.
During those subsequent process steps, hard mask 110 may be
retained to prevent a significant part of masking layer 103 from
being converted into a silicide. Conversely, if it is desirable to
subsequently convert part or all of masking layer 103 into a
silicide, then hard mask 110 must be removed beforehand.
[0023] Referring to FIG. 3, in accordance with another embodiment
of the present invention, a polymer diffusion barrier 306 may be
selectively deposited on the dielectric layer 301 of a stack
including a masking layer 303. The masking layer 303 may correspond
to the layers 203 and 103 in the other embodiments and the masking
layer 310 may correspond to the masking layers 210 and 110 in the
other embodiments. Likewise, the dielectric layer 301 may
correspond to the dielectric layers 101 and 201 in other
embodiments.
[0024] The diffusion barrier 306 may be selectively formed on a
substrate 300 and the dielectric layer 301 by etching using a
gaseous plasma mixture that polymerizes onto the dielectric layer
30 on contact. For example, with fluorocarbon etch chemistries,
polymer deposition can occur selectively on metal containing layers
such as a layer 301 in the form of a metal oxide. This selective
deposition is believed to be due to increased reactivity catalysis
at the metal surface, due to its electrical properties.
[0025] FIGS. 2a-2h illustrate structures that may be formed, when
carrying out a third embodiment of the method of the present
invention. Initially, dielectric layer 201 is formed on substrate
200, generating the FIG. 2a structure. As indicated above,
dielectric layer 201 preferably comprises a high-k gate dielectric
layer. First metal layer 202 is then formed on dielectric layer
201, and part of that layer is masked by masking layer
203--generating the FIG. 2b structure. First metal layer 202 may
comprise any conductive material from which a metal gate electrode
may be derived. When first metal layer 202 comprises an n-type
metal, it may be formed from any of the n-type materials identified
above, using well known PVD or CVD processes, may have a
workfunction that is between about 3.9 eV and about 4.2 eV, and,
for example, is between about 25 Angstroms and about 300 Angstroms
thick.
[0026] Masking layer 203 may be formed from conventional materials
using conventional techniques. In one embodiment, masking layer 203
may comprise a silicon nitride or silicon dioxide hard mask, which
may be formed using deposition and patterning techniques that are
well known to those skilled in the art. After forming masking layer
203, a dry or wet etch process is applied to remove part of first
metal layer 202, leaving part of dielectric layer 201 exposed.
After first metal layer 202 is etched, the remainder of masking
layer 203 is removed, generating the FIG. 2c structure.
[0027] In this embodiment, second metal layer 204 is then deposited
on first metal layer 202 and on the exposed part of dielectric
layer 201--generating the FIG. 2d structure. When first metal layer
202 comprises an n-type metal, second metal layer 204 preferably
comprises a p-type metal, e.g., one of the p-type metals identified
above. When second metal layer 204 comprises a p-type material, it
may be formed on dielectric layer 201 and first metal layer 202
using a conventional PVD or CVD process, for example, is between
about 25 Angstroms and about 300 Angstroms thick and, in one
embodiment, has a workfunction that is between about 4.9 eV and
about 5.2 eV.
[0028] After depositing second metal layer 204 on first metal layer
202 and dielectric layer 201, masking layer 203 (e.g., a hard mask)
is deposited on second metal layer 204. Masking layer 210 is then
formed on masking layer 203 to define sections of masking layer 203
to be removed and sections to be retained. FIG. 2e represents a
cross-section of the structure that results after masking layer 210
is formed on masking layer 203. In one embodiment, masking layer
203 comprises polysilicon, and masking layer 210 comprises silicon
nitride or silicon dioxide. After layer 210 is formed, part of
layer 203 is removed selective to second metal layer 204, e.g.,
using a dry etch process, to expose part of layer 204 and to create
the FIG. 2f structure.
[0029] After etching masking layer 203, the sides of masking
structures 207, 208 are lined with a polymer diffusion layer 206,
generating the FIG. 2g structure. Sacrificial layer 206 may
comprise any of the materials identified above, and may be formed
using a conventional CVD process. After layer 206 is deposited, an
anisotropic plasma dry etch process may be applied to the layer 206
over the substrate 200, generating the FIG. 2h structure.
[0030] Because process steps for completing the device are well
known to those skilled in the art, they will be omitted here. As
with the previously described embodiment, masking layers 210 may be
removed prior to converting masking structures 207, 208 into a
silicide, or retained to prevent significant portions of structures
207, 208 from being converted into a silicide during subsequent
process steps.
[0031] The three layer gate electrode stack of FIG. 2h may serve as
the gate electrode for an NMOS transistor with a workfunction
between about 3.9 eV and about 4.2 eV, while the two layer gate
electrode stack may serve as the gate electrode for a PMOS
transistor with a workfunction between about 4.9 eV and about 5.2
eV. Alternatively, the three layer gate electrode stack may serve
as the gate electrode for a PMOS transistor, while the two layer
gate electrode stack may serve as the gate electrode for an NMOS
transistor.
[0032] The first metal layer should set the transistor's
workfunction, regardless of the composition of the remainder of the
gate electrode stack. For that reason, the presence of the second
metal layer on top of the first metal layer in the three layer gate
electrode stack, and the presence of a dummy doped polysilicon
layer in either a three or two layer gate electrode stack, should
not affect the workfunction of that stack in a meaningful way.
[0033] Although such a polysilicon layer should not affect the
workfunction of an underlying metal layer, that polysilicon layer
may serve as an extension of the transistor's contacts, as well as
a support for the nitride spacers. It also defines the transistor's
vertical dimension. Gate electrode stacks that include such a
polysilicon layer are thus considered to be "metal gate
electrodes," as are gate electrode stacks that include one or more
metal layers, but do not include a polysilicon layer.
[0034] As illustrated above, the method of the present invention
enables one to etch a metal layer without depositing undesirable
residues on the sides of an overlying masking layer and without
removing significant portions of the metal layer from beneath that
masking layer. Although the embodiments described above provide
examples of desirable metal layer etch processes, the present
invention is not limited to these particular embodiments.
[0035] Although the foregoing description has specified certain
steps and materials that may be used in the present invention,
those skilled in the art will appreciate that many modifications
and substitutions may be made. Accordingly, it is intended that all
such modifications, alterations, substitutions and additions be
considered to fall within the spirit and scope of the invention as
defined by the appended claims.
* * * * *