U.S. patent application number 11/860590 was filed with the patent office on 2008-01-10 for interconnect structure and method of fabrication of same.
Invention is credited to Lawrence A. Clevenger, Andrew P. Cowley, Timothy J. Dalton, Chih-Chao Yang, Meeyoung H. Yoon.
Application Number | 20080006944 11/860590 |
Document ID | / |
Family ID | 37109075 |
Filed Date | 2008-01-10 |
United States Patent
Application |
20080006944 |
Kind Code |
A1 |
Yang; Chih-Chao ; et
al. |
January 10, 2008 |
INTERCONNECT STRUCTURE AND METHOD OF FABRICATION OF SAME
Abstract
A damascene wire and method of forming the wire. The method
including: forming a mask layer on a top surface of a dielectric
layer; forming an opening in the mask layer; forming a trench in
the dielectric layer where the dielectric layer is not protected by
the mask layer; recessing the sidewalls of the trench under the
mask layer; forming a conformal conductive liner on all exposed
surface of the trench and the mask layer; filling the trench with a
core electrical conductor; removing portions of the conductive
liner extending above the top surface of the dielectric layer and
removing the mask layer; and forming a conductive cap on a top
surface of the core conductor. The structure includes a core
conductor clad in a conductive liner and a conductive capping layer
in contact with the top surface of the core conductor that is not
covered by the conductive liner.
Inventors: |
Yang; Chih-Chao;
(Poughkeepsie, NY) ; Clevenger; Lawrence A.; (La
Grangeville, NY) ; Cowley; Andrew P.; (Wappingers
Falls, NY) ; Dalton; Timothy J.; (Ridgefield, CT)
; Yoon; Meeyoung H.; (Hopewell Junction, NY) |
Correspondence
Address: |
SCHMEISER, OLSEN & WATTS
22 CENTURY HILL DR.
SUITE 302
LATHAM
NY
12110
US
|
Family ID: |
37109075 |
Appl. No.: |
11/860590 |
Filed: |
September 25, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11107074 |
Apr 15, 2005 |
|
|
|
11860590 |
Sep 25, 2007 |
|
|
|
Current U.S.
Class: |
257/751 ;
257/E21.579; 257/E23.141 |
Current CPC
Class: |
H01L 21/76843 20130101;
H01L 21/76814 20130101; H01L 2924/00 20130101; H01L 21/76849
20130101; H01L 2924/0002 20130101; H01L 21/76807 20130101; H01L
21/76831 20130101; H01L 2924/0002 20130101 |
Class at
Publication: |
257/751 ;
257/E23.141 |
International
Class: |
H01L 23/52 20060101
H01L023/52 |
Claims
1. A structure, comprising: a core electrical conductor having a
top surface, an opposite bottom surface and sides between said top
and bottom surfaces; an electrically conductive liner in direct
physical contact with and covering said bottom surface and said
sides of said core electrical conductor, embedded portions of said
electrically conductive liner in direct physical contact with and
extending over said core electrical conductor in regions of said
core electrical conductor adjacent to both said top surface and
said sides of said core electrical conductor; and an electrically
conductive cap in direct physical contact with said top surface of
said core electrical conductor that is exposed between said
embedded portions of said electrically conductive liner.
2. The structure of claim 1, wherein said portions of said
electrically conductive liner in direct physical contact with and
extending over said core electrical conductor extend over said core
electrical conductor from opposing pairs of sides of said sides of
said core electrical conductor a distance between about 3% to about
48% of the total distance between said sides of said core
electrical conductor.
3. The structure of claim 1, wherein top surfaces of said portions
of said electrically conductive liner in direct physical contact
with and extending over said core electrical conductor are coplanar
with said top surface of said core electrical conductor.
4. The structure of claim 1, wherein said electrically conductive
cap does not overlap said embedded portions of said electrically
conductive liner.
5. The structure of claim 1, wherein said electrically conductive
liner comprises a material selected from the group consisting of
Ta, TaN, Ti, TiN, TiSiN, W, Ru and combinations thereof.
6. The structure of claim 1, wherein said core electrical conductor
comprises a material selected from the group consisting of Al,
AlCu, Cu, W, Ag, Au and combinations thereof.
7. The structure of claim 1, wherein said electrically conductive
cap comprises a material selected from the group consisting of
CoWP, CoSnP, CoP, Pd or combinations thereof.
8. A structure, comprising: a core electrical conductor having a
top surface, an opposite bottom surface and sides between said top
and bottom surfaces; a dielectric liner formed on said sides of
said core electrical conductor; an electrically conductive liner in
direct physical contact with and covering said bottom surface of
said core electrical conductor and said dielectric liner, embedded
portions of said electrically conductive liner extending over said
dielectric liner and said core electrical conductor in regions of
said core electrical conductor adjacent to both said top surface
and said sides of said core electrical conductor; and an
electrically conductive cap in direct physical contact with said
top surface of said core electrical conductor that is exposed
between said embedded portions of said electrically conductive
liner.
9. The structure of claim 9, wherein said portions of said
electrically conductive liner in direct physical contact with and
extending over said core electrical conductor extend over said core
electrical conductor from opposing pairs of sides of said sides of
said core electrical conductor a distance between about 3% to about
48% of the total distance between said sides of said core
electrical conductor.
10. The structure of claim 8, wherein top surfaces of said portions
of said electrically conductive liner in direct physical contact
with and extending over said core electrical conductor are coplanar
with said top surface of said core electrical conductor.
11. The structure of claim 8, wherein said electrically conductive
cap does not overlap said embedded portion of said electrically
conductive liner and does not overlap any edge of said dielectric
liner exposed between said electrically embedded portion of said
conductive liner and said core electrical conductor.
12. The structure of claim 8, wherein: said dielectric liner
comprises a material selected from the group consisting of
SiO.sub.2, Si.sub.3N.sub.4, SiC, SiON, SiOC, hydrogen doped silica
glass (SiCOH), plasma-enhanced silicon nitride (PSiN.sub.x) or
NBLoK (SiC(N,H)) and combinations thereof; said electrically
conductive liner comprises a material selected from the group
consisting of Ta, TaN, Ti, TiN, TiSiN, W, Ru and combinations
thereof; said core electrical conductor comprises a material
selected from the group consisting of Al, AlCu, Cu, W, Ag, Au and
combinations thereof; and. said electrically conductive cap
comprises a material selected from the group consisting of CoWP,
CoSnP, CoP, Pd or combinations thereof.
Description
[0001] This application is a division of copending U.S. patent
application Ser. No. 11/107,074 filed on Apr. 15, 2005.
FIELD OF THE INVENTION
[0002] The present invention relates to the field of integrated
circuit manufacture; more specifically, it relates to an
interconnect structure and method of fabricating the interconnect
structure for wiring levels of an integrated circuit.
BACKGROUND OF THE INVENTION
[0003] Advanced integrated circuits utilize copper and other
metallurgy in the interconnect or wiring levels in order to
increase performance of the integrated circuit. Because of the
possibility of copper and other metal diffusion through interlevel
dielectric layers, copper and other metal interconnects are
fabricated with conductive diffusion barrier liners on the sides
and bottoms of the wires and dielectric copper and other metal
diffusion barrier caps on the top surface of the wires. However, it
has been found that wires using dielectric diffusion barrier caps
are susceptible to reliability failures.
[0004] Therefore, there is a need for improved diffusion barrier
capped interconnect structures.
SUMMARY OF THE INVENTION
[0005] The present invention utilizes electrically conductive
diffusion barrier caps to seal surfaces of damascene and dual
damascene interconnect structures not covered by electrically
conductive liners or dielectric layers that may also act as
diffusion barriers. The caps (and electrically conductive liners
and dielectric layers, when acting as diffusion barrier) are
diffusion barriers to a material contained in the core electrical
conductor of a damascene or dual damascene line.
[0006] A first aspect of the present invention is a method,
comprising: providing a substrate having a dielectric layer;
forming a hard mask layer on a top surface of the dielectric layer;
forming an opening in the hard mask layer; forming a trench in the
dielectric layer where the dielectric layer is not protected by the
hard mask layer, the trench having sidewalls and a bottom;
recessing the sidewalls of the trench under the hard mask layer;
forming a conformal electrically conductive liner on all exposed
surfaces of the trench and the hard mask layer; filling the trench
with a core electrical conductor; removing portions of the
electrically conductive liner extending above the top surface of
the dielectric layer and removing the mask layer; and forming an
electrically conductive cap on a top surface of the core electrical
conductor.
[0007] A second aspect of the present invention is a method
comprising: providing a substrate having a dielectric layer;
forming a hard mask layer on a top surface of the dielectric layer;
forming an opening in the hard mask layer; forming a trench in the
dielectric layer where the dielectric layer is not protected by the
hard mask layer, the trench having sidewalls and a bottom, the
sidewalls of the trench aligned with the opening in the hard mask;
performing an isotropic etch of the sidewalls and bottom of the
trench, the isotropic etch undercutting the hard mask layer and
forming a hard mask overhang projecting over the trench; forming a
conformal electrically conductive liner on all exposed surfaces of
the trench and on all exposed surfaces of the hard mask layer, an
upper portion of the electrically conductive liner in physical
contact with the hard mask overhang and forming an electrically
conductive overhang projecting over the trench; forming a core
electrical conductor over the electrically conductive liner, the
core electrical conductor filling the trench; performing a
chemical-mechanical polish to remove the hard mask layer and all
core electrical conductor extending above the top surface of the
dielectric layer, the chemical-mechanical-polishing making coplanar
a top surface of the dielectric layer, a top surface of the
electrically conductive liner and a top surface of the core
electrical conductor in the trench, the electrically conductive
layer extending over and in direct physical contact with the core
electrical conductor; and forming an electrically conductive cap on
the top surface of the core electrical conductor.
[0008] A third aspect of the present invention is a structure,
comprising: a core electrical conductor having a top surface, an
opposite bottom surface and sides between the top and bottom
surfaces; an electrically conductive liner in direct physical
contact with and covering the bottom surface and the sides of the
core electrical conductor, embedded portions of the electrically
conductive liner in direct physical contact with and extending over
the core electrical conductor in regions of the core electrical
conductor adjacent to both the top surface and the sides of the
core electrical conductor; and an electrically conductive cap in
direct physical contact with the top surface of the core electrical
conductor that is exposed between the embedded portions of the
electrically conductive liner.
[0009] A fourth aspect of the present invention is a structure,
comprising: a core electrical conductor having a top surface, an
opposite bottom surface and sides between the top and bottom
surfaces; a dielectric liner formed on the sides of the core
electrical conductor; an electrically conductive liner in direct
physical contact with and covering the bottom surface of the core
electrical conductor and the dielectric liner, embedded portions of
the electrically conductive liner extending over the dielectric
liner and the core electrical conductor in regions of the core
electrical conductor adjacent to both the top surface and the sides
of the core electrical conductor; and an electrically conductive
cap in direct physical contact with the top surface of the core
electrical conductor that is exposed between the embedded portions
of the electrically conductive liner.
BRIEF DESCRIPTION OF DRAWINGS
[0010] The features of the invention are set forth in the appended
claims. The invention itself, however, will be best understood by
reference to the following detailed description of an illustrative
embodiment when read in conjunction with the accompanying drawings,
wherein:
[0011] FIGS. 1A through 1H are cross-sectional views illustrating
common process steps for fabricating an interconnect structure
according to both first and second embodiments of the present
invention;
[0012] FIGS. 2A through 2C are cross-sectional views illustrating
process steps for fabricating an interconnect structure according
to the first embodiment of the present invention;
[0013] FIGS. 3A through 3E are cross-sectional views illustrating
process steps for fabricating an interconnect structure according
to the second embodiment of the present invention;
[0014] FIG. 4 is a cross-sectional view illustrating multiple
wiring levels fabricated according to the first embodiment of the
present invention; and
[0015] FIG. 5 is a cross-sectional view illustrating multiple
wiring levels fabricated with additional diffusion barriers
applicable to the first and the second embodiments of the present
invention.
DETAILED DESCRIPTION OF THE INVENTION
[0016] For the purposes of describing the present invention, the
terms conductor and conductive should be reads as electrical
conductor and electrically conductive.
[0017] A (single) damascene process is one in which wire trench or
via openings are formed in a dielectric layer, an electrical
conductor deposited on a top surface of the dielectric of
sufficient thickness to fill the trenches and a
chemical-mechanical-polish (CMP) process performed to remove excess
conductor and make the surface of the conductor co-planer with the
surface of the dielectric layer to form damascene wires (or
damascene vias).
[0018] A dual damascene process is one in which via openings are
formed through the entire thiclness of a dielectric layer followed
by formation of trenches part of the way through the dielectric
layer in any given cross-sectional view. All via openings are
intersected by integral wire trenches above and by a wire trench
below, but not all trenches need intersect a via opening. An
electrical conductor is deposited on a top surface of the
dielectric of sufficient thickness to fill the trenches and via
opening and a CMP process performed to make the surface of the
conductor in the trench co-planer with the surface the dielectric
layer to form dual damascene wire and dual damascene wires having
integral dual damascene vias.
[0019] The structure of present invention will be described as
being fabricated to connect to a contact level of an integrated
circuit chip using a dual damascene process copper metallurgy
process, though the present invention is applicable to metallurgies
other than copper. A contact level is a transitional level,
connecting devices such as metal-oxide-silicon field effect
transistors (MOSFETs) to the first of wiring level of an integrated
circuit, where the individual devices are "wired" into circuits. It
should be understood that the structure of the present invention
may be formed in any or all of these wiring levels as illustrated
in FIGS. 4 and 5 and as well as using a single damascene
process.
[0020] FIGS. 1A through 1H are cross-sectional views illustrating
common process steps for fabricating an interconnect structure
according to both first and second embodiments of the present
invention. In FIG. 1A, formed on a substrate 100 is a dielectric
layer 105. A dielectric diffusion barrier 110 is formed on a top
surface 115 of dielectric layer 105. Formed through diffusion
barrier 110 and dielectric layer 105 is a stud contact 120. A top
surface 125 of stud contact 120 is coplanar with a top surface 130
of barrier layer 110. In one example, barrier 110 is a diffusion
barrier to materials contained in subsequently formed wires. In one
example, barrier 110 is a diffusion barrier to copper.
[0021] In FIG. 1B, a dielectric layer 135 is formed on top surface
130 of barrier layer 110 and a hard mask layer 140 is formed on a
top surface 145 of dielectric layer 135.
[0022] In one example, dielectric layer 135 is a low K (dielectric
constant) material, examples of which include but are not limited
to hydrogen silsesquioxane polymer (HSQ), methyl silsesquioxane
polymer (MSQ) and polyphenylene oligomer (SiOx(CH.sub.3).sub.y). A
low K dielectric material has a relative permittivity of about 4 or
less. In a second example, dielectric layer 135 comprises
SiO.sub.2. Dielectric layer 135 may be, for example, between about
50 nm and about 1,000 nm thick. In one example, hard mask layer 140
may comprise, for example, silicon dioxide (SiO.sub.2), silicon
nitride (Si.sub.3N.sub.4), silicon carbide (SiC), silicon oxy
nitride (SiON), silicon oxy carbide (SiOC), hydrogen doped silica
glass (SiCOH), plasma-enhanced silicon nitride (PSiN.sub.x) or
NBLoK (SiC(N,H)). Hard mask layer 140 may be, for example, between
about 5 nm and about 100 nm thick. It is possible for hard mask
layer 140 to comprise a metal.
[0023] In FIG. 1C, a patterned photoresist layer 150 is formed on a
top surface 155 of hard mask layer 140, the photoresist is layer
patterned by any number of well known lithographic processes and a
trench 155 etched through hard mask layer 140, exposing top surface
145 of dielectric layer 140.
[0024] In FIG. 1D, patterned photoresist layer 150 (see FIG. 1C) is
removed and a trench 160 is formed, for example using a reactive
ion etch (RIE) process, into dielectric layer 135 to expose top
surface 125 of stud contact 120 using patterned hard mask layer 140
as an etch mask.
[0025] In FIG. 1E, another patterned photoresist layer 165 is
formed on a top surface 155 of hard mask layer 140, the photoresist
is layer patterned by any number of well known lithographic
processes and trenches 155A (trench 155 of FIG. 1C widened) and 170
are etched through hard mask layer 140, exposing top surface 145 of
dielectric layer 140.
[0026] In FIG. 1F, patterned photoresist layer 165 (see FIG. 1E) is
removed and a trenches 175 and 180 are etched, for example using an
RIE process, part way into dielectric layer 135. Trench 180
intersects trench 160.
[0027] In FIG. 1G, overhangs 185 of hard mask layer 140 are created
by isotropic removal of a layer of dielectric layer 135 exposed in
trenches 160, 175 and 180. In a first example, the isotropic
removal of a layer of dielectric layer 135 may be accomplished by
wet etching in solution comprising HNO.sub.3, HCl, H.sub.2SO.sub.4,
HF, NH.sub.4OH, NH.sub.4F or combinations thereof. In a second
example, the isotropic removal of a layer of dielectric layer 135
may be accomplished by a high-pressure plasma etch having low
directionality.
[0028] Using trench 175 as an example, if the widest portion of the
opening in hard mask layer 140 is W1, and the overhang has a width
W2, then the ratio W2/W1 may be between about 0.03 and about
0.48
[0029] In FIG. 1H, a conformal conductive liner 190 is formed over
top surface 155 of hard mask layer 140, all exposed surfaces of
overhangs 185, including bottom surfaces 195 of the overhangs,
exposed surfaces 200 of trenches 160, 175 and 180, and a top
surface 125A of stud contact 120. In one example, liner 190 is a
diffusion barrier to the material(s) of a core conductor 210 (see
FIG. 2A or 3C) that will be later formed over the liner. In one
example, liner 190 is a diffusion barrier to copper. In one example
liner 190 comprises Ta, TaN, Ti, TiN, TiSiN, W, Ru or combinations
thereof. In one example, liner 190 is between about 2 nm and about
100 nm thick. Liner 190 may be formed, for example by chemical
vapor deposition (CVD) or atomic layer deposition (ALD).
[0030] Alternatively, liner 190 may be formed in a process of
conformal deposition of liner material followed by a simultaneous
sputter etch (using a charged sputtering species) and liner
deposition as metal neutrals process as taught in U.S. Pat. No.
6,784,105 to Yang et al., issued on Aug. 31, 2004 which is hereby
incorporated by reference in its entirety. In one example, metal
neutrals comprises include Ta, TaN, Ti, TiN, TiSiN, W, Ru or
combinations thereof and the gas used to generate the sputtering
species comprises Ar, He, Ne, Xe, N.sub.2, H.sub.2 NH.sub.3,
N.sub.2H.sub.2 or combinations thereof. The liner material
previously deposited is removed from the bottom of the trench along
with any metal oxide that may be present on top surface 125A of
stud contact 120 (or any core conductor as illustrated in FIGS. 5
and 6). When sputtering is stopped but metal neutral deposition
continued, a new layer of liner 190 is formed to replace that which
was removed.
[0031] FIGS. 2A through 2C are cross-sectional views illustrating
process steps for fabricating an interconnect structure according
to the first embodiment of the present invention. FIG. 2A continues
from FIG. 1H. In FIG. 2A, a core conductor 210 is formed on top of
liner 190. In one example core conductor 210 comprises Al, AlCu,
Cu, W, Ag, Au or combinations thereof. In the example of core
conductor 210 being copper, a thin copper layer is evaporated or
deposited and then a thicker layer of copper is electroplated. The
thickness of core conductor 210 is sufficient to completely fill
trenches 160, 175 and 180.
[0032] In FIG. 2B, a chemical-mechanical-polish (CMP) process is
performed to co-planarize a top surface 145A of dielectric layer
135, a top surface 215 of liner 190 and a top surface 220 of core
conductor 210. After the CMP process, a damascene wire 225 and a
dual damascene wire 230 having with an integral damascene via 235
are formed.
[0033] In FIG. 2C, conductive diffusion barrier caps 240 are
selectively formed on top surface 220 of core conductor 210. In one
example, barrier caps 240 comprises CoWP, CoSnP, CoP and Pd or
combinations thereof. In one example caps 240 are about 5 nm to
about 80 nm thick. In one example, caps 240 are diffusion barriers
to the material(s) of core conductor 210. In one example, caps 240
is a diffusion barrier to copper In one example, caps 240 are
formed by a process that includes electroless plating. Methods of
forming CoWP, CoSnP, CoP and Pd layers are disclosed in U.S. Pat.
No. 5,695,810 to Bubin et al, issued on Dec. 9, 1997 and U.S. Pat.
No. 6,342,733 to Hu et al., issued on Jan. 29, 2002 which are
hereby incorporated by reference in their entireties. Barrier caps
240 are in direct physical contact with top surface 220 of core
conductor 210.
[0034] FIGS. 3A through 3E are cross-sectional views illustrating
process steps for fabricating an interconnect structure according
to the second embodiment of the present invention. FIG. 3A
continues from FIG. 1H. In FIG. 3A a dielectric liner 245 is formed
on all exposed surfaces of liner 190. In one example, dielectric
liner 245 may comprise, for example, silicon dioxide (SiO.sub.2),
silicon nitride (Si.sub.3N.sub.4), silicon carbide (SiC), silicon
oxy nitride (SiON), silicon oxy carbide (SiOC), hydrogen doped
silica glass (SiCOH), plasma-enhanced silicon nitride (PSiN.sub.x)
or NBLoIK (SiC(N,H)) or combinations thereof. In one example
dielectric liner 245 is about 5 nm to about 100 nm thick.
Dielectric liner 245 may be formed, for example by CVD or ALD.
[0035] In FIG. 3B, a directional etch process (such as an RIE) is
performed to remove dielectric liner 245 from horizontal surfaces
of liner 190 disposed on bottom surfaces of trenches 160. 175 and
180. The directional etch process may be followed by a simultaneous
sputter etch and liner deposition as metal neutrals process as
described supra, in reference to FIG. 1H.
[0036] In FIG. 3C, core conductor 210 is formed as described supra
ion reference to FIG. 2A. The thickness of core conductor 210 is
sufficient to completely fill trenches 160, 175 and 180.
[0037] In FIG. 3D, a CMP process is performed to co-planarize top
surface 145A of dielectric layer 135, top surface 215 of liner 190,
top surface 220 of core conductor 210 and a top surface 250 of
dielectric liner 245. After the CMP process, a damascene wire 255
and a dual damascene wire 260 having with an integral damascene via
265 are formed.
[0038] In FIG. 3E, caps 240 are selectively formed on top surface
220 of core conductor 210. Caps 240 are in direct physical contact
with and completely covers top surface 220 of core conductor
210.
[0039] FIG. 4 is a cross-sectional view illustrating multiple
wiring levels fabricated according to the first embodiment of the
present invention. In FIG. 4, an interlevel dielectric layer 270
containing a damascene wire 275 and dual damascene wire 280 having
with an integral damascene via 285 is formed over dielectric layer
135 (which can also be considered an interlevel dielectric layer).
An interlevel dielectric layer 290 containing a dual damascene wire
295 with an integral damascene via 300 and dual damascene wire 305
having with an integral damascene via 310 is formed over interlevel
dielectric layer dielectric layer 270. Interlevel dielectric layers
270 and 275 are similar to dielectric layer 135. Damascene wire 275
is similar to damascene wire 225 and dual damascene wires 280, 295
and 305 with respective integral vias 285, 300 and 310 are similar
to dual damascene wire 230 and integral via 235. Caps 240A and 240B
are similar to caps 240. While three wiring levels are illustrated
in FIG. 4, any number of similar wiring levels may be so stacked.
Damascene wires and vias and dual damascene wires and vias having
structures of the second embodiment of the present invention may be
similarly formed in stacked interlevel dielectric layers.
[0040] FIG. 5 is a cross-sectional view illustrating multiple
wiring levels fabricated with additional diffusion barriers
applicable to the first and the second embodiments of the present
invention. FIG. 5 is similar to FIG. 4 with the difference that a
dielectric layer 135A includes dielectric layer 135 and a
dielectric diffusion barrier 315, an interlevel dielectric layer
270A includes dielectric layer 270 and a dielectric diffusion
barrier layer 320 and an interlevel dielectric layer 290A includes
dielectric layer 290 and a dielectric diffusion barrier layer 325.
Diffusion barrier 315 is formed between dielectric layer 135 and
interlevel dielectric layer 275, diffusion barrier 320 is formed on
top of interlevel dielectric layer 275. Diffusion barriers 315, 320
and 325 are similar to diffusion barrier 110. In one example,
diffusion barriers 315, 320 and 325 are diffusion barriers to
materials contained in wires 225, 230, 275, 280, 295 and 305. In
one example, diffusion barriers 315, 320 and 325 are diffusion
barriers to copper. While three wiring levels are illustrated in
FIG. 5, any number of similar wiring levels may be so stacked.
Damascene wires and vias and dual damascene wires and vias having
structures of the second embodiment of the present invention may be
similarly formed in stacked interlevel dielectric layers.
[0041] Thus, the present invention provides improved diffusion
barrier capped interconnect structures.
[0042] The description of the embodiments of the present invention
is given above for the understanding of the present invention. It
will be understood that the invention is not limited to the
particular embodiments described herein, but is capable of various
modifications, rearrangements and substitutions as will now become
apparent to those skilled in the art without departing from the
scope of the invention. Therefore, it is intended that the
following claims cover all such modifications and changes as fall
within the true spirit and scope of the invention.
* * * * *