| Patent | Date |
|---|
Back-end-of-line interconnect structures with varying aspect ratios
Grant 11,444,029 - Bhosale , et al. September 13, 2 | 2022-09-13 |
Interconnects having air gap spacers
Grant 11,430,690 - Cheng , et al. August 30, 2 | 2022-08-30 |
Subtractive back-end-of-line vias
Grant 11,410,879 - Park , et al. August 9, 2 | 2022-08-09 |
Metallic interconnect structures with wrap around capping layers
Grant 11,404,311 - Peethala , et al. August 2, 2 | 2022-08-02 |
Magneto-resistive Random Access Memory With Laterally-recessed Free Layer
App 20220190235 - van der Straten; Oscar ; et al. | 2022-06-16 |
Forming decoupled interconnects
Grant 11,361,987 - Dutta , et al. June 14, 2 | 2022-06-14 |
Non Volatile Resistive Memory Logic Device
App 20220172776 - Chen; Hsueh-Chung ; et al. | 2022-06-02 |
Advanced Copper Interconnects With Hybrid Microstructure
App 20220165620 - Edelstein; Daniel C. ; et al. | 2022-05-26 |
Aluminum Alloy Wheel And Method For Manufacturing The Same
App 20220161313 - Chou; Yu-Hsien ; et al. | 2022-05-26 |
Bi metal subtractive etch for trench and via formation
Grant 11,328,954 - Mignot , et al. May 10, 2 | 2022-05-10 |
Mim Capacitor Structures
App 20220139820 - LIANG; JIM SHIH-CHUN ; et al. | 2022-05-05 |
Self-aligned top via scheme
Grant 11,322,402 - Xie , et al. May 3, 2 | 2022-05-03 |
Single process for liner and metal fill
Grant 11,322,359 - Adusumilli , et al. May 3, 2 | 2022-05-03 |
Back end of line structures with metal lines with alternating patterning and metallization schemes
Grant 11,315,799 - Xie , et al. April 26, 2 | 2022-04-26 |
Metallic interconnect structures with wrap around capping layers
Grant 11,315,830 - Peethala , et al. April 26, 2 | 2022-04-26 |
Self-aligned top via
Grant 11,315,872 - Park , et al. April 26, 2 | 2022-04-26 |
Footing flare pedestal structure
Grant 11,302,639 - Yang , et al. April 12, 2 | 2022-04-12 |
Electrode-via structure
Grant 11,302,630 - Standaert , et al. April 12, 2 | 2022-04-12 |
Fully aligned interconnects with selective area deposition
Grant 11,289,375 - Park , et al. March 29, 2 | 2022-03-29 |
Interconnect Structures Including Self Aligned Vias
App 20220093453 - Yang; Chih-Chao ; et al. | 2022-03-24 |
Interconnect and memory structures formed in the BEOL
Grant 11,282,788 - Yang , et al. March 22, 2 | 2022-03-22 |
Switchable metal insulator metal capacitor
Grant 11,276,748 - Li , et al. March 15, 2 | 2022-03-15 |
Metallization layer formation process
Grant 11,270,935 - Cheng , et al. March 8, 2 | 2022-03-08 |
E-fuse co-processed with MIM capacitor
Grant 11,257,750 - Li , et al. February 22, 2 | 2022-02-22 |
Interconnect structures with selective capping layer
Grant 11,251,368 - Zhou , et al. February 15, 2 | 2022-02-15 |
Method and structure for forming fully-aligned via
Grant 11,244,861 - Xie , et al. February 8, 2 | 2022-02-08 |
Fully aligned via interconnects with partially removed etch stop layer
Grant 11,244,853 - Motoyama , et al. February 8, 2 | 2022-02-08 |
Dual damascene fully aligned via in interconnects
Grant 11,244,854 - Cheng , et al. February 8, 2 | 2022-02-08 |
Back end of line metallization
Grant 11,244,897 - Park , et al. February 8, 2 | 2022-02-08 |
Double patterning interconnect integration scheme with SAV
Grant 11,244,860 - Chen , et al. February 8, 2 | 2022-02-08 |
Metal surface preparation for increased alignment contrast
Grant 11,244,907 - Zhou , et al. February 8, 2 | 2022-02-08 |
On integrated circuit (IC) device simultaneously formed capacitor and resistor
Grant 11,244,850 - Liang , et al. February 8, 2 | 2022-02-08 |
E-fuse with dielectric zipping
Grant 11,239,160 - Zhou , et al. February 1, 2 | 2022-02-01 |
Bottom conductive structure with a limited top contact area
Grant 11,239,278 - Yang , et al. February 1, 2 | 2022-02-01 |
Method of forming an interconnect structure with enhanced corner connection
Grant 11,239,165 - Xie , et al. February 1, 2 | 2022-02-01 |
Fully Aligned Via for Interconnect
App 20220020688 - Xie; Ruilong ; et al. | 2022-01-20 |
Interconnect Structures with Selective Barrier for BEOL Applications
App 20220020638 - Bhosale; Prasad ; et al. | 2022-01-20 |
MRAM integration with BEOL interconnect including top via
Grant 11,227,892 - Dutta , et al. January 18, 2 | 2022-01-18 |
Interconnect structures including self aligned vias
Grant 11,227,792 - Yang , et al. January 18, 2 | 2022-01-18 |
Planar resistive random-access memory (RRAM) device with a shared top electrode
Grant 11,227,997 - Dutta , et al. January 18, 2 | 2022-01-18 |
Planar Resistive Random-access Memory (rram) Device With A Shared Top Electrode
App 20220013723 - Dutta; Ashim ; et al. | 2022-01-13 |
Semiconductor tool matching and manufacturing management in a blockchain
Grant 11,223,655 - Bhosale , et al. January 11, 2 | 2022-01-11 |
Advanced copper interconnects with hybrid microstructure
Grant 11,222,817 - Edelstein , et al. January 11, 2 | 2022-01-11 |
Semiconductor device with reduced via resistance
Grant 11,222,815 - Murray , et al. January 11, 2 | 2022-01-11 |
Bottom electrode for semiconductor memory device
Grant 11,217,742 - Yang , et al. January 4, 2 | 2022-01-04 |
Via formation with robust hardmask removal
Grant 11,211,291 - Xie , et al. December 28, 2 | 2021-12-28 |
Self-aligned top via structure
Grant 11,205,592 - Xie , et al. December 21, 2 | 2021-12-21 |
Top via interconnect with self-aligned barrier layer
Grant 11,205,591 - Cheng , et al. December 21, 2 | 2021-12-21 |
Interconnect architecture with enhanced reliability
Grant 11,205,588 - Li , et al. December 21, 2 | 2021-12-21 |
E-Fuse with Dielectric Zipping
App 20210391256 - Zhou; Tianji ; et al. | 2021-12-16 |
Fully-aligned skip-vias
Grant 11,201,112 - Cheng , et al. December 14, 2 | 2021-12-14 |
Pitch multiplication with high pattern fidelity
Grant 11,201,056 - Park , et al. December 14, 2 | 2021-12-14 |
Bilayer barrier for interconnect and memory structures formed in the BEOL
Grant 11,195,751 - Yang , et al. December 7, 2 | 2021-12-07 |
Embedding Mram Device In Advanced Interconnects
App 20210375986 - Dutta; Ashim ; et al. | 2021-12-02 |
Forming Decoupled Interconnects
App 20210358801 - Dutta; Ashim ; et al. | 2021-11-18 |
Interconnects with gouged vias
Grant 11,177,169 - Cheng , et al. November 16, 2 | 2021-11-16 |
Top via structure with enlarged contact area with upper metallization level
Grant 11,177,163 - Motoyama , et al. November 16, 2 | 2021-11-16 |
Embedded small via anti-fuse device
Grant 11,177,213 - Yang , et al. November 16, 2 | 2021-11-16 |
Interconnects with hybrid metal conductors
Grant 11,177,214 - Cheng , et al. November 16, 2 | 2021-11-16 |
Ultrathin multilayer metal alloy liner for nano Cu interconnects
Grant 11,177,167 - Edelstein , et al. November 16, 2 | 2021-11-16 |
Planarization Controllability For Interconnect Structures
App 20210351064 - Xie; Ruilong ; et al. | 2021-11-11 |
Planarization controllability for interconnect structures
Grant 11,171,044 - Xie , et al. November 9, 2 | 2021-11-09 |
Bamboo tall via interconnect structures
Grant 11,164,779 - Yang , et al. November 2, 2 | 2021-11-02 |
Interconnects with spacer structure for forming air-gaps
Grant 11,164,774 - Cheng , et al. November 2, 2 | 2021-11-02 |
Interconnect and memory structures having reduced topography variation formed in the BEOL
Grant 11,164,878 - Yang , et al. November 2, 2 | 2021-11-02 |
Fully Aligned Via Interconnects With Partially Removed Etch Stop Layer
App 20210335659 - Motoyama; Koichi ; et al. | 2021-10-28 |
Selective CVD alignment-mark topography assist for non-volatile memory
Grant 11,158,584 - Rizzolo , et al. October 26, 2 | 2021-10-26 |
MRAM device formation with controlled ion beam etch of MTJ
Grant 11,158,786 - Dutta , et al. October 26, 2 | 2021-10-26 |
Method And Structure For Forming Fully-aligned Via
App 20210327756 - Xie; Ruilong ; et al. | 2021-10-21 |
Interconnect Structures With Selective Capping Layer
App 20210328137 - Zhou; Tianji ; et al. | 2021-10-21 |
Electrical fuse with metal line migration
Grant 11,152,300 - Li , et al. October 19, 2 | 2021-10-19 |
Electrode-via Structure
App 20210320060 - Standaert; Theodorus E. ; et al. | 2021-10-14 |
Bottom electrode for semiconductor memory device
Grant 11,145,813 - Yang , et al. October 12, 2 | 2021-10-12 |
Integrated circuit (IC) device integral capacitor and anti-fuse
Grant 11,145,591 - Liang , et al. October 12, 2 | 2021-10-12 |
Subtractive Back-end-of-line Vias
App 20210313226 - Park; Chanro ; et al. | 2021-10-07 |
Back End Of Line Metallization
App 20210313264 - PARK; CHANRO ; et al. | 2021-10-07 |
Via Formation With Robust Hardmask Removal
App 20210313229 - Xie; Ruilong ; et al. | 2021-10-07 |
Via-to-metal tip connections in multi-layer chips
Grant 11,139,242 - Xie , et al. October 5, 2 | 2021-10-05 |
Fully aligned top vias with replacement metal lines
Grant 11,139,202 - Park , et al. October 5, 2 | 2021-10-05 |
Multi-metal Interconnects For Semiconductor Device Structures
App 20210305160 - CHEN; Hsueh-Chung ; et al. | 2021-09-30 |
Embedded Memory Devices
App 20210305494 - Dutta; Ashim ; et al. | 2021-09-30 |
Dual Damascene Fully Aligned Via Interconnects
App 20210305090 - Cheng; Kenneth Chun Kuen ; et al. | 2021-09-30 |
Bottom electrode structure and method of forming the same
Grant 11,133,462 - Yang , et al. September 28, 2 | 2021-09-28 |
Controllable formation of recessed bottom electrode contact in a memory metallization stack
Grant 11,133,457 - Patlolla , et al. September 28, 2 | 2021-09-28 |
Interconnect structure
Grant 11,133,216 - Chen , et al. September 28, 2 | 2021-09-28 |
Fully Aligned Interconnects With Selective Area Deposition
App 20210296172 - Park; Chanro ; et al. | 2021-09-23 |
Pitch Multiplication With High Pattern Fidelity
App 20210296127 - PARK; CHANRO ; et al. | 2021-09-23 |
Top Via Structure With Enlarged Contact Area With Upper Metallization Level
App 20210296164 - Motoyama; Koichi ; et al. | 2021-09-23 |
Removal or reduction of chamfer for fully-aligned via
Grant 11,127,676 - Park , et al. September 21, 2 | 2021-09-21 |
Bi Metal Subtractive Etch For Trench And Via Formation
App 20210287940 - Mignot; Yann ; et al. | 2021-09-16 |
On Integrated Circuit (ic) Device Capacitor Between Metal Lines
App 20210287984 - Li; Baozhen ; et al. | 2021-09-16 |
Interconnect Structure With Enhanced Corner Connection
App 20210287988 - Xie; Ruilong ; et al. | 2021-09-16 |
Sub-ground rule e-Fuse structure
Grant 11,121,082 - Kim , et al. September 14, 2 | 2021-09-14 |
Rram Structures In The Beol
App 20210280638 - Li; Baozhen ; et al. | 2021-09-09 |
Protuberant contacts for resistive switching devices
Grant 11,107,984 - Ando , et al. August 31, 2 | 2021-08-31 |
Self-aligned repaired top via
Grant 11,107,731 - Xie , et al. August 31, 2 | 2021-08-31 |
Back-end-of-line Interconnect Structures With Varying Aspect Ratios
App 20210265277 - Bhosale; Prasad ; et al. | 2021-08-26 |
EFuse structure with multiple links
Grant 11,101,213 - Li , et al. August 24, 2 | 2021-08-24 |
Electromigration test structures for void localization
Grant 11,099,230 - Li , et al. August 24, 2 | 2021-08-24 |
Tall trenches for via chamferless and self forming barrier
Grant 11,101,175 - Mignot , et al. August 24, 2 | 2021-08-24 |
Hybrid Interconnect With A Reliability Liner In Wide Features
App 20210257299 - Yang; Chih-Chao ; et al. | 2021-08-19 |
Wet clean solutions to prevent pattern collapse
Grant 11,094,527 - Peethala , et al. August 17, 2 | 2021-08-17 |
Structure and method to fabricate fully aligned via with reduced contact resistance
Grant 11,094,580 - Park , et al. August 17, 2 | 2021-08-17 |
Formation of semiconductor devices including electrically programmable fuses
Grant 11,094,630 - Li , et al. August 17, 2 | 2021-08-17 |
E-fuse Co-processed With Mim Capacitor
App 20210249348 - Li; Baozhen ; et al. | 2021-08-12 |
Landing Pad In Interconnect And Memory Stacks: Structure And Formation Of The Same
App 20210249053 - Yang; Chih-Chao | 2021-08-12 |
Double replacement metal line patterning
Grant 11,087,993 - Xie , et al. August 10, 2 | 2021-08-10 |
Interconnect And Memory Structures Having Reduced Topography Variation Formed In The Beol
App 20210242216 - Yang; Chih-Chao ; et al. | 2021-08-05 |
Bottom Conductive Structure With A Limited Top Contact Area
App 20210242278 - Yang; Chih-Chao ; et al. | 2021-08-05 |
Planarization Stop Region For Use With Low Pattern Density Interconnects
App 20210242077 - Peethala; Cornelius Brown ; et al. | 2021-08-05 |
Embedded Small Via Anti-fuse Device
App 20210233843 - Yang; Chih-Chao ; et al. | 2021-07-29 |
Efuse Structure With Multiple Links
App 20210233844 - LI; BAOZHEN ; et al. | 2021-07-29 |
Automated method for integrated analysis of back end of the line yield, line resistance/capacitance and process performance
Grant 11,074,387 - Bhosale , et al. July 27, 2 | 2021-07-27 |
Self-aligned Top Via Structure
App 20210225705 - Xie; Ruilong ; et al. | 2021-07-22 |
Fully-aligned Skip-vias
App 20210225760 - Cheng; Kenneth Chun Kuen ; et al. | 2021-07-22 |
Footing Flare Pedestal Structure
App 20210225774 - Yang; Chih-Chao ; et al. | 2021-07-22 |
Removal Or Reduction Of Chamfer For Fully-aligned Via
App 20210225759 - Park; Chanro ; et al. | 2021-07-22 |
Interconnects With Spacer Structure For Forming Air-gaps
App 20210225691 - Cheng; Kenneth Chun Kuen ; et al. | 2021-07-22 |
Liner-free and partial liner-free contact/via structures
Grant 11,069,611 - Yang July 20, 2 | 2021-07-20 |
Modulating metal interconnect surface topography
Grant 11,069,567 - Murray , et al. July 20, 2 | 2021-07-20 |
Interconnects With Hybrid Metal Conductors
App 20210217698 - Cheng; Kenneth Chun Kuen ; et al. | 2021-07-15 |
Top Via Interconnect With Self-aligned Barrier Layer
App 20210217662 - Cheng; Kenneth Chun Kuen ; et al. | 2021-07-15 |
Resistive memory device with meshed electrodes
Grant 11,063,089 - Ando , et al. July 13, 2 | 2021-07-13 |
Metal Surface Preparation For Increased Alignment Contrast
App 20210210434 - Zhou; Tianji ; et al. | 2021-07-08 |
Structural enhancement of Cu nanowires
Grant 11,056,425 - Edelstein , et al. July 6, 2 | 2021-07-06 |
Metallization interconnect structure formation
Grant 11,056,426 - Mignot , et al. July 6, 2 | 2021-07-06 |
Semiconductor Device With Reduced Via Resistance
App 20210183699 - Murray; Conal E. ; et al. | 2021-06-17 |
Material for forming metal matrix composite and metal matrix composite bulk
Grant 11,035,029 - Chou , et al. June 15, 2 | 2021-06-15 |
Planarization of dielectric topography and stopping in dielectric
Grant 11,037,795 - Amanapu , et al. June 15, 2 | 2021-06-15 |
Contact via with pillar of alternating layers
Grant 11,031,542 - Yang , et al. June 8, 2 | 2021-06-08 |
Metal interconnects
Grant 11,031,339 - Patlolla , et al. June 8, 2 | 2021-06-08 |
Low resistance high capacitance density MIM capacitor
Grant 11,031,457 - Li , et al. June 8, 2 | 2021-06-08 |
Embedded anti-fuses for small scale applications
Grant 11,024,577 - Park , et al. June 1, 2 | 2021-06-01 |
Self-aligned cut process for self-aligned via process window
Grant 11,024,539 - Xie , et al. June 1, 2 | 2021-06-01 |
Landing pad in interconnect and memory stacks: structure and formation of the same
Grant 11,024,344 - Yang June 1, 2 | 2021-06-01 |
Resistance Tunable Fuse Structure Formed By Embedded Thin Metal Layers
App 20210159173 - REZNICEK; Alexander ; et al. | 2021-05-27 |
Metal interconnects
Grant 11,018,087 - Patlolla , et al. May 25, 2 | 2021-05-25 |
Selective CVD alignment-mark topography assist for non-volatile memory
Grant 11,018,090 - Rizzolo , et al. May 25, 2 | 2021-05-25 |
On Integrated Circuit (ic) Device Simultaneously Formed Capacitor And Resistor
App 20210151345 - Liang; Jim Shih-Chun ; et al. | 2021-05-20 |
Integrated Circuit (ic) Device Integral Capacitor And Anti-fuse
App 20210151373 - Liang; Jim Shih-Chun ; et al. | 2021-05-20 |
Back End Of Line Structures With Metal Lines With Alternating Patterning And Metallization Schemes
App 20210151327 - Xie; Ruilong ; et al. | 2021-05-20 |
Hybrid Metallization And Dielectric Interconnects In Top Via Configuration
App 20210143061 - AMANAPU; Hari Prasad ; et al. | 2021-05-13 |
Integrated circuit having a single damascene wiring network
Grant 11,004,736 - Chen , et al. May 11, 2 | 2021-05-11 |
Conductive interconnect having a semi-liner and no top surface recess
Grant 11,004,735 - Peethala , et al. May 11, 2 | 2021-05-11 |
Embedding Magneto-resistive Random-access Memory Devices Between Metal Levels
App 20210134883 - DUTTA; Ashim ; et al. | 2021-05-06 |
Metal insulator metal capacitor with extended capacitor plates
Grant 10,998,227 - Yang , et al. May 4, 2 | 2021-05-04 |
Top via process accounting for misalignment by increasing reliability
Grant 10,991,619 - Zhang , et al. April 27, 2 | 2021-04-27 |
Interconnects Having Air Gap Spacers
App 20210118722 - Cheng; Kenneth Chun Kuen ; et al. | 2021-04-22 |
Double Patterning Interconnect Integration Scheme With Sav
App 20210118732 - Chen; Shyng-Tsong ; et al. | 2021-04-22 |
Hard mask films with graded vertical concentration formed using reactive sputtering in a radio frequency deposition chamber
Grant 10,975,464 - De Silva , et al. April 13, 2 | 2021-04-13 |
Electrode with Alloy Interface
App 20210104406 - Yang; Chih-Chao ; et al. | 2021-04-08 |
Cobalt interconnect structure including noble metal layer
Grant 10,971,398 - Standaert , et al. April 6, 2 | 2021-04-06 |
BEOL electrical fuse
Grant 10,971,447 - Yang , et al. April 6, 2 | 2021-04-06 |
Structure And Method To Fabricate Fully Aligned Via With Reduced Contact Resistance
App 20210098287 - Park; Chanro ; et al. | 2021-04-01 |
Fully Aligned Top Vias With Replacement Metal Lines
App 20210098284 - Park; Chanro ; et al. | 2021-04-01 |
Dielectric crack stop for advanced interconnects
Grant 10,964,647 - Li , et al. March 30, 2 | 2021-03-30 |
Controllable Formation Of Recessed Bottom Electrode Contact In A Memory Metallization Stack
App 20210091303 - PATLOLLA; Raghuveer ; et al. | 2021-03-25 |
Controlled Ion Beam Etch of MTJ
App 20210091306 - Dutta; Ashim ; et al. | 2021-03-25 |
Beol Alternative Metal Interconnects: Integration And Process
App 20210091010 - Yang; Chih-Chao ; et al. | 2021-03-25 |
Interconnect Structures Including Self Aligned Vias
App 20210090942 - Yang; Chih-Chao ; et al. | 2021-03-25 |
Resistance Tunable Fuse Structure Formed By Embedded Thin Metal Layers
App 20210090996 - REZNICEK; Alexander ; et al. | 2021-03-25 |
Interconnects Having Air Gap Spacers
App 20210090938 - Cheng; Kenneth Chun Kuen ; et al. | 2021-03-25 |
Advanced crack stop structure
Grant 10,957,657 - Yang , et al. March 23, 2 | 2021-03-23 |
Resistance tunable fuse structure formed by embedded thin metal layers
Grant 10,957,642 - Reznicek , et al. March 23, 2 | 2021-03-23 |
Formation of semiconductor devices including electrically programmable fuses
Grant 10,957,643 - Li , et al. March 23, 2 | 2021-03-23 |
Back End Of Line Structures With Metal Lines With Alternating Patterning And Metallization Schemes
App 20210082714 - Xie; Ruilong ; et al. | 2021-03-18 |
Bilayer Barrier For Interconnect And Memory Structures Formed In The Beol
App 20210082751 - Yang; Chih-Chao ; et al. | 2021-03-18 |
Back end of line structures with metal lines with alternating patterning and metallization schemes
Grant 10,950,459 - Xie , et al. March 16, 2 | 2021-03-16 |
Method having resistive memory crossbar array employing selective barrier layer growth
Grant 10,950,787 - Ando , et al. March 16, 2 | 2021-03-16 |
Resistive memory device with meshed electrodes
Grant 10,950,662 - Ando , et al. March 16, 2 | 2021-03-16 |
Interconnects having air gap spacers
Grant 10,950,493 - Cheng , et al. March 16, 2 | 2021-03-16 |
Precision BEOL resistors
Grant 10,943,972 - Li , et al. March 9, 2 | 2021-03-09 |
Self-formed liner for interconnect structures
Grant 10,930,520 - Yang February 23, 2 | 2021-02-23 |
Advanced interconnects containing an IMT liner
Grant 10,930,589 - Maniscalco , et al. February 23, 2 | 2021-02-23 |
Self-aligned Top Via Scheme
App 20210050259 - Xie; Ruilong ; et al. | 2021-02-18 |
Double Replacement Metal Line Patterning
App 20210043462 - Xie; Ruilong ; et al. | 2021-02-11 |
Back end of line electrical fuse structure and method of fabrication
Grant 10,916,501 - Briggs , et al. February 9, 2 | 2021-02-09 |
Back end of line metallization structure
Grant 10,916,503 - Yang February 9, 2 | 2021-02-09 |
Resistive memory crossbar array employing selective barrier layer growth
Grant 10,916,699 - Ando , et al. February 9, 2 | 2021-02-09 |
Planarization of Dielectric Topography and Stopping in Dielectric
App 20210035813 - Amanapu; Hari Prasad ; et al. | 2021-02-04 |
Switchable Metal Insulator Metal Capacitor
App 20210036096 - Li; Baozhen ; et al. | 2021-02-04 |
Back end of line metallization structure
Grant 10,910,307 - Patlolla , et al. February 2, 2 | 2021-02-02 |
Interconnect And Memory Structures Formed In The Beol
App 20210028107 - Yang; Chih-Chao ; et al. | 2021-01-28 |
Back end of line metallization structure
Grant 10,903,161 - Patlolla , et al. January 26, 2 | 2021-01-26 |
Void-free metallic interconnect structures with self-formed diffusion barrier layers
Grant 10,903,116 - Maniscalco , et al. January 26, 2 | 2021-01-26 |
Controlling grain boundaries in high aspect-ratio conductive regions
Grant 10,903,115 - Murray , et al. January 26, 2 | 2021-01-26 |
Extreme ultraviolet (EUV) lithography patterning methods utilizing EUV resist hardening
Grant 10,901,317 - Briggs , et al. January 26, 2 | 2021-01-26 |
Fuse element resistance enhancement by laser anneal and ion implantation
Grant 10,903,162 - Jiang , et al. January 26, 2 | 2021-01-26 |
Fabricating vias with lower resistance
Grant 10,903,117 - Li , et al. January 26, 2 | 2021-01-26 |
Fabrication Of Phase Change Memory Cell In Integrated Circuit
App 20210020836 - Li; Baozhen ; et al. | 2021-01-21 |
Integrated Circuit Having A Single Damascene Wiring Network
App 20210020507 - Chen; Hsueh-Chung ; et al. | 2021-01-21 |
Metallization Layer Formation Process
App 20210020565 - Cheng; Kangguo ; et al. | 2021-01-21 |
Controlling performance and reliability of conductive regions in a metallization network
Grant 10,896,846 - Patlolla , et al. January 19, 2 | 2021-01-19 |
Interconnect Architecture With Enhanced Reliability
App 20210013097 - Li; Baozhen ; et al. | 2021-01-14 |
Dielectric surface modification in sub-40nm pitch interconnect patterning
Grant 10,886,166 - Lanzillo , et al. January 5, 2 | 2021-01-05 |
BEOL alternative metal interconnects: integration and process
Grant 10,886,225 - Yang , et al. January 5, 2 | 2021-01-05 |
Surface modified dielectric refill structure
Grant 10,886,168 - Yang , et al. January 5, 2 | 2021-01-05 |
Patterning integration scheme with trench alignment marks
Grant 10,879,190 - Yang , et al. December 29, 2 | 2020-12-29 |
Mram Integration With Beol Interconnect Including Top Via
App 20200403032 - Dutta; Ashim ; et al. | 2020-12-24 |
Beol Electrical Fuse And Method Of Forming The Same
App 20200402907 - Yang; Chih-Chao ; et al. | 2020-12-24 |
Self-aligned Cut Process For Self-aligned Via Process Window
App 20200402852 - Xie; Ruilong ; et al. | 2020-12-24 |
Interconnects With Gouged Vias
App 20200402844 - Cheng; Kenneth Chun Kuen ; et al. | 2020-12-24 |
Surface Modified Dielectric Refill Structure
App 20200388524 - Yang; Chih-Chao ; et al. | 2020-12-10 |
Bottom Electrode Structure And Method Of Forming The Same
App 20200388757 - Yang; Chih-Chao ; et al. | 2020-12-10 |
Metallization Interconnect Structure Formation
App 20200381354 - Mignot; Yann ; et al. | 2020-12-03 |
Advanced crack stop structure
Grant 10,847,475 - Yang , et al. November 24, 2 | 2020-11-24 |
BEOL electrical fuse and method of forming the same
Grant 10,847,458 - Yang , et al. November 24, 2 | 2020-11-24 |
Fabrication of phase change memory cell in integrated circuit
Grant 10,840,447 - Li , et al. November 17, 2 | 2020-11-17 |
Low resistance metal-insulator-metal capacitor electrode
Grant 10,840,325 - Maniscalco , et al. November 17, 2 | 2020-11-17 |
Advanced crack stop structure
Grant 10,840,195 - Yang , et al. November 17, 2 | 2020-11-17 |
Advanced crack stop structure
Grant 10,840,194 - Yang , et al. November 17, 2 | 2020-11-17 |
Forming gate contact over active free of metal recess
Grant 10,832,963 - Cheng , et al. November 10, 2 | 2020-11-10 |
Circular ring shape fuse device
Grant 10,833,007 - Yang November 10, 2 | 2020-11-10 |
Resistive memory crossbar array with ruthenium protection layer
Grant 10,833,266 - Ando , et al. November 10, 2 | 2020-11-10 |
MRAM device formation with in-situ encapsulation
Grant 10,833,258 - Dutta , et al. November 10, 2 | 2020-11-10 |
Formation of embedded magnetic random-access memory devices with multi-level bottom electrode via contacts
Grant 10,833,257 - Dutta , et al. November 10, 2 | 2020-11-10 |
Three-dimensional and planar memory device co-integration
Grant 10,833,127 - Ando , et al. November 10, 2 | 2020-11-10 |
Contact Via
App 20200350486 - Yang; Chih-Chao ; et al. | 2020-11-05 |
Patterning Integration Scheme With Trench Alignment Marks
App 20200350257 - Yang; Chih-Chao ; et al. | 2020-11-05 |
Mram Device Formation With In-situ Encapsulation
App 20200350495 - Dutta; Ashim ; et al. | 2020-11-05 |
Formation Of Embedded Magnetic Random-access Memory Devices With Multi-level Bottom Electrode Via Contacts
App 20200350494 - Dutta; Ashim ; et al. | 2020-11-05 |
Metal bonding pads for packaging applications
Grant 10,825,792 - Yang November 3, 2 | 2020-11-03 |
Via-to-metal Tip Connections In Multi-layer Chips
App 20200343186 - Xie; Ruilong ; et al. | 2020-10-29 |
Metal interconnect structures with self-forming sidewall barrier layer
Grant 10,818,589 - Amanapu , et al. October 27, 2 | 2020-10-27 |
Method and structure for cost effective enhanced self-aligned contacts
Grant 10,818,548 - Lai , et al. October 27, 2 | 2020-10-27 |
Top Via Process Accounting For Misalignment By Increasing Reliability
App 20200335393 - Zhang; Chen ; et al. | 2020-10-22 |
Sub-ground Rule E-fuse Structure
App 20200335440 - Kim; Andrew T. ; et al. | 2020-10-22 |
Sub-ground rule e-Fuse structure
Grant 10,811,353 - Li , et al. October 20, 2 | 2020-10-20 |
Co-fabrication of magnetic device structures with electrical interconnects having reduced resistance through increased conductor grain size
Grant 10,811,599 - Clevenger , et al. October 20, 2 | 2020-10-20 |
Bamboo Tall Via Interconnect Structures
App 20200328112 - Yang; Chih-Chao ; et al. | 2020-10-15 |
Low Aspect Ratio Interconnect
App 20200328156 - Briggs; Benjamin D. ; et al. | 2020-10-15 |
Fabrication Of Embedded Memory Devices Utilizing A Self Assembled Monolayer
App 20200328251 - DUTTA; Ashim ; et al. | 2020-10-15 |
Semiconductor device with reduced via resistance
Grant 10,804,147 - Murray , et al. October 13, 2 | 2020-10-13 |
Hardmask stress, grain, and structure engineering for advanced memory applications
Grant 10,796,911 - Rizzolo , et al. October 6, 2 | 2020-10-06 |
Protuberant contacts for resistive switching devices
Grant 10,790,445 - Ando , et al. September 29, 2 | 2020-09-29 |
Semiconductor device and method of forming the semiconductor device
Grant 10,784,159 - Clevenger , et al. Sept | 2020-09-22 |
Fabrication Of Phase Change Memory Cell In Integrated Circuit
App 20200295261 - Li; Baozhen ; et al. | 2020-09-17 |
Metal Interconnect Structures with Self-Forming Sidewall Barrier Layer
App 20200294911 - Amanapu; Hari Prasad ; et al. | 2020-09-17 |
Contact via structures
Grant 10,777,735 - Yang , et al. Sept | 2020-09-15 |
Dielectric Surface Modification In Sub-40nm Pitch Interconnect Patterning
App 20200286776 - Lanzillo; Nicholas Anthony ; et al. | 2020-09-10 |
Fabricating Vias With Lower Resistance
App 20200286780 - Li; Baozhen ; et al. | 2020-09-10 |
Fuse Element Resistance Enhancement By Laser Anneal And Ion Implantation
App 20200286827 - Jiang; Liying ; et al. | 2020-09-10 |
Reliable Resistive Random Access Memory
App 20200287136 - Li; Baozhen ; et al. | 2020-09-10 |
Three-dimensional And Planar Memory Device Co-integration
App 20200286956 - Ando; Takashi ; et al. | 2020-09-10 |
BEOL thin film resistor
Grant 10,770,393 - Kim , et al. Sep | 2020-09-08 |
Silicon carbide and silicon nitride interconnects
Grant 10,770,395 - Yang Sep | 2020-09-08 |
Metal resistor structures with nitrogen content
Grant 10,770,537 - Yang Sep | 2020-09-08 |
Circular ring shaped antifuse device
Grant 10,763,210 - Yang , et al. Sep | 2020-09-01 |
Film stress control for memory device stack
Grant 10,763,431 - Ok , et al. Sep | 2020-09-01 |
Single Process For Liner And Metal Fill
App 20200273708 - Adusumilli; Praneet ; et al. | 2020-08-27 |
Air-Gap Containing Metal Interconnects
App 20200273743 - Cheng; Kenneth C. K. ; et al. | 2020-08-27 |
Co-fabrication of magnetic device structures with electrical interconnects having reduced resistance through increased conductor grain size
Grant 10,756,260 - Clevenger , et al. A | 2020-08-25 |
Air-gap containing metal interconnects
Grant 10,748,812 - Cheng , et al. A | 2020-08-18 |
Liner planarization-free process flow for fabricating metallic interconnect structures
Grant 10,741,397 - Yang A | 2020-08-11 |
Back end of line metallization structures
Grant 10,741,748 - Maniscalco , et al. A | 2020-08-11 |
Collar formation for chamfer-less and chamfered vias
Grant 10,741,441 - Li , et al. A | 2020-08-11 |
Pre-patterned etch stop for interconnect trench formation overlying embedded MRAM structures
Grant 10,741,609 - Muthinti , et al. A | 2020-08-11 |
Fully aligned semiconductor device with a skip-level via
Grant 10,741,751 - Lanzillo , et al. A | 2020-08-11 |
Rework For Metal Interconnects Using Etch And Thermal Anneal
App 20200251386 - Kind Code | 2020-08-06 |
Protuberant contacts for resistive switching devices
Grant 10,734,579 - Ando , et al. | 2020-08-04 |
Top via back end of the line interconnect integration
Grant 10,734,277 - Yang , et al. | 2020-08-04 |
Interconnect structure with fully self-aligned via pattern formation
Grant 10,727,123 - Lai , et al. | 2020-07-28 |
Liner-less contact metallization
Grant 10,727,070 - Adusumilli , et al. | 2020-07-28 |
Advanced Copper Interconnects With Hybrid Microstructure
App 20200227317 - Edelstein; Daniel C. ; et al. | 2020-07-16 |
Reducing contact resistance in vias for copper interconnects
Grant 10,714,379 - Murray , et al. | 2020-07-14 |
Controlling performance and reliability of conductive regions in a metallization network
Grant 10,714,382 - Patlolla , et al. | 2020-07-14 |
Directional deposition of protection layer
Grant 10,714,596 - He , et al. | 2020-07-14 |
Circular Ring Shaped Antifuse Device
App 20200219811 - Yang; Chih-Chao ; et al. | 2020-07-09 |
Back End Of Line Integration For Interconnects
App 20200219759 - Peethala; Cornelius B. ; et al. | 2020-07-09 |
Circular Ring Shape Fuse Device
App 20200219812 - Yang; Chih-Chao | 2020-07-09 |
Pre-patterned Etch Stop For Interconnect Trench Formation Overlying Embedded Mram Structures
App 20200219932 - MUTHINTI; GANGADHARA RAJA ; et al. | 2020-07-09 |
Advanced metal interconnects
Grant 10,707,166 - Yang | 2020-07-07 |
Formation of embedded magnetic random-access memory devices
Grant 10,707,413 - Dutta , et al. | 2020-07-07 |
Front-end-of-line shape merging cell placement and optimization
Grant 10,699,050 - Wolpert , et al. | 2020-06-30 |
Back end of line integration for interconnects
Grant 10,699,945 - Peethala , et al. | 2020-06-30 |
Metal Matrix Composite Material And Metal Matrix Composite Bulk
App 20200199721 - Chou; Li-Shing ; et al. | 2020-06-25 |
Hardmask Stress, Grain, And Structure Engineering For Advanced Memory Applications
App 20200203164 - Rizzolo; Michael ; et al. | 2020-06-25 |
Metal-ceramic Composite Material And Method For Forming The Same
App 20200199714 - CHEN; Chi-San ; et al. | 2020-06-25 |
Metal Matrix Composite Material And Metal Matrix Composite Bulk
App 20200199722 - Chou; Li-Shing ; et al. | 2020-06-25 |
Single process for linear and metal fill
Grant 10,692,722 - Adusumilli , et al. | 2020-06-23 |
Dielectric fill for memory pillar elements
Grant 10,692,925 - Rizzolo , et al. | 2020-06-23 |
Back end of line metallization structures
Grant 10,686,126 - Maniscalco , et al. | 2020-06-16 |
Back-end-of-the line capacitor
Grant 10,685,784 - Yang | 2020-06-16 |
Contact via structures
Grant 10,686,124 - Yang , et al. | 2020-06-16 |
Via contact resistance control
Grant 10,685,915 - Yang , et al. | 2020-06-16 |
Multi-buried ULK field in BEOL structure
Grant 10,679,892 - Mignot , et al. | 2020-06-09 |
Metallic interconnect structures with wrap around capping layers
Grant 10,672,653 - Peethala , et al. | 2020-06-02 |
Advanced BEOL interconnect architecture
Grant 10,672,649 - Yang , et al. | 2020-06-02 |
Low aspect ratio interconnect
Grant 10,672,707 - Briggs , et al. | 2020-06-02 |
Hardmask stress, grain, and structure engineering for advanced memory applications
Grant 10,672,611 - Rizzolo , et al. | 2020-06-02 |
Top Via Back End Of The Line Interconnect Integration
App 20200161175 - Yang; Chih-Chao ; et al. | 2020-05-21 |
Film Stress Control For Memory Device Stack
App 20200161547 - Ok; Injo ; et al. | 2020-05-21 |
Back End Of Line Electrical Fuse Structure And Method Of Fabrication
App 20200161239 - Briggs; Benjamin D. ; et al. | 2020-05-21 |
Tall Trenches For Via Chamferless And Self Forming Barrier
App 20200161180 - MIGNOT; Yann ; et al. | 2020-05-21 |
Dedicated contacts for controlled electroforming of memory cells in resistive random-access memory array
Grant 10,658,585 - Ando , et al. | 2020-05-19 |
Rework for metal interconnects using etch and thermal anneal
Grant 10,658,235 - Bhosale , et al. | 2020-05-19 |
Metallic Interconnect Structures With Wrap Around Capping Layers
App 20200152511 - Peethala; Cornelius Brown ; et al. | 2020-05-14 |
Metallic Interconnect Structures With Wrap Around Capping Layers
App 20200152510 - Peethala; Cornelius Brown ; et al. | 2020-05-14 |
Graded interconnect cap
Grant 10,651,083 - Kim , et al. | 2020-05-12 |
Back End Of Line Metallization Structure
App 20200144178 - Patlolla; Raghuveer R. ; et al. | 2020-05-07 |
Metal Insulator Metal Capacitor With Extended Capacitor Plates
App 20200144113 - Yang; Chih-Chao ; et al. | 2020-05-07 |
Back End Of Line Metallization Structure
App 20200144180 - Patlolla; Raghuveer R. ; et al. | 2020-05-07 |
Silicon Carbide And Silicon Nitride Interconnects
App 20200144195 - Yang; Chih-Chao | 2020-05-07 |
Bottom Electrode For Semiconductor Memory Device
App 20200144498 - Yang; Chih-Chao ; et al. | 2020-05-07 |
Ultrathin multilayer metal alloy liner for nano Cu interconnects
Grant 10,643,890 - Edelstein , et al. | 2020-05-05 |
Back-end-of-the Line Capacitor
App 20200135407 - Yang; Chih-Chao | 2020-04-30 |
Controlling Grain Boundaries In High Aspect-ratio Conductive Regions
App 20200135556 - Murray; Conal ; et al. | 2020-04-30 |
Fully Aligned Semiconductor Device With A Skip-level Via
App 20200136028 - Lanzillo; Nicholas A. ; et al. | 2020-04-30 |
Cobalt Interconnect Structure
App 20200135558 - Standaert; Theodorus E. ; et al. | 2020-04-30 |
Hardmask Stress, Grain, And Structure Engineering For Advanced Memory Applications
App 20200126791 - Rizzolo; Michael ; et al. | 2020-04-23 |
Sub-ground Rule E-fuse Structure
App 20200126911 - Li; Baozhen ; et al. | 2020-04-23 |
Controlling Performance And Reliability Of Conductive Regions In A Metallization Network
App 20200118866 - Patlolla; Raghuveer ; et al. | 2020-04-16 |
Controlling Performance And Reliability Of Conductive Regions In A Metallization Network
App 20200118865 - Patlolla; Raghuveer ; et al. | 2020-04-16 |
Wet Clean Solutions To Prevent Pattern Collapse
App 20200118808 - Peethala; Cornelius B. ; et al. | 2020-04-16 |
Advanced Crack Stop Structure
App 20200118943 - Yang; Chih-Chao ; et al. | 2020-04-16 |
Dielectric Fill For Memory Pillar Elements
App 20200119089 - Rizzolo; Michael ; et al. | 2020-04-16 |
Back End Of Line Integration For Interconnects
App 20200111699 - Peethala; Cornelius B. ; et al. | 2020-04-09 |
Resistive Memory Crossbar Array With Ruthenium Protection Layer
App 20200111958 - Ando; Takashi ; et al. | 2020-04-09 |
Resistive Memory Device With Meshed Electrodes
App 20200111838 - Ando; Takashi ; et al. | 2020-04-09 |
Resistive Memory Device With Meshed Electrodes
App 20200111837 - Ando; Takashi ; et al. | 2020-04-09 |
Vertical Electrical Fuse
App 20200111741 - Yang; Chih-Chao ; et al. | 2020-04-09 |
Landing Pad In Interconnect And Memory Stacks: Structure And Formation Of The Same
App 20200111511 - Yang; Chih-Chao | 2020-04-09 |
MIM capacitor for improved process defect tolerance
Grant 10,615,112 - Li , et al. | 2020-04-07 |
Surface nitridation in metal interconnects
Grant 10,615,116 - Clevenger , et al. | 2020-04-07 |
Advanced copper interconnects with hybrid microstructure
Grant 10,615,074 - Edelstein , et al. | 2020-04-07 |
Back end of line electrical fuse structure and method of fabrication
Grant 10,615,119 - Briggs , et al. | 2020-04-07 |
Collar Formation For Chamfer-less And Chamfered Vias
App 20200105590 - Li; Baozhen ; et al. | 2020-04-02 |
Improved Bottom Electrode For Semiconductor Memory Device
App 20200098975 - Yang; Chih-Chao ; et al. | 2020-03-26 |
Controlling grain boundaries in high aspect-ratio conductive regions
Grant 10,600,686 - Murray , et al. | 2020-03-24 |
Semiconductor Device With Reduced Via Resistance
App 20200090993 - Murray; Conal E. ; et al. | 2020-03-19 |
Protuberant Contacts For Resistive Switching Devices
App 20200091427 - Ando; Takashi ; et al. | 2020-03-19 |
Liner-free And Partial Liner-free Contact/via Structures
App 20200091067 - Yang; Chih-Chao | 2020-03-19 |
Semiconductor Device With Reduced Via Resistance
App 20200090994 - Murray; Conal E. ; et al. | 2020-03-19 |
Conductive Interconnect Having A Semi-liner And No Top Surface Recess
App 20200090988 - Peethala; Cornelius B. ; et al. | 2020-03-19 |
Automated Method For Integrated Analysis Of Back End Of The Line Yield, Line Resistance/capacitance And Process Performance
App 20200089831 - Bhosale; Prasad ; et al. | 2020-03-19 |
Contact Via Structures
App 20200083426 - YANG; Chih-Chao ; et al. | 2020-03-12 |
Back End Of Line Metallization Structure
App 20200083174 - YANG; Chih-Chao | 2020-03-12 |
Metal Interconnects
App 20200083169 - Patlolla; Raghuveer R. ; et al. | 2020-03-12 |
Back End Of Line Metallization Structures
App 20200083435 - Maniscalco; Joseph F. ; et al. | 2020-03-12 |
Contact Via Structures
App 20200083436 - YANG; Chih-Chao ; et al. | 2020-03-12 |
Automated method for integrated analysis of back end of the line yield, line resistance/capacitance and process performance
Grant 10,585,998 - Bhosale , et al. | 2020-03-10 |
Via cleaning to reduce resistance
Grant 10,586,732 - Mignot , et al. | 2020-03-10 |
Resistive Memory Crossbar Array Employing Selective Barrier Layer Growth
App 20200066982 - Ando; Takashi ; et al. | 2020-02-27 |
Forming Gate Contact Over Active Free of Metal Recess
App 20200066597 - Cheng; Kangguo ; et al. | 2020-02-27 |
Selective Ion Filtering In A Multipurpose Chamber
App 20200066491 - Clevenger; Lawrence A. ; et al. | 2020-02-27 |
Via Cleaning To Reduce Resistance
App 20200066577 - Mignot; Yann A.M. ; et al. | 2020-02-27 |
Resistive Memory Crossbar Array Employing Selective Barrier Layer Growth
App 20200066983 - Ando; Takashi ; et al. | 2020-02-27 |
Reducing Contact Resistance In Vias For Copper Interconnects
App 20200066576 - Murray; Conal E. ; et al. | 2020-02-27 |
Formation Of Semiconductor Devices Including Electrically Programmable Fuses
App 20200058588 - Li; Juntao ; et al. | 2020-02-20 |
Selective Cvd Alignment-mark Topography Assist For Non-volatile Memory
App 20200058594 - Rizzolo; Michael ; et al. | 2020-02-20 |
Formation Of Semiconductor Devices Including Electrically Programmable Fuses
App 20200058587 - Li; Juntao ; et al. | 2020-02-20 |
Microstructure modulation for metal wafer-wafer bonding
Grant 10,566,314 - Yang Feb | 2020-02-18 |
Advanced Crack Stop Structure
App 20200051930 - Yang; Chih-Chao ; et al. | 2020-02-13 |
Selective Cvd Alignment-mark Topography Assist For Non-volatile Memory
App 20200051924 - Rizzolo; Michael ; et al. | 2020-02-13 |
Semiconductor Tool Matching And Manufacturing Management In A Blockchain
App 20200053128 - Bhosale; Prasad ; et al. | 2020-02-13 |
Metal insulator metal capacitor with extended capacitor plates
Grant 10,559,649 - Yang , et al. Feb | 2020-02-11 |
Bottom electrode for semiconductor memory device
Grant 10,559,751 - Yang , et al. Feb | 2020-02-11 |
Fully aligned semiconductor device with a skip-level via
Grant 10,553,789 - Lanzillo , et al. Fe | 2020-02-04 |
Semiconductor device with reduced via resistance
Grant 10,553,483 - Murray , et al. Fe | 2020-02-04 |
Formation of semiconductor devices including electrically programmable fuses
Grant 10,553,535 - Li , et al. Fe | 2020-02-04 |
Advanced Crack Stop Structure
App 20200035620 - Yang; Chih-Chao ; et al. | 2020-01-30 |
Advanced Crack Stop Structure
App 20200035621 - Yang; Chih-Chao ; et al. | 2020-01-30 |
Liner-free and partial liner-free contact/via structures
Grant 10,546,812 - Yang Ja | 2020-01-28 |
Resistive memory device with meshed electrodes
Grant 10,546,892 - Ando , et al. Ja | 2020-01-28 |
Advanced Interconnects Containing An Imt Liner
App 20200027829 - Maniscalco; Joseph F. ; et al. | 2020-01-23 |
Formation Of Semiconductor Devices Including Electrically Programmable Fuses
App 20200027830 - Li; Juntao ; et al. | 2020-01-23 |
BEOL integration with advanced interconnects
Grant 10,541,199 - Yang Ja | 2020-01-21 |
Void-free Metallic Interconnect Structures With Self-formed Diffusion Barrier Layers
App 20200020581 - Maniscalco; Joseph F. ; et al. | 2020-01-16 |
Void-free Metallic Interconnect Structures With Self-formed Diffusion Barrier Layers
App 20200020577 - Maniscalco; Joseph F. ; et al. | 2020-01-16 |
Liner-free And Partial Liner-free Contact/via Structures
App 20200020626 - Yang; Chih-Chao | 2020-01-16 |
Hybrid back end of line metallization to balance performance and reliability
Grant 10534888 - | 2020-01-14 |
Lithographic photomask alignment using non-planar alignment structures formed on wafer
Grant 10,534,276 - Yang , et al. Ja | 2020-01-14 |
Rework For Metal Interconnects Using Etch And Thermal Anneal
App 20190393085 - Bhosale; Prasad ; et al. | 2019-12-26 |
Back End Of Line Metallization Structures
App 20190393409 - Maniscalco; Joseph F. ; et al. | 2019-12-26 |
Selective CVD alignment-mark topography assist for non-volatile memory
Grant 10515903 - | 2019-12-24 |
Interconnect Structure With Fully Self-aligned Via Pattern Formation
App 20190385910 - Lai; Kafai ; et al. | 2019-12-19 |
Extreme Ultraviolet (euv) Lithography Patterning Methods Utilizing Euv Resist Hardening
App 20190384180 - Briggs; Benjamin D. ; et al. | 2019-12-19 |
Secondary use of aspect ratio trapping trenches as resistor structures
Grant 10510829 - | 2019-12-17 |
Controlling Grain Boundaries In High Aspect-ratio Conductive Regions
App 20190378755 - Murray; Conal ; et al. | 2019-12-12 |
Interconnect Structure
App 20190371656 - Chen; Hsueh-Chung ; et al. | 2019-12-05 |
Semiconductor Device And Method Of Forming The Semiconductor Device
App 20190363013 - CLEVENGER; Lawrence A. ; et al. | 2019-11-28 |
Advanced crack stop structure
Grant 10490513 - | 2019-11-26 |
Selective Cvd Alignment-mark Topography Assist For Non-volatile Memory
App 20190355668 - Rizzolo; Michael ; et al. | 2019-11-21 |
Selective Ion Filtering In A Multipurpose Chamber
App 20190355555 - Clevenger; Lawrence A. ; et al. | 2019-11-21 |
Dielectric Crack Stop For Advanced Interconnects
App 20190348377 - Li; Baozhen ; et al. | 2019-11-14 |
Secondary Use Of Aspect Ratio Trapping Trenches As Resistor Structures
App 20190348497 - REZNICEK; Alexander ; et al. | 2019-11-14 |
Advanced crack stop structure
Grant 10475753 - | 2019-11-12 |
Forming resistive memory crossbar array employing selective barrier layer growth
Grant 10475997 - | 2019-11-12 |
Front-end-of-line Shape Merging Cell Placement And Optimization
App 20190340324 - WOLPERT; David ; et al. | 2019-11-07 |
Via Contact Resistance Control
App 20190341298 - Yang; Chih-Chao ; et al. | 2019-11-07 |
Mim Capacitor For Improved Process Defect Tolerance
App 20190341347 - Li; Baozhen ; et al. | 2019-11-07 |
Metal Insulator Metal Capacitor With Extended Capacitor Plates
App 20190341307 - Yang; Chih-Chao ; et al. | 2019-11-07 |
Metal Interconnects
App 20190333857 - Patlolla; Raghuveer R. ; et al. | 2019-10-31 |
Metal Embedded Low-resistance Beol Antifuse
App 20190326215 - REZNICEK; Alexander ; et al. | 2019-10-24 |
Modulating Metal Interconnect Surface Topography
App 20190318962 - Murray; Conal ; et al. | 2019-10-17 |
Low Resistance Metal-insulator-metal Capacitor Electrode
App 20190319088 - Maniscalco; Joseph F. ; et al. | 2019-10-17 |
Hard Mask Films With Graded Vertical Concentration Formed Using Reactive Sputtering In A Radio Frequency Deposition Chamber
App 20190309410 - De Silva; Ekmini Anuja ; et al. | 2019-10-10 |
Advanced Interconnects Containing An Imt Liner
App 20190311985 - Maniscalco; Joseph F. ; et al. | 2019-10-10 |
Metal Bonding Pads For Packaging Applications
App 20190304948 - YANG; CHIH-CHAO | 2019-10-03 |
Advanced Crack Stop Structure
App 20190304929 - Yang; Chih-Chao ; et al. | 2019-10-03 |
Advanced Crack Stop Structure
App 20190304928 - Yang; Chih-Chao ; et al. | 2019-10-03 |
Beol Thin Film Resistor
App 20190295947 - Kim; Andrew Tae ; et al. | 2019-09-26 |
Liner Planarization-free Process Flow For Fabricating Metallic Interconnect Structures
App 20190279873 - Yang; Chih-Chao | 2019-09-12 |
Co-fabrication Of Magnetic Device Structures With Electrical Interconnects Having Reduced Resistance Through Increased Conductor
App 20190280196 - Clevenger; Lawrence A. ; et al. | 2019-09-12 |
Precision Beol Resistors
App 20190280080 - Li; Baozhen ; et al. | 2019-09-12 |
| 