loadpatents
name:-0.016921997070312
name:-0.016431093215942
name:-0.00057005882263184
Cowley; Andrew P. Patent Filings

Cowley; Andrew P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Cowley; Andrew P..The latest application filed is for "via bottom contact and method of manufacturing same".

Company Profile
0.14.16
  • Cowley; Andrew P. - Wappingers Falls NY
  • Cowley; Andrew P. - Hopewell Junction NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method for prediction of premature dielectric breakdown in a semiconductor
Grant 8,053,257 - Chanda , et al. November 8, 2
2011-11-08
Via bottom contact and method of manufacturing same
Grant 7,830,019 - Chanda , et al. November 9, 2
2010-11-09
Structure for modeling stress-induced degradation of conductive interconnects
Grant 7,692,439 - Chanda , et al. April 6, 2
2010-04-06
Structure for monitoring stress-induced degradation of conductive interconnects
Grant 7,639,032 - Chanda , et al. December 29, 2
2009-12-29
Interconnect structure
Grant 7,598,616 - Yang , et al. October 6, 2
2009-10-06
VIA bottom contact and method of manufacturing same
Grant 7,585,764 - Chanda , et al. September 8, 2
2009-09-08
Via Bottom Contact And Method Of Manufacturing Same
App 20090200673 - Chanda; Kaushik ;   et al.
2009-08-13
Method of fabrication of interconnect structures
Grant 7,563,710 - Yang , et al. July 21, 2
2009-07-21
Interconnect structure and method of fabrication of same
Grant 7,528,493 - Yang , et al. May 5, 2
2009-05-05
Back end interconnect with a shaped interface
Grant 7,494,915 - Clevenger , et al. February 24, 2
2009-02-24
Interconnect Structure And Method Of Fabrication Of Same
App 20080246151 - Yang; Chih-Chao ;   et al.
2008-10-09
Structure for modeling stress-induced degradation of conductive interconnects
App 20080231312 - Chanda; Kaushik ;   et al.
2008-09-25
Method For Prediction Of Premature Dielectric Breakdown In A Semiconductor
App 20080174334 - Chanda; Kaushik ;   et al.
2008-07-24
Structure and method for monitoring stress-induced degradation of conductive interconnects
Grant 7,397,260 - Chanda , et al. July 8, 2
2008-07-08
Method for monitoring stress-induced degradation of conductive interconnects
App 20080107149 - Chanda; Kaushik ;   et al.
2008-05-08
Interconnect structure and method of fabrication of same
Grant 7,335,588 - Yang , et al. February 26, 2
2008-02-26
Interconnect Structure And Method Of Fabrication Of Same
App 20080014744 - Yang; Chih-Chao ;   et al.
2008-01-17
Interconnect Structure And Method Of Fabrication Of Same
App 20080006944 - Yang; Chih-Chao ;   et al.
2008-01-10
Structure And Method For Monitoring Stress-induced Degradation Of Conductive Interconnects
App 20070115018 - Chanda; Kaushik ;   et al.
2007-05-24
Post-etch removal of fluorocarbon-based residues from a hybrid dielectric structure
App 20070059922 - Clevenger; Lawrence A. ;   et al.
2007-03-15
Via Bottom Contact And Method Of Manufacturing Same
App 20070037403 - Chanda; Kaushik ;   et al.
2007-02-15
Back End Interconnect With A Shaped Interface
App 20060292852 - Clevenger; Lawrence A. ;   et al.
2006-12-28
Method For Prediction Of Premature Dielectric Breakdown In A Semiconductor
App 20060281338 - Chanda; Kaushik ;   et al.
2006-12-14
Interconnect structure and method of fabrication of same
App 20060234497 - Yang; Chih-Chao ;   et al.
2006-10-19
Back end interconnect with a shaped interface
Grant 7,122,462 - Clevenger , et al. October 17, 2
2006-10-17
Crystallographic modification of hard mask properties
Grant 7,001,835 - Clevenger , et al. February 21, 2
2006-02-21
Back End Interconnect With a Shaped Interface
App 20050112864 - Clevenger, Lawrence A. ;   et al.
2005-05-26
Crystallographic Modification of Hard mask Properties
App 20050112862 - Clevenger, Lawrence A. ;   et al.
2005-05-26
Method of forming an on-chip decoupling capacitor with bottom hardmask
Grant 6,387,754 - Dalton , et al. May 14, 2
2002-05-14
Method of forming an on-chip decoupling capacitor with bottom hardmask
App 20010036753 - Dalton, Timothy J. ;   et al.
2001-11-01

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed