U.S. patent application number 11/418577 was filed with the patent office on 2006-09-28 for using different gate dielectrics with nmos and pmos transistors of a complementary metal oxide semiconductor integrated circuit.
Invention is credited to Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Jack Kavalieros, Matthew V. Metz.
Application Number | 20060214237 11/418577 |
Document ID | / |
Family ID | 34981845 |
Filed Date | 2006-09-28 |
United States Patent
Application |
20060214237 |
Kind Code |
A1 |
Metz; Matthew V. ; et
al. |
September 28, 2006 |
Using different gate dielectrics with NMOS and PMOS transistors of
a complementary metal oxide semiconductor integrated circuit
Abstract
Complementary metal oxide semiconductor integrated circuits may
be formed with NMOS and PMOS transistors having different gate
dielectrics. The different gate dielectrics may be formed, for
example, by a replacement process. The gate dielectrics may differ
in material, thickness, or formation techniques, as a few
examples.
Inventors: |
Metz; Matthew V.;
(Hillsboro, OR) ; Datta; Suman; (Beaverton,
OR) ; Kavalieros; Jack; (Portland, OR) ;
Doczy; Mark L.; (Beaverton, OR) ; Brask; Justin
K.; (Portland, OR) ; Chau; Robert S.;
(Beaverton, OR) |
Correspondence
Address: |
TROP PRUNER & HU, PC
1616 S. VOSS ROAD, SUITE 750
HOUSTON
TX
77057-2631
US
|
Family ID: |
34981845 |
Appl. No.: |
11/418577 |
Filed: |
May 5, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10881055 |
Jun 30, 2004 |
7060568 |
|
|
11418577 |
May 5, 2006 |
|
|
|
Current U.S.
Class: |
257/392 ;
257/369; 257/391; 257/E21.635; 257/E21.639 |
Current CPC
Class: |
H01L 21/823857 20130101;
H01L 21/823828 20130101 |
Class at
Publication: |
257/392 ;
257/391; 257/369 |
International
Class: |
H01L 29/94 20060101
H01L029/94; H01L 29/76 20060101 H01L029/76 |
Claims
1. an integrated circuit comprising: a substrate; and an NMOS
transistor and a PMOS transistor, said NMOS and PMOS transistors
formed on said substrate, said NMOS transistor and said PMOS
transistor forming a complementary metal oxide semiconductor
structure, said NMOS transistor and said PMOS transistor having
different gate dielectrics, one of said transistors having a gate
dielectric with a dielectric constant greater than 10 and the other
of said transistors having a gate dielectric with a dielectric
constant of less than 10.
2. The circuit of claim 1 wherein said dielectrics have different
dielectric thicknesses.
3. The circuit of claim 1 wherein said dielectrics are formed of
different dielectric materials.
4. The circuit of claim 1 wherein said dielectrics are formed by
different techniques.
5. The circuit of claim 1 wherein said dielectrics are covered by
metal gate electrodes.
6. The circuit of claim 1 wherein said NMOS transistor has a gate
dielectric with a larger conduction band offset.
7. The circuit of claim 1 wherein said PMOS transistor has a gate
dielectric with a higher dielectric constant.
8. The circuit of claim 1 wherein the gate dielectric of said NMOS
transistor is thicker than the gate dielectric of said PMOS
transistor.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. patent
application Ser. No. 10/881,055, filed on Jun. 30, 2004.
BACKGROUND
[0002] This invention relates generally to semiconductor
technology, semiconductor processing, and the formation of
complementary metal oxide semiconductor integrated circuits.
[0003] Complementary metal oxide semiconductor integrated circuits
include NMOS transistors and PMOS transistors. Generally, these
transistors may be made by forming a gate dielectric and then
forming NMOS and PMOS gate structures on top of that dielectric.
The gate electrode structures may be made of polysilicon, silicide,
or metal.
[0004] A dummy gate electrode, such as a polysilicon gate
electrode, may also be formed over a gate dielectric. Then the
dummy gate electrode may be removed and replaced with a metal gate
electrode. In such a process, different metal gate electrodes may
be utilized for the NMOS and PMOS transistors, but a common
dielectric is utilized.
[0005] Thus, there is a need for complementary metal oxide
semiconductor fabrication techniques.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] FIG. 1 is an enlarged, partial, cross-sectional view of one
embodiment of the present invention at an early stage of
manufacture;
[0007] FIG. 2 is an enlarged, partial, cross-sectional view of the
embodiment shown in FIG. 1 at a subsequent stage of manufacture in
accordance with one embodiment of the present invention;
[0008] FIG. 3 is an enlarged, partial, cross-sectional view of the
embodiment shown in FIG. 2 at a subsequent stage of manufacture in
accordance with one embodiment of the present invention;
[0009] FIG. 4 is a partial, enlarged, cross-sectional view of the
embodiment shown in FIG. 3 at a subsequent stage of manufacture in
accordance with one embodiment of the present invention;
[0010] FIG. 5 is an enlarged, partial, cross-sectional view of the
embodiment shown in FIG. 4 at a subsequent stage of manufacture in
accordance with one embodiment of the present invention;
[0011] FIG. 6 is a partial, enlarged, cross-sectional view of the
embodiment shown in FIG. 5 at a subsequent stage of manufacture in
accordance with one embodiment of the present invention; and
[0012] FIG. 7 is a partial, enlarged, cross-sectional view of the
embodiment shown in FIG. 6 at a subsequent stage of manufacture in
accordance with one embodiment of the present invention.
DETAILED DESCRIPTION
[0013] Complementary metal oxide semiconductor (CMOS) integrated
circuits may be fabricated with NMOS and PMOS transistors having
different gate dielectrics. The dielectrics may be different in
terms of the materials used, their thicknesses, or the techniques
used to form the gate dielectrics, to mention a few examples. As a
result, the gate dielectric can be tailored to the particular type
of transistor, be it an NMOS or PMOS transistor, as the case may
be.
[0014] Referring to FIG. 1, in accordance with one embodiment of
the present invention, an initial semiconductor structure 10
includes a semiconductor substrate 12 having an insulator 14 formed
thereon with trenches filled by dummy gate materials 16 and 18. The
dummy gate materials 16 and 18, in one embodiment, may be doped
polysilicon, for example.
[0015] Referring to FIG. 2, the dummy gate material 16 has been
removed. The removal of the dummy gate material 16 may be
accomplished by masking, etch-out, or other methods. In an etch-out
process, the material 16 may be selectively etched relative to the
material 18. Thus, in one embodiment, the materials 16 and 18 may
be different materials such that one may be etched selectively
relative to the other. If an etchant, such as a wet etchant, is
utilized which preferentially attacks the material 16, the material
16 can be selectively etched while the material 18 remains.
[0016] For example, in accordance with one embodiment of the
present invention, the material 16 may be an N-doped polysilicon,
while the material 18 is a P-doped polysilicon. An etchant such as
tetramethylammonium hydroxide (TMAH) or NH.sub.40H, together with
sonication, may be utilized to selectively etch one of the
materials 16 or 18, while not significantly etching the other
material. Depending on the choice of wet etchant utilized to etch
the material 16 or 18, one of the dummy gate materials 16 and 18
can be etched while the other one is substantially unetched. Then
the other or remaining gate material 16 or 18 may be removed.
[0017] Referring to FIG. 3, in accordance with one embodiment of
the present invention, a dielectric 22 may be formed on the
substrate 12 in the opening 20 creating by the removal of the gate
material 16. In one embodiment, the dielectric 22 can be selected
to have characteristics to optimize the performance of either an
NMOS or PMOS transistor to be formed in the region 20. For example,
the gate dielectric 22 material, thickness or formation technique
may be tailored for its particular application.
[0018] For example, the NMOS transistor may use a larger conduction
band offset material, such as silicon dioxide, and the PMOS
transistor may use a material with a higher dielectric constant,
such as hafnium dioxide, which also happens to have good band
offset for holes. Higher dielectric constants may be greater than
ten in one embodiment. As another example, a thicker material may
be utilized for the NMOS than the PMOS transistors in some cases.
For example, hafnium dioxide leaks electrons more than holes, so a
thicker hafnium dioxide layer may be utilized on the NMOS
transistors and a thinner hafnium dioxide layer may be utilized on
the PMOS transistors. For example, in one embodiment, the hafnium
dioxide gate dielectric may be 30 Angstroms for the NMOS
transistors and 15 Angstroms for the gate dielectric for PMOS
transistors.
[0019] As still another example, the deposition techniques may be
different for the two gate dielectrics. For example, materials for
the NMOS transistor, such as silicon dioxide, may be deposited
using diffusion techniques, while atomic layer deposition,
sputtering, or metal organic chemical vapor deposition (MOCVD) may
be utilized to deposit high dielectric constant materials such as
hafnium dioxide.
[0020] One gate dielectric may be a high-k material (having a
dielectric constant greater than 10) and the other may be a low-k
material (having a dielectric constant less than 10).
Alternatively, both dielectrics may be high-k or both may be low-k
dielectrics.
[0021] The appropriate gate electrode material 24 may then be
deposited over the gate dielectric 22 in the opening 20 created by
the removal of the material 16.
[0022] Referring to FIG. 4, a gate electrode material 24 may be
deposited over the gate dielectric 22. The material 24 may be any
conductive material, including doped polysilicon or metal. The
material may be deposited using any suitable technique.
[0023] Referring to FIG. 5, the gate material 18 may be selectively
removed. The selective removal may again be accomplished using
selective etching, masking, or any other method to remove the
material 18, while leaving the material 24.
[0024] Then, as shown in FIG. 6, a gate dielectric 28 may be formed
in the opening 26 created by the removal of the material 18. Again,
the characteristics of the gate dielectric 28 may be optimized for
its particular application, be it for a PMOS or an NMOS transistor.
For example, its thickness, formation technique, or the material
utilized may be selected to optimize the performance of the
ultimate transistor.
[0025] In some embodiments of the present invention, it may be
desirable to ensure that the material 18 is selectively etchable
relative to the material 24. For example, selective etching may be
based on the fact that the materials 18 and 24 are of a different
material type.
[0026] Referring to FIG. 7, an appropriate gate electrode material
30 may then be formed in the opening 26 over the gate dielectric
28. In some embodiments, the gate materials 24 and 30 may be doped
polysilicon, may include silicide, or may be a metal.
[0027] In some embodiments, a single gate dielectric material may
not provide the highest performance for both NMOS and PMOS
structures. This may be due, for example, to poor band offset with
conduction or valence bonds, incompatibility to the gate electrode
material, incompatibility with gate electrode processing or
thickness requirements. By selecting the better candidate
dielectric film for each structure, and depositing the best film
with the optimal thickness, higher performance complementary metal
oxide semiconductor devices may be created in some embodiments. By
using better gate dielectric material of optimal thickness for each
electrode stack, higher performance structures may be created that
may exhibit higher mobility, higher saturation current, or better
threshold voltage in some embodiments.
[0028] While the present invention has been described with respect
to a limited number of embodiments, those skilled in the art will
appreciate numerous modifications and variations therefrom. It is
intended that the appended claims cover all such modifications and
variations as fall within the true spirit and scope of this present
invention.
* * * * *