U.S. patent application number 11/218355 was filed with the patent office on 2006-01-12 for methods for integrating replacement metal gate structures.
Invention is credited to Chris E. Barns, Justin K. Brask, Robert S. Chau, Mark L. Doczy, Scott A. Hareland, Jack Kavalieros, Matthew V. Metz.
Application Number | 20060008954 11/218355 |
Document ID | / |
Family ID | 34700884 |
Filed Date | 2006-01-12 |
United States Patent
Application |
20060008954 |
Kind Code |
A1 |
Kavalieros; Jack ; et
al. |
January 12, 2006 |
Methods for integrating replacement metal gate structures
Abstract
Methods and associated structures of forming a microelectronic
device are described. Those methods comprise providing a substrate
comprising a first transistor structure comprising an n-type gate
material and second transistor structure comprising a p-type gate
material, selectively removing the n-type gate material to form a
recess in the first gate structure, and then filling the recess
with an n-type metal gate material.
Inventors: |
Kavalieros; Jack; (Portland,
OR) ; Brask; Justin K.; (Portland, OR) ;
Doczy; Mark L.; (Beaverton, OR) ; Hareland; Scott
A.; (Lino Lakes, MN) ; Metz; Matthew V.;
(Hillsboro, OR) ; Barns; Chris E.; (Portland,
OR) ; Chau; Robert S.; (Beaverton, OR) |
Correspondence
Address: |
BLAKELY SOKOLOFF TAYLOR & ZAFMAN
12400 WILSHIRE BOULEVARD
SEVENTH FLOOR
LOS ANGELES
CA
90025-1030
US
|
Family ID: |
34700884 |
Appl. No.: |
11/218355 |
Filed: |
September 2, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10748383 |
Dec 29, 2003 |
|
|
|
11218355 |
Sep 2, 2005 |
|
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Current U.S.
Class: |
438/149 ;
257/E21.637; 257/E29.158 |
Current CPC
Class: |
H01L 29/517 20130101;
Y10S 438/926 20130101; H01L 29/66545 20130101; H01L 21/823842
20130101; H01L 29/495 20130101 |
Class at
Publication: |
438/149 |
International
Class: |
H01L 31/119 20060101
H01L031/119; H01L 31/113 20060101 H01L031/113; H01L 31/062 20060101
H01L031/062; H01L 29/94 20060101 H01L029/94; H01L 29/76 20060101
H01L029/76; H01L 21/84 20060101 H01L021/84; H01L 21/00 20060101
H01L021/00 |
Claims
1. A method comprising: providing a substrate comprising a first
transistor structure comprising an n-type gate material and second
transistor structure comprising an p-type gate material;
selectively removing the n-type gate material to form a recess in
the first gate structure; and filling the recess with an n-type
metal gate material.
2. The method of claim 1 wherein providing a substrate comprising a
first transistor structure comprising an n-type gate material and
second transistor structure comprising a p-type gate material
comprises providing a substrate comprising an NMOS transistor
structure comprising an n doped polysilicon gate material and a
PMOS transistor structure comprising a p doped polysilicon gate
material.
3. The method of claim 2 wherein providing a substrate comprising
an NMOS transistor structure comprising an n doped polysilicon gate
material and an PMOS transistor structure comprising a p doped
polysilicon gate material comprises providing a substrate
comprising an NMOS transistor structure comprising an n doped
polysilicon gate material and a PMOS transistor structure
comprising a p doped polysilicon gate, wherein the PMOS transistor
structure comprises source and drain regions comprising a silicon
germanium alloy.
4. The method of claim 1 wherein selectively removing the n-type
gate material comprises selectively removing the n-type gate
material by wet etching the n-type gate material with a mixture of
about 2 percent to about 30 percent ammonium hydroxide in deionized
water and applying a sonication from about 0.5 MHz to about 1.2
MHz.
5. The method of claim 4 wherein wet etching the n-type gate
material with a mixture of about 10 percent to about 20 percent
ammonium hydroxide in deionized water comprises wet etching the
n-type gate material with a mixture of about 10 percent to about 20
percent ammonium hydroxide in deionized water at a temperature from
about 10 degrees to about 40 degrees Celsius.
6. The method of claim 1 wherein selectively removing the n-type
gate material comprises wet etching the n-type gate material with a
mixture of about 15 percent to about 30 percent tetramethylammonium
hydroxide in deionized water and applying a sonication from about
0.8 MHz to about 1.2 MHz.
7. The method of claim 6 wherein wet etching the n-type gate
material with a mixture of about 15 percent to about 30 percent
tetramethylammonium hydroxide in deionized water comprises wet
etching the n-type gate material with a mixture of about 15 percent
to about 30 percent tetramethylammonium hydroxide in deionized
water at a temperature from about 60 degrees to about 90 degrees
Celsius.
8. The method of claim 1 wherein selectively removing the n-type
gate material comprises selectively removing the n-type gate
material and not substantially removing the p-type gate
material.
9. The method of claim 1 wherein selectively removing the n-type
gate material to form a recess in the first gate structure further
comprises selectively removing a first gate dielectric layer
disposed beneath the n-type gate material.
10. The method of claim 9 wherein selectively removing the first
gate dielectric layer disposed beneath the n-type gate material
further comprises forming a second gate dielectric layer within the
recess.
11. The method of claim 10 wherein forming the second gate
dielectric layer within the recess comprises forming a high k gate
dielectric layer within the recess.
12. The method of claim 10 wherein selectively removing a first
gate dielectric layer disposed beneath the n-type gate material
further comprises forming a high k gate dielectric layer selected
from the group consisting of hafnium oxide, zirconium oxide,
titanium oxide, and aluminum oxide and/or combinations thereof
within the recess.
13. The method of claim 1 wherein filling the recess with an n-type
metal gate material comprises filling the recess with a metal gate
material selected from the group consisting of hafnium, zirconium,
titanium, tantalum, and aluminum and/or combinations thereof.
14. A method of forming a microelectronic structure comprising;
providing a substrate comprising an n-type transistor structure
comprising an n-type polysilicon gate material and a p-type
transistor structure comprising a p-type polysilicon gate material,
wherein a first dielectric layer is disposed above the n-type and
the p-type gate structures; removing a portion of the first
dielectric layer so that the n-type polysilicon gate material is
exposed; selectively removing the n-type polysilicon gate material
to form a recess; and filling the recess with an n-type metal gate
material.
15. The method of claim 14 wherein filling the recess with an
n-type metal gate material further comprises forming a second
dielectric layer on the n-type metal gate material.
16. The method of claim 14 wherein selectively removing the n-type
polysilicon gate material comprises selectively removing the n-type
polysilicon gate material and not substantially removing the p-type
polysilicon gate material.
17. The method of claim 14 wherein selectively removing the n-type
polysilicon gate material comprises selectively removing the n-type
gate material by wet etching the n-type gate material with a
mixture of about 2 percent to about 30 percent ammonium hydroxide
in deionized water and applying a sonication from about 0.5 MHz to
about 1.2 MHz.
18. A structure comprising: a substrate comprising an n-type
transistor structure comprising an n-type metal gate material and a
p-type transistor structure comprising a p-type polysilicon gate
material.
19. The structure of claim 18 wherein the p-type transistor
structure further comprises a source and a drain region comprising
a silicon germanium alloy.
20. The structure of claim 18 wherein the n-type transistor
structure further comprises a high k gate dielectric layer selected
from the group consisting of hafnium oxide, zirconium oxide,
titanium oxide, and aluminum oxide and/or combinations thereof.
21. The structure of claim 18 wherein the n-type metal gate
material is selected from the group consisting of hafnium,
zirconium, titanium, tantalum and aluminum and/or combinations
thereof.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to the field of
microelectronic devices, and more particularly to methods of
fabricating metal gate transistors.
BACKGROUND OF THE INVENTION
[0002] Microelectronic devices are often manufactured in and on
silicon wafers and on other types other substrates. Such integrated
circuits may include millions of transistors, such as metal oxide
semiconductor (MOS) field effect transistors, as are well known in
the art. MOS transistors typically comprise source, drain and gate
regions, in which the gate material may typically comprise
polysilicon. Polysilicon gates, however, can be susceptible to
depletion effects, wherein an electric field applied to a
polysilicon gate sweeps away carriers (holes in a p-type doped
polysilicon, or electrons in an n-type doped polysilicon) so as to
create a depletion of carriers in the area of the polysilicon gate
near an underlying gate dielectric of the transistor. The depletion
effect can add to the overall gate dielectric thickness in the MOS
device. Recently, silicon germanium source and drain regions have
been incorporated within transistors utilizing polysilicon gates,
which greatly improves the performance of such transistors since
the strained lattice of the silicon germanium regions enhance the
electron and hole mobility within the channel of such a transistor,
as is well known in the art.
[0003] Metal gates, on the other hand, are not as susceptible to
depletion effects as gates comprising polysilicon. Typical prior
art microelectronic processes, however, do not incorporate both
metal gates and polysilicon gates within the same device or
integrated circuit. This is due, in part, to the complexity and
cost of developing a microelectronic process that can reliably form
both a metal gate structure and a polysilicon gate structure within
the same microelectronic device or integrated circuit. It would
therefore be advantageous to incorporate both a metal gate
structure and a polysilicon gate structure with silicon germanium
source and drain regions. The methods and structures of the present
invention provide such a process.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] While the specification concludes with claims particularly
pointing out and distinctly claiming that which is regarded as the
present invention, the advantages of this invention can be more
readily ascertained from the following description of the invention
when read in conjunction with the accompanying drawings in
which:
[0005] FIGS. 1a-1e represent structures according to an embodiment
of the present invention.
[0006] FIGS. 2a-2e represent structures according to an embodiment
of the present invention.
DETAILED DESCRIPTION OF THE PRESENT INVENTION
[0007] In the following detailed description, reference is made to
the accompanying drawings that show, by way of illustration,
specific embodiments in which the invention may be practiced. These
embodiments are described in sufficient detail to enable those
skilled in the art to practice the invention. It is to be
understood that the various embodiments of the invention, although
different, are not necessarily mutually exclusive. For example, a
particular feature, structure, or characteristic described herein,
in connection with one embodiment, may be implemented within other
embodiments without departing from the spirit and scope of the
invention. In addition, it is to be understood that the location or
arrangement of individual elements within each disclosed embodiment
may be modified without departing from the spirit and scope of the
invention. The following detailed description is, therefore, not to
be taken in a limiting sense, and the scope of the present
invention is defined only by the appended claims, appropriately
interpreted, along with the full range of equivalents to which the
claims are entitled. In the drawings, like numerals refer to the
same or similar functionality throughout the several views.
[0008] Methods and associated structures of forming a
microelectronic structure are described. Those methods comprise
providing a substrate comprising a first gate transistor comprising
an n-type gate material and second gate transistor comprising a
p-type gate material, selectively removing the n-type gate material
to form a recess in the first transistor structure, and then
filling the recess with an n-type metal gate material. The methods
of the present invention enable the incorporation of NMOS metal
gate transistors with PMOS polysilicon transistors utilizing
silicon germanium source and drain regions, within the same
microelectronic device.
[0009] FIGS. 1a-1e illustrate an embodiment of a method and
associated structures of incorporation of NMOS metal gate
transistors with PMOS polysilicon transistors. FIG. 1a illustrates
a cross-section of a portion of a substrate 100 that may preferably
comprise a silicon substrate 100. The silicon substrate 102 may be
comprised of materials such as, but not limited to, silicon,
silicon-on-insulator, germanium, indium antimonide, lead telluride,
indium arsenide, indium phosphide, gallium arsenide, gallium
antimonide, or combinations thereof.
[0010] The substrate 100 may comprise a first transistor structure
102 that is preferably an n-type transistor structure 102 (i.e., an
NMOS transistor), as is well known in the art. The substrate 100
may also comprise a second transistor structure 104 that is
preferably a p-type transistor structure 104 (i.e., a PMOS
transistor), as is well known in the art. The n-type transistor
structure 102 may comprise a gate dielectric layer 106, a source
region 112, a drain region 114, and a spacer 110, as are well known
in the art. The n-type transistor structure 102 may further
comprise an n-type gate material 108, that is preferably a
polysilicon gate material 108, and that is disposed on the gate
dielectric layer 106. The n-type gate material 108 may preferably
be doped with an n-type dopant, such as phosphorus, for
example.
[0011] The p-type transistor structure 104 may comprise a p
transistor gate dielectric layer 116, a source region 122, a drain
region 124, and a spacer 120, as are well known in the art. The
source region 122 and the drain region 124 may preferably comprise
a silicon germanium alloy material. The p-type transistor structure
104 may further comprise a p-type gate material 118, that is
preferably a p-type polysilicon gate material 118, and that is
disposed on the p transistor gate dielectric layer 116. The p-type
gate material 118 may preferably be doped with a p-type dopant,
such as boron, for example.
[0012] A dielectric layer 126 may be disposed above and on the
n-type and the p-type gate structures, and may comprise an
inter-layer dielectric (ILD) as is well known in the art. A portion
128 of the dielectric layer 126 may be removed, by preferably
utilizing a chemical mechanical process (CMP), for example, to
expose the p-type gate material 118 and the n-type gate material
108 (see FIG. 1b).
[0013] After the p-type gate material 118 and the n-type gate
material 108 are exposed, the n-type gate material may be
selectively removed from the n-type transistor structure 102 to
form a recess 130 (FIG. 1c). The n-type gate material 108 may be
selectively removed by utilizing a wet etch, that preferably
comprises an ammonium hydroxide etch. In one embodiment, the
ammonium hydroxide etch may comprise about 2 percent to about 30
percent ammonium hydroxide in deionized water, and sonication, as
is known in the art, may be applied to the mixture with a power
that may range from about 0.5 MHz to about 1.2 MHz. The temperature
of the wet etch may preferably range from about 10 degrees to about
40 degrees Celsius.
[0014] In another embodiment, the wet etch may comprise a mixture
of about 15 percent to about 30 percent tetramethylammonium
hydroxide (TMAH) in deionized water, with an applied a sonication
from about 0.5 MHz to about 1.2 MHz, and a temperature from about
60 degrees to about 90 degrees Celsius. The particular parameters
of the removal process may depend upon the particular application,
but any such removal process that is highly selective to the n-type
gate material 108, that is, which substantially removes the n-type
gate material 108 while leaving the p-type material 118
substantially intact, may be utilized. Alternatively, but much less
desirable since it involves an additional lithography step, the
p-type devices could be masked off to expose only the n-type
devices, eliminating the need for etch selectivity between the two
types of devices.
[0015] The recess 130 may be filled with an n-type metal gate
material 132, such as hafnium, zirconium, titanium, tantalum, or
aluminum, or combinations thereof, for example (see FIG. 1d). The
recess 130 may be filled using PVD ("Physical vapor deposition"),
CVD ("Chemical vapor deposition"), or ALD ("Atomic Layer
deposition") as are known in the art. In this manner, the n-type
polysilicon gate material 108 may be replaced with the n-type metal
gate material 132, which greatly enhances the performance of an
n-type transistor fabricated according to the methods of the
present invention. The methods of the present invention also enable
the integration of an n-type (NMOS) metal gate transistor with a
p-type polysilicon transistor (PMOS), which may preferably comprise
silicon germanium source and drain regions, within the same
device.
[0016] Referring to FIG. 1e, after the recess 130 has been filled
with the n-type metal material 132, a second dielectric layer 134
may be formed on the n-type metal gate material 132 and on the
p-type gate material 118 (i.e., the ILD layer may be recapped).
[0017] In another embodiment (see FIG. 2a), a substrate 200,
(similar to the substrate 100 of FIG. 1) may comprise a first
transistor structure 202, that is preferably an n-type transistor
structure 202, and a second transistor structure 204 that is
preferably a p-type transistor structure 204. The n-type transistor
structure 202 may comprise a first gate dielectric layer 206, a
source region 212, a drain region 214, and a spacer 210. The n-type
transistor structure 202 may further comprise a recess 230, similar
to the recess 130 of FIG. 1c.
[0018] The p-type transistor structure 204 may comprise a p
transistor gate dielectric layer 216, a source region 222, a drain
region 224, and a spacer 220. The source region 222 and the drain
region 224 may preferably comprise a silicon germanium alloy
material. The p-type transistor structure 204 may further comprise
a p-type gate material 218, that is preferably a p-type polysilicon
gate material 218, and that is disposed on the p transistor gate
dielectric layer 216.
[0019] The first gate dielectric layer 206 of the n-type transistor
structure 202 may be removed by using techniques well known in the
art, such as a wet chemical etch (see FIG. 2b). Then, a second gate
dielectric layer 207 may be formed (using conventional methods
known in the art) in the recess 230 of the n-type transistor
structure 202 (FIG. 2c). The second gate dielectric layer 207 may
preferably comprise a high k gate dielectric layer, and may
comprise material such as, for example, hafnium oxide, zirconium
oxide, titanium oxide, and aluminum oxide and/or combinations
thereof. The use of a high k second gate dielectric layer 207 may
enhance the performance of the n-type transistor structure 202 by
reducing the gate leakage current of devices so fabricated, as is
well known in the art.
[0020] Referring to FIG. 2d, the recess 230 may then be filled with
an n-type metal material 232 (similar to the n-type metal gate
material 132 of FIG. 1d), and a second dielectric layer 234
(similar to the second dielectric layer 134 of FIG. 1e) may be
formed on the n-type metal gate material 232 and on the p-type gate
material 218 (see FIG. 2e).
[0021] Thus, the current embodiment of the present invention
enables the use of a p-type polysilicon gate material with an n-ype
metal gate material that comprises a high k dielectric gate
layer.
[0022] As described above, the present invention provides methods
and associated structures of providing a substrate comprising a
first transistor structure comprising an n-type gate material and
second transistor structure comprising an p-type gate material,
selectively removing the n-type gate material to form a recess in
the first transistor structure, and then filling the recess with an
n-type metal gate material. The methods of the present invention
enable the replacement of a p-type polysilicon gate material with
an n-type metal gate material, which greatly enhances the
performance of an n-type transistor fabricated according to the
methods of the present invention. The methods of the present
invention also enable the integration of an n-type metal gate
transistor with a p-type polysilicon transistor, which may
preferably comprise silicon germanium source and drain regions,
within the same device.
[0023] Although the foregoing description has specified certain
steps and materials that may be used in the method of the present
invention, those skilled in the art will appreciate that many
modifications and substitutions may be made. Accordingly, it is
intended that all such modifications, alterations, substitutions
and additions be considered to fall within the spirit and scope of
the invention as defined by the appended claims. In addition, it is
appreciated that a microelectronic device, such as a transistor is
well known in the art. Therefore, it is appreciated that the
Figures provided herein illustrate only portions of an exemplary
microelectronic device that pertains to the practice of the present
invention. Thus the present invention is not limited to the
structures described herein.
* * * * *