U.S. patent application number 09/569306 was filed with the patent office on 2002-03-14 for self-aligned silicone process for low resistivity contacts to thin film silicon-on-insulator mosfets.
Invention is credited to Cabral, Cyril JR., Chan, Kevin Kok, Cohen, Guy Moshe, Lavoie, Christian, Roy, Ronnen Andrew, Solomon, Paul Michael.
Application Number | 20020031909 09/569306 |
Document ID | / |
Family ID | 24274883 |
Filed Date | 2002-03-14 |
United States Patent
Application |
20020031909 |
Kind Code |
A1 |
Cabral, Cyril JR. ; et
al. |
March 14, 2002 |
Self-aligned silicone process for low resistivity contacts to thin
film silicon-on-insulator mosfets
Abstract
A silicide processing method for a thin film SOI device
including depositing a metal or an alloy on a gate and a
source/drain structure formed in a silicon-on-insulator film,
reacting the metal or alloy at a first temperature with the
silicon-on-insulator film to form a first alloy, etching the
unreacted layer of the metal (or alloy) selectively, depositing a
Si film on the first alloy, reacting the Si film at a second
temperature to form a second alloy, and etching the unreacted layer
of the Si film selectively.
Inventors: |
Cabral, Cyril JR.;
(Ossining, NY) ; Chan, Kevin Kok; (Staten Island,
NY) ; Cohen, Guy Moshe; (Mohegan Lake, NY) ;
Lavoie, Christian; (Ossining, NY) ; Roy, Ronnen
Andrew; (Ossining, NY) ; Solomon, Paul Michael;
(Yorktown Heights, NY) |
Correspondence
Address: |
McGinn & Gibb
8321 Old Courthouse Road
Suite 200
Vienna
VA
22182-3817
US
|
Family ID: |
24274883 |
Appl. No.: |
09/569306 |
Filed: |
May 11, 2000 |
Current U.S.
Class: |
438/655 ;
257/E21.165; 257/E21.415; 257/E21.438; 257/E29.147;
257/E29.151 |
Current CPC
Class: |
H01L 29/665 20130101;
H01L 21/28518 20130101; H01L 29/458 20130101; H01L 29/78 20130101;
H01L 29/4908 20130101; H01L 29/66772 20130101 |
Class at
Publication: |
438/655 |
International
Class: |
H01L 021/44 |
Goverment Interests
[0001] The subject matter of the present Application was at least
partially funded under the Grant No. N66001-97-1-8908 from the U.S.
Defense Advanced Research Projects Agency (DARPA).
Claims
What is claimed is:
1. A method for fabricating a silicide for a semiconductor device,
said method comprising: depositing a buried oxide layer on a
substrate; applying a silicon layer to said buried oxide layer;
forming a source and drain in said silicon layer; forming a gate on
said layer of silicon; and depositing a metal or an alloy on said
gate and said source and drain, to form said silicide for said
semiconductor device.
2. The method, as claimed in claim 1, further comprising: reacting
said metal or said alloy with said silicon to form a first alloy at
said gate and said source/drain structure.
3. The method, as claimed in claim 1, wherein said semiconductor
device comprises a metal oxide semiconductor field-effect
transistor (MOSFET) device.
4. The method, as claimed in claim 1, wherein said metal is
selected from one of a group consisting of cobalt, titanium,
nickel, platinum, Pt.sub.x Si.sub.1-x alloy, palladium, Pd.sub.x
Si.sub.1-x alloy, and Co.sub.x Si.sub.1-x alloy.
5. The method, as claimed in claim 2, wherein said reacting is
performed at a first temperature.
6. The method, as claimed in claim 2, wherein said reacting is
performed within a range of a first predetermined lower temperature
to a second predetermined higher temperature.
7. The method, as claimed in claim 6, wherein said reacting is
performed at a third temperature, said third temperature being
intermediate said first and second temperatures.
8. The method, as claimed in claim 2, wherein said first alloy is
an alloy selected from the group consisting of Co.sub.2 Si and Co
Si.
9. The method, as claimed in claim 2, wherein said first alloy is
formed under an unreacted layer of said metal or said alloy.
10. The method, as claimed in claim 9, further comprising: etching
said unreacted layer of said metal or said alloy selectively;
depositing a Si film on said first alloy; and reacting said Si film
to form a second alloy.
11. The method, as claimed in claim 10, wherein said film is a film
selected from the group consisting of a single crystal Si film and
a polysilicon film.
12. The method, as claimed in claim 10, wherein said reacting said
Si film is performed at a second temperature.
13. The method, as claimed in claim 10, wherein said second alloy
is formed under an unreacted layer of said Si film.
14. The method, as claimed in claim 13, wherein said second alloy
is CoSi.sub.2.
15. The method, as claimed in claim 13, further comprising: etching
said unreacted layer of said Si film selectively.
16. A silicide processing method for a thin film
silicon-on-insulator (SOI) device, said method comprising:
depositing a metal or an alloy on a gate and a source and drain
formed in a silicon-on-insulator (SOI) film; reacting said metal or
said alloy at a first temperature with said SOI film to form a
first alloy; selectively etching said unreacted layer of said metal
or said alloy; depositing a Si film on said first alloy; and
reacting said Si film at a second temperature to form a second
alloy.
17. The method, as claimed in claim 16, wherein said reacting of
said Si film at said second temperature reduces consumption of said
silicon-on-insulator film by at least a factor of two.
18. The method, as claimed in claim 16, further comprising
selectively etching said unreacted layer of said metal or said
alloy.
19. The method, as claimed in claim 16, wherein said second
temperature is greater than said first temperature.
20. The method as claimed in claim 16, further comprising
selectively etching said unreacted layer of said Si film.
21. The method, as claimed in claim 16, wherein said metal is
selected from one of a group consisting of cobalt, titanium,
nickel, platinum, Pt.sub.x Si.sub.1-x alloy, palladium, Pd.sub.x
Si.sub.1-x alloy, and Co.sub.x Si.sub.1-x alloy.
22. The method, as claimed in claim 16, wherein said reacting is
performed within a range of a first predetermined lower temperature
to a second predetermined higher temperature.
23. The method, as claimed in claim 16, wherein said first alloy is
an alloy selected from the group consisting of Co.sub.2Si and
CoSi.
24. The method, as claimed in claim 16, wherein said film is a film
selected from the group consisting of a single crystal Si film and
a polysilicon film.
25. The method, as claimed in claim 16, wherein said second alloy
is CoSi.sub.2.
Description
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention generally relates to
silicon-on-insulator (SOI) MOSFETs and specifically, a self-aligned
silicide (salicide) process for thin film SOI MOSFETs having low
resistivity contacts.
[0004] 2. Description of the Related Art
[0005] Conventionally, a reduction of a short channel effect in a
silicon-on-insulator (SOI) MOSFET has been addressed by using
ultra-thin silicon films (e.g., having a thickness substantially
within a range of about 50 nm to about 3 nm). However, using an
ultra-thin SOI film can result in high source/drain series
resistance. A portion of the high source/drain series resistance
can be reduced by using a self-aligned silicide (salicide) contact
(e.g., for a discussion of salicides, see Lisa T. Su et al.,
"Optimization of the series resistance in sub--0.2 .mu.m SOI
MOSFET's", Electron Device Letters, 15(9), p. 363, September
1994).
[0006] The conventional salicide process has been limited to bulk
or thick SOI films (e.g., for purposes of the invention, a "bulk"
or "thick" SOI film is thicker than 100 nm). Reduction of a SOI
film thickness to an estimated 10 nm precludes the use of
conventional salicide. That is, if the amount of silicon consumed
by the formation of the silicide alloy becomes a large portion of
the initial SOI film thickness, then the contact area will
decrease, leading to an increase in the contact resistance.
Further, even if a conventional salicide was used with thin films,
there is no guarantee of low parasitic resistance because an
ultra-thin silicon film may be completely consumed during the
silicide formation. Further, the conventional salicide process can
form a metal-rich silicide which is characterized by higher
resistance.
[0007] In the case of a thin SOI film, the percentage of the SOI
consumed by the silicide considerably affects the series
resistance. It has been demonstrated that when 80% or more of the
SOI layer is consumed, the series resistance begins to increase as
a result of a reduction in the contact area (e.g., see Su et al.,
supra).
[0008] Alternatively, if the silicide layer is made extremely thin
(e.g., less than 30 nm) to avoid consuming the thin SOI film, then
the silicide layer loses its efficiency in reducing the series
resistance. For example, if the silicide is in the thick regime,
then a reduction of the silicide thickness would roughly yield a
proportional increase in the series resistance. This linear
behavior would hold down to about 20 nm (depending on the silicide
metal). A thinner silicide film may exhibit nucleation problems and
some of the phases may not form. All of this would lead to a very
steep increase in the contact resistance.
[0009] The series parasitic resistance must be minimized in order
to facilitate the fabrication of high performance thin film SOI
MOSFETs. The conventional salicide process is not applicable to the
production of ultra-thin SOI MOSFETs, and therefore a new salicide
process is required to overcome the problems of the conventional
method.
[0010] Further, the conventional method and structures are
deficient in their silicide/SOI interface roughness.
SUMMARY OF THE INVENTION
[0011] In view of the foregoing and other problems of the
conventional methods and structures, an object of the present
invention is to provide a new salicide process applicable to the
production of ultra-thin SOI MOSFETs (e.g., having a thickness
substantially within a range of about 3 nm to about 100 nm).
[0012] It is a further object to provide a new salicide process in
which less of the thin SOI film is consumed, produces a thicker SOI
film in a source/drain region, and is a self-aligned process.
[0013] Additionally, a further object of the invention is to stay
within the thermal budget allowed for the production of
conventional MOSFETs using the conventional salicide process. The
thermal budget consists of both the temperature and the time length
at which the wafer was held at a given temperature. Typically, to
minimize the thermal budget the wafer is annealed by rapid thermal
annealing (RTA) to form the silicide alloy. For example, to form
the CoSi.sub.2 phase from the CoSi phase the wafer is annealed at
about 750.degree. C. for 60 seconds.
[0014] In a first aspect of the invention, a method for fabricating
a semiconductor device, includes depositing a buried oxide layer on
a substrate, applying a silicon layer to the buried oxide layer,
forming a source and drain in the silicon layer, forming a gate on
the layer of silicon, and depositing a metal on the gate and the
source and drain, to form the silicide for the semiconductor
device.
[0015] In a second aspect of the present invention, a silicide
processing method for a thin film silicon-on-insulator (SOI)
device, includes depositing a metal on a gate and a source and
drain formed in a silicon-on-insulator (SOI) film, reacting the
metal at a first temperature with the SOI film to form a first
alloy, selectively etching the unreacted layer of the metal,
depositing a Si film on the first alloy, reacting the Si film at a
second temperature to form a second alloy, and selectively etching
the unreacted layer of the Si film.
[0016] In the method of the present invention, preferably a
thin-film of cobalt (Co) is deposited on a substrate and is reacted
with silicon (Si) at a low temperature to form an alloy of
Co.sub.2Si (e.g., having a metal-rich phase). The Co which is not
reacted is removed by selective etching.
[0017] This step is similar to the etching step in the conventional
salicide processing, but in the conventional process, a higher
temperature anneal is used so the etching is usually performed at
the CoSi formation stage. After the etching step, a non-crystalline
film of Si or poly-Si is deposited and subsequently annealed to
form the alloy (CoSi.sub.2) followed by selective etching of the
un-reacted silicon.
[0018] In this manner, a reaction of Co to initially form
Co.sub.2Si, minimizes the silicon consumption of the thin SOI film.
The consumption of the thin SOI film is additionally reduced by the
deposition of a silicon or poly-silicon film on the Co.sub.2Si.
[0019] The present invention extends the use of a salicide-like
process to thin SOI films, which are expected to be used in future
SOI MOSFETs. Such thin-film SOI films will be advantageous in
making the devices smaller, reducing the source/drain to substrate
overlap capacitance, and eliminating the floating body voltage.
[0020] Further, the invention provides a superior solution to the
alternative method(s) which include a raised source/drain by
epitaxy.
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The foregoing and other objects, aspects and advantages will
be better understood from the following detailed description of a
preferred embodiment of the invention with reference to the
drawings, in which:
[0022] FIGS. 1-6 illustrate a self-aligned method for forming low
resistivity contacts to thin film SOI MOSFETs, and more
specifically:
[0023] FIG. 1 shows a conventional MOSFET device to be
silicided;
[0024] FIG. 2 shows a thin film of metal (e.g., Co) deposited on
the device of FIG. 1;
[0025] FIG. 3 shows the formation of an alloy including the cobalt
after exposure to a low-temperature processing;
[0026] FIG. 4 shows an amorphous Si film deposition on the
alloy;
[0027] FIG. 5 shows the device after an annealing step at high
temperature; and
[0028] FIG. 6 shows the device after un-reacted silicon has been
removed by selective etching.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION
[0029] Referring now to the drawings, and more particularly to
FIGS. 1-6, there is shown a preferred embodiment of the method of
making of a self-aligned silicide which is applicable to the
standard MOSFET structure, and also to non-conventional MOSFETs and
structures according to the present invention.
[0030] Referring now to FIG. 1, a conventional MOSFET structure 100
is shown having a substrate 1 formed of silicon, a buried oxide
layer 2 (e.g., silicon oxide layer), an SOI layer 3 which thickness
noted by t.sub.si, a gate dielectric 6A (e.g., SiO.sub.2), sidewall
spacers 6B formed of nitride or oxide, a gate 7 (e.g. doped
poly-Si, or metal), and a source 4 and a drain 5 maid into the SOI
film 3, typically by an implant.
[0031] The inventive method is directed to making a self-aligned
silicide which is applicable to the standard MOSFET structure, and
also to non-conventional MOSFETs and structures. For ease of
discussion, the present invention will be applied to the
conventional MOSFET of FIG. 1.
[0032] However, although the process flow is demonstrated using a
conventional MOSFET structure, it is applicable to a wide variety
of structures. Metals, other than Co, that are used for silicides
(e.g., Ti, Ni, Pd, Pt and alloys thereof) can be used with the
present invention.
[0033] Referring to FIG. 2, a metal 20 (e.g., Co, Ni, Ti, Pd, Pt or
alloys thereof) is deposited in a thickness within a range of about
7 nm, and is reacted with silicon in the source 4, drain 5, and
gate 7 regions at a low temperature T.sub.1. It is noted that if
the temperature is too low, no reaction will take place. On the
other hand, if the temperature is too high, then the silicide phase
of CoSi will be formed. Since the temperature window over which the
metal-rich phase Co.sub.2Si is formed is narrow, it is difficult to
achieve only this phase during the first anneal. To extend the
temperature window, a mixture of 80% Co and 20% Si may be deposited
(e.g., by co-sputtering or evaporation from a Si.sub.0.2Co.sub.0.8
target). The temperature window for the formation of the Co.sub.2Si
out of the Si.sub.0.2Co.sub.0.8 mixture is about 337.degree. C. to
about 487.degree. C. The use of a 80% Si and 20% Co to extend the
temperature window is described in U.S. patent application Ser. No.
______, Cyril Carbal et. al, "Method for self-aligned formation of
silicide contacts using metal silicon alloys for limited silicon
consumption and for reduction of bridging", filed on ______, having
IBM Docket No. YOR900-0044, incorporated herein by reference.
[0034] As shown in FIG. 3, the alloy Co.sub.2Si 30 is formed, as a
result of applying the low temperature (e.g., T.sub.1) in the
anneal process to the structure of FIG. 2. (The thickness depends
on the initial Co film thickness. One angstrom of Co yields 1.47
angstroms of Co.sub.2Si. The typical Co film thickness is about 7
nm. Using the conversion ratio stated above, a 10.3 nm thick film
of Co.sub.2Si will be obtained after the first anneal.) An upper
layer of the cobalt 20 (e.g., over the alloy Co.sub.2Si 30) is
unreacted Co 20.
[0035] That is, in the standard process, all of the Co which is
deposited over a Si surface will react with the silicon surface and
will form a silicide. On the other hand, the Co that was deposited
over dielectric surfaces such as the oxide or nitride sidewalls
cannot react with the Si surface and will remain as unreacted Co.
FIG. 3 demonstrates a case in which some Co is left unreacted on
top of the silicide. As described above, this is not desirable in a
manufacturing process. Yet, even if this does happen, the overall
process of the invention will not be affected except that the
silicide film will be thinner than targeted. As such, the
robustness of the process is clearly demonstrated. It is noted that
in most cases, there will be no unreacted Co.
[0036] For example, the unreacted cobalt 20 has a thickness
dependent on the anneal time/temperature, and is removed through
selective etching. That is, a too short anneal may leave some of
the Co unreacted. If the temperature is too low, then the Co will
not react with the SOI film. This step is similar to the etching
step in the conventional salicide process with the exception that
in the conventional salicide process the un-reacted Co is etched at
the stage where CoSi is formed. It is noted that the deposition of
the a-Si may be carried out over the CoSi phase. However, by
forming the CoSi phase, much more of the Si in the SOI layer will
be consumed. An example of a selective etching solution is 10:1
H.sub.2O.sub.2:H.sub.2SO.sub.4 at 65.degree. C.
[0037] Next, referring to FIG. 4, an amorphous Si (a-Si) or a
poly-Si film 40 is deposited over the alloy Co.sub.2Si 30. The a-Si
film thickness depend on the initial Co film thickness. One unit of
Co would require 0.91 units of Si to form Co.sub.2Si, 1.82 units of
Si to form CoSi and 3.64 units of Si to form CoSi.sub.2. For
example, suppose the process starts with a 7 nm Co film which are
then reacted with the SOI film to form 10.3 nm film of Co.sub.2Si.
Assuming that all the Co will diffuse into the top deposited a-Si,
then it requires the a-Si film to be about 19 nm thick. A more
realistic assumption is that more than half but not all the Co will
diffuse into the top film, so that a thinner film is actually
needed. The amorphous silicon or polysilicon film 40 is annealed at
a high temperature T.sub.2, (e.g., T.sub.2>T.sub.1). The
temperature window for the formation of CoSi is about 481.degree.
C. to about 625.degree. C. (at about 625.degree. C., CoSi.sub.2
will start to form). Typical annealing temperature (T2) for the
second anneal is about 750.degree. C. These temperatures may vary
slightly depending on the doping species and concentration that
were implanted into the SOI film.
[0038] Hereinbelow, the amount of required Si in angstroms per
angstroms of metal is described. Forming 1 angstrom of Co.sub.2Si
will take 0.91 angstrom of Si, CoSi will take 1.82 angstroms of Si,
and CoSi.sub.2 will take 3.64 angstrom of Si. If the a-Si layer is
deposited on top of the Co.sub.2Si film, then the Si consumption
may be reduced by at least a half, since the Co.sub.2Si film would
be reacting on both top and bottom interfaces.
[0039] It is important to clean the top surface of the Co.sub.2Si
and remove any native oxide before the a-Si film deposition. The
existence of such an oxide at the interface may prevent the
Co.sub.2Si to react with the deposited a-Si layer. The cleaning of
the surface and the stripping of a native oxide may be achieved by
Ar (argon) sputtering in the a-Si deposition chamber or by a short
dip in a diluted HF acid.
[0040] As shown in FIG. 5, as a result of the annealing operation
at a high temperature T.sub.2, a layer of CoSi.sub.2 50 is formed
under an unreacted layer/portion 40A of the amorphous silicon or
polysilicon film 40. The thickness of the layer of un-reacted
amorphous silicon/polysilicon layer 40A depends on the initial
thickness of the top a-Si layer 40. It is desirable that all of the
Co.sub.2Si is transformed into CoSi.sub.2, without consuming the
entire a-Si layer. The unreacted layer/portion 40A results from the
supply of Si from the a-Si exceeding that which is needed to form
CoSi.sub.2. In other words, the a-Si layer was too thick.
[0041] FIG. 6 illustrates the selective etching of the layer of
un-reacted a-Si or poly-Si film 40 in a last phase.
[0042] Thus, with the invention, the reacting of the metal (e.g.,
cobalt) in an annealing operation to initially form the alloy
Co.sub.2Si 30 minimizes the silicon consumption of the SOI film
3.
[0043] Additionally, the deposit of the amorphous silicon or the
polysilicon film 40 on top of the alloy Co.sub.2Si 30 further
reduces consumption of the SOI film 3 by a factor of two since at
least half of the Co contained in the Co.sub.2Si 30 will diffuse
into the top amorphous silicon/polysilicon film layer 40 at the
high temperature anneal which forms the CoSi.sub.2.
[0044] The diffusivity of cobalt in polysilicon may be larger than
in single crystal (mono-crystal) silicon. Due to this diffusivity
difference between polysilicon and single crystal silicon, the high
temperature anneal will consume more of the top polysilicon layer
than that of the bottom single crystal SOI film.
[0045] In an alternative embodiment, the invention can be modified
so that the first anneal is at an intermediate temperature, T.sub.3
(e.g., T.sub.3 is about 550.degree. C.), where CoSi is formed
(T.sub.1<T.sub.3<T.sub.2). The anneal process at this
temperature will consume more of the SOI film than a Co.sub.2Si
formation. However, it may provide a larger temperature window for
the anneal.
[0046] The larger the temperature window, the easier it is to form
a given silicide phase without the risk of obtaining a mix phase.
The temperature window for Co.sub.2Si is about 20.degree. C. wide
if pure Co is used. It may be widened to about 100.degree. C. by
using Co.sub.0.8Si.sub.0.2. The window may shift and vary depending
on the SOI doping. This makes it difficult to obtain the Co.sub.2Si
phase if the window is narrow. If pure Co rather than
Co.sub.0.8Si.sub.0.2 is used, then it is easier to form CoSi due to
its large temperature window of about 150.degree. C.
[0047] Also, the etch selectivity of CoSi, with respect to Co, is
higher than that of Co.sub.2Si with respect to Co. The advantages
of this selectivity include better reliability and precision of the
resulting product. After the Co is reacted to form CoSi, the
unreacted Co must be etched away. Otherwise, the source/drain
regions will be shortened to the gate. The etchant should be
selective to CoSi. That is, it should only remove the Co and leave
the CoSi alloy intact. The etching selectivity is typically higher
if the alloy contains less Co and more Si. Thus, CoSi is expected
to be more resistant to the etch of Co than Co.sub.2Si. The
remainder of the steps in the process are the same.
[0048] Thus, the present invention is optimized over the
conventional techniques. That is, alternative conventional
methodologies (e.g., which are less desirable when contrasted to
the embodiments of the invention described above), include
thickening a SOI layer (by at least the amount that will be
consumed by the silicide in source and drain regions by using
selective epitaxial growth of silicon on these regions, fabricating
different silicide thicknesses over gate, source and drain regions
by laser melting, and the deposit of a silicon alloy
(Co.sub.1-xSi.sub.x, where x<0.2) to limit the amount of silicon
consumed at source, drain, and gates during silicide formation.
[0049] As mentioned above, the epitaxial growth of Si is performed
by thickening a SOI layer in the source/drain regions through
selective epitaxial growth of Si in these regions. This alternative
has several disadvantages when compared to the process of the
present invention.
[0050] First, the epitaxial growth has to be selective, otherwise
Si growth will take place on the sidewalls of the device. This
condition can lead to shorting the gate to the source and the
drain. To avoid this problem, the choice of the sidewall material
to use is narrowed because only growth-resistant materials can be
selected.
[0051] Further, the growth temperature is an important parameter in
determining the selectivity of the growth. The Si epitaxial growth
loses selectivity at low growth temperatures. "Low growth
temperatures" depend on the growth technique, and the sillicon
source. The most selective source is SiCl.sub.4, but it also
requires the highest deposition temperature (about 900.degree. C.
to 1200.degree. C.). Silane (SiH.sub.4) can be used for low
temperature deposition (as low as about 650.degree. C.), but it
exhibits very little selectivity, if any. Therefore, a sufficiently
high growth temperature (e.g., about 900.degree. C.) is required to
guarantee selectivity. The required high growth temperature may be
in excess of the thermal budget incurred in the conventional
salicide process.
[0052] A further problem with producing a raised source/drain by
epitaxial growth of silicon is the process robustness. Silicon
epitaxy is very sensitive to surface preparation and cleaning.
Different surface treatments can lead to different defects in the
film. Oxide residuals (e.g., even an atomic monolayer) can prevent
epitaxial growth.
[0053] Another problem with the epitaxial growth approach, known as
growth rate dependency on feature size, can occur. In a chemical
vapor deposition (CVD)-type epitaxy, the growth rate may be
dependent on the topography, the dimensions of the growth area, and
the ratio between the growth to non-growth areas. This may lead to
a growth of different film thicknesses in devices that are embedded
in different circuit layouts. This condition is an additional
dimension that must be included in a manufacturing process, and
hence require additional costs. The present invention does not
require epitaxy, and is therefore not limited by the difficulties
imposed by epitaxy.
[0054] A second approach is siliciding by laser melting. This is a
relatively new technique that allows the fabrication of different
silicide thicknesses over the gate and over the source/drain
region. This technique has not been applied in a manufacturing
context and therefore its usage in practice is unknown. The
throughput of the technique may be lower than that achieved with
the other techniques such as raised source/drain, deposition of
CoSi alloy, etc. Laser annealing is carried out per wafer, that is
the wafers are processed sequentially, one at a time. Raised
source/drain epitaxy and the present invention are parallel
techniques in the sense that the entire wafer lot may be processed
together (e.g., a single deposition is carried out on all
wafers).
[0055] The invention uses conventional fabrication techniques, and
does not have a throughput problem. The thermal budget required by
the invention is the same as in a conventional salicide
process.
[0056] A third approach employs deposition of a Co.sub.1-xSi.sub.x
alloy to limit the source and drain silicon consumed during
silicide formation. This approach is limited to a composition that
has a sufficiently small concentration of Si (x<0.2) permitting
the alloy deposited on the oxide sidewalls to be removed by
selective etching.
[0057] It is noted that the invention can utilize this technique to
further decrease the Si consumption by depositing
Co.sub.1-xSi.sub.x instead of pure Co as mentioned above. The
second advantage of Co.sub.1-xSi.sub.x is the larger temperature
window which is available for the formation of the metal-rich
phase.
[0058] Thus, the present invention overcomes the above-mentioned
and other problems of the conventional techniques and allows
forming a silicon-on-insulator (SOI) MOSFET having ultra-thin
silicon films and while preventing (or at least minimizing) the
high source/drain series resistance and maintaining its efficiency.
Thus, bulk or thick SOI films are unnecessary with the inventive
method. Further, series parasitic resistance is minimized in order
to facilitate the fabrication of high performance thin film SOI
MOSFETs with the inventive method.
[0059] While the invention has been described in terms of preferred
embodiments, those skilled in the art will recognize that the
invention can be practiced with modification within the spirit and
scope of the appended claims.
[0060] The method and structure of the present invention are not
limited to a specific silicide-forming metal. Further, the
invention, is not limited to one particular device as described
above, but can also be used in devices with a non-planar
source/drain region, such as a polysilicon sidewall source drain
(e.g., see P. M. Solomon, H. -S. P. Wong, "Method for Making Single
and Double Gate Field Effect Transistors with Sidewall Source Drain
Contacts", U.S. Pat. No. 5,773,331, Jun. 30, 1998, incorporated
herein by reference; and T. Yoshimoto et al., "Silicided
Silicon-Sidewall Source and Drain Structure for High Performance
75-nm gate length pMOSFETs," 1995 Symposium on VLSI Technology,
digest p.11).
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