| Patent | Date |
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Low Temperature Bi-cmos Compatible Process For Mems Rf Resonators And Filters
App 20120270351 - BUCHWALTER; Leena Paivikki ; et al. | 2012-10-25 |
Low temperature Bi-CMOS compatible process for MEMS RF resonators and filters
Grant 8,269,291 - Buchwalter , et al. September 18, 2 | 2012-09-18 |
Low temperature Bi-CMOS compatible process for MEMS RF resonators and filters
Grant 7,943,412 - Buchwalter , et al. May 17, 2 | 2011-05-17 |
Low Temperature BI-CMOS Compatible Process For MEMS RF Resonators and Filters
App 20110109405 - Buchwalter; Leena Paivikki ; et al. | 2011-05-12 |
Polycrystalline SiGe Junctions for advanced devices
Grant 7,741,165 - Chan , et al. June 22, 2 | 2010-06-22 |
Low temperature bi-CMOS compatible process for MEMS RF resonators and filters
App 20090108381 - Buchwalter; Leena Paivikki ; et al. | 2009-04-30 |
Polycrystalline SiGe Junctions for Advanced Devices
App 20080248635 - Chan; Kevin Kok ; et al. | 2008-10-09 |
Polycrystalline SiGe junctions for advanced devices
Grant 7,387,924 - Chan , et al. June 17, 2 | 2008-06-17 |
Shallow trench isolation structure for strained Si on SiGe
Grant 7,183,175 - Koester , et al. February 27, 2 | 2007-02-27 |
Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier
Grant 7,169,674 - Bojarczuk, Jr. , et al. January 30, 2 | 2007-01-30 |
Polycrystalline SiGe junctions for advanced devices
App 20070010076 - Chan; Kevin Kok ; et al. | 2007-01-11 |
Polycrystalline SiGe junctions for advanced devices
Grant 7,135,391 - Chan , et al. November 14, 2 | 2006-11-14 |
Self-aligned silicide (salicide) process for low resistivity contacts to thin film silicon-on-insulator and bulk mosfets and for shallow junctions
App 20060043484 - Cabral; Cyril JR. ; et al. | 2006-03-02 |
Self-aligned silicide (salicide) process for low resistivity contacts to thin film silicon-on-insulator and bulk MOSFETS and for shallow junctions
Grant 6,987,050 - Cabral, Jr. , et al. January 17, 2 | 2006-01-17 |
Polycrystalline SiGe junctions for advanced devices
App 20050260832 - Chan, Kevin Kok ; et al. | 2005-11-24 |
Shallow trench isolation structure for strained Si on SiGe
App 20050260825 - Koester, Steven John ; et al. | 2005-11-24 |
Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier
App 20050156257 - Bojarczuk, Nestor Alexander JR. ; et al. | 2005-07-21 |
Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier
Grant 6,891,231 - Bojarczuk, Jr. , et al. May 10, 2 | 2005-05-10 |
Scalable MOS field effect transistor
Grant 6,870,232 - Chan , et al. March 22, 2 | 2005-03-22 |
Shallow trench isolation structure for strained Si on SiGe
App 20040164373 - Koester, Steven John ; et al. | 2004-08-26 |
Vertical aligned liquid crystal display and method using dry deposited alignment layer films
Grant 6,724,449 - Andry , et al. April 20, 2 | 2004-04-20 |
Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby
Grant 6,716,708 - Cabral, Jr. , et al. April 6, 2 | 2004-04-06 |
Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby
App 20030132487 - Cabral, Cyril JR. ; et al. | 2003-07-17 |
Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby
Grant 6,555,880 - Cabral, Jr. , et al. April 29, 2 | 2003-04-29 |
Self-aligned silicide (salicide) process for strained silicon MOSFET on SiGe and structure formed thereby
App 20030068883 - Ajmera, Atul Champaklal ; et al. | 2003-04-10 |
Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby
Grant 6,503,833 - Ajmera , et al. January 7, 2 | 2003-01-07 |
Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier
App 20020190302 - Bojarczuk, Alexander JR. ; et al. | 2002-12-19 |
Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby
App 20020185691 - Cabral, Cyril JR. ; et al. | 2002-12-12 |
Self-aligned silicone process for low resistivity contacts to thin film silicon-on-insulator mosfets
App 20020031909 - Cabral, Cyril JR. ; et al. | 2002-03-14 |
Self-aligned silicide (salicide) process for low resistivity contacts to thin film silicon-on-insulator and bulk MOSFETS and for shallow Junctions
App 20020022366 - Cabral, Cyril JR. ; et al. | 2002-02-21 |
Back-plane for semiconductor device
Grant 6,281,551 - Chan , et al. August 28, 2 | 2001-08-28 |
Light emitting structures in back-end of line silicon technology
Grant 6,236,060 - Chan , et al. May 22, 2 | 2001-05-22 |
Scalable MOS field effect transistor
Grant 6,096,590 - Chan , et al. August 1, 2 | 2000-08-01 |
Method for making bonded metal back-plane substrates
Grant 6,057,212 - Chan , et al. May 2, 2 | 2000-05-02 |
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