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Aggregate adjustments in a cross bar neural network
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Circuit Methodology For Highly Linear And Symmetric Resistive Processing Unit
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Circuit methodology for highly linear and symmetric resistive processing unit
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Compact vertical injection punch through floating gate analog memory and a manufacture thereof
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Aggregate Adjustments In A Cross Bar Neural Network
App 20200050929 - Leobandung; Effendi ; et al. | 2020-02-13 |
Circuit Methodology For Highly Linear And Symmetric Resistive Processing Unit
App 20190228823 - Gokmen; Tayfun ; et al. | 2019-07-25 |
Circuit methodology for highly linear and symmetric resistive processing unit
Grant 10,269,425 - Gokmen , et al. | 2019-04-23 |
Compact Vertical Injection Punch through Floating Gate Analog Memory and a Manufacture Thereof
App 20190097060 - Leobandung; Effendi ; et al. | 2019-03-28 |
Circuit Methodology For Highly Linear And Symmetric Resistive Processing Unit
App 20180114572 - Gokmen; Tayfun ; et al. | 2018-04-26 |
Circuit methodology for highly linear and symmetric resistive processing unit
Grant 9,852,790 - Gokmen , et al. December 26, 2 | 2017-12-26 |
Interface engineering to optimize metal-III-V contacts
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Interface Engineering to Optimize Metal-III-V Contacts
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Self-aligned silicide process for silicon sidewall source and drain contacts and structure formed thereby
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Self-aligned silicide (salicide) process for low resistivity contacts to thin film silicon-on-insulator and bulk mosfets and for shallow junctions
App 20060043484 - Cabral; Cyril JR. ; et al. | 2006-03-02 |
Self-aligned silicide (salicide) process for low resistivity contacts to thin film silicon-on-insulator and bulk MOSFETS and for shallow junctions
Grant 6,987,050 - Cabral, Jr. , et al. January 17, 2 | 2006-01-17 |
Self-aligned silicide process for silicon sidewall source and drain contacts and structure formed thereby
App 20040108598 - Cabral, Cyril JR. ; et al. | 2004-06-10 |
Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby
Grant 6,716,708 - Cabral, Jr. , et al. April 6, 2 | 2004-04-06 |
Self-aligned silicide process for silicon sidewall source and drain contacts
Grant 6,645,861 - Cabral, Jr. , et al. November 11, 2 | 2003-11-11 |
Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby
App 20030132487 - Cabral, Cyril JR. ; et al. | 2003-07-17 |
Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby
Grant 6,555,880 - Cabral, Jr. , et al. April 29, 2 | 2003-04-29 |
Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby
App 20020185691 - Cabral, Cyril JR. ; et al. | 2002-12-12 |
Self-aligned silicide process for silicon sidewall source and drain contacts and structure formed thereby
App 20020155690 - Cabral, Cyril JR. ; et al. | 2002-10-24 |
Self-aligned silicone process for low resistivity contacts to thin film silicon-on-insulator mosfets
App 20020031909 - Cabral, Cyril JR. ; et al. | 2002-03-14 |
Self-aligned silicide (salicide) process for low resistivity contacts to thin film silicon-on-insulator and bulk MOSFETS and for shallow Junctions
App 20020022366 - Cabral, Cyril JR. ; et al. | 2002-02-21 |
Back-plane for semiconductor device
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Method for making bonded metal back-plane substrates
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Method of making EEPROM having coplanar on-insulator FET and control gate
Grant 5,960,265 - Acovic , et al. September 28, 1 | 1999-09-28 |
EEPROM having coplanar on-insulator FET and control gate
Grant 5,886,376 - Acovic , et al. March 23, 1 | 1999-03-23 |
Method for making single and double gate field effect transistors with sidewall source-drain contacts
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