U.S. patent application number 09/982221 was filed with the patent office on 2002-02-28 for pre-patterned substrate layers for being personalized as needed.
Invention is credited to Gupta, Dinesh, Herron, Lester Wynn, Knickerbocker, John U., Long, David C., Nayak, Jawahar P., O'Neil, Keith C., Peterson, Brenda L..
Application Number | 20020023779 09/982221 |
Document ID | / |
Family ID | 23599892 |
Filed Date | 2002-02-28 |
United States Patent
Application |
20020023779 |
Kind Code |
A1 |
Gupta, Dinesh ; et
al. |
February 28, 2002 |
Pre-patterned substrate layers for being personalized as needed
Abstract
A method and structure for personalizing a multi-layer substrate
structure includes supplying a generic layer having electrical
features and altering the electrical features to produce a
personalized layer of the multi-layer substrate.
Inventors: |
Gupta, Dinesh; (Hopewell
Junction, NY) ; Herron, Lester Wynn; (New Paltz,
NY) ; Knickerbocker, John U.; (Hopewell Junction,
NY) ; Long, David C.; (Wappingers Falls, NY) ;
Nayak, Jawahar P.; (Wappingers Falls, NY) ; O'Neil,
Keith C.; (Hughsonville, NY) ; Peterson, Brenda
L.; (Wappingers Falls, NY) |
Correspondence
Address: |
FREDERICK W. GIBB, III
MCGINN & GIBB, PLLC
2568-A RIVA ROAD
SUITE 304
ANNAPOLIS
MD
21401
US
|
Family ID: |
23599892 |
Appl. No.: |
09/982221 |
Filed: |
October 18, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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09982221 |
Oct 18, 2001 |
|
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09404510 |
Sep 23, 1999 |
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Current U.S.
Class: |
174/262 ;
174/255; 257/E23.171; 29/830; 29/852 |
Current CPC
Class: |
H05K 1/0306 20130101;
H01L 2924/0002 20130101; H05K 1/0298 20130101; Y10T 29/49165
20150115; H01L 2924/00 20130101; H01L 2924/0002 20130101; Y10T
29/49117 20150115; H01L 23/5382 20130101; H05K 1/0287 20130101;
Y10T 29/49126 20150115; Y10T 29/49155 20150115 |
Class at
Publication: |
174/262 ; 29/830;
29/852; 174/255 |
International
Class: |
H05K 001/11; H05K
003/36; H01K 003/10 |
Claims
What is claimed is:
1. A process for personalizing a multi-layer substrate structure
comprising: supplying a generic layer having electrical features;
and altering said electrical features to produce a personalized
layer of said multi-layer substrate.
2. The process in claim 1, wherein said altering comprises
selectively filling vias in said generic layer with conductive
material.
3. The process in claim 1, wherein said altering comprises removing
portions of electrical wiring on said generic layer.
4. The process in claim 1, further comprising supplying a second
generic layer identical to said generic layer and altering said
electrical features of said second generic layer to produce a
second personalized layer different than said personalized
layer.
5. The process in claim 1, wherein said altering changes said
generic layer into a plurality of differently personalized
layers.
6. The process in claim 1, wherein said generic layer includes a
grid of vias useful with a plurality of differently personalized
layers.
7. The process in claim 1, wherein said generic layer includes a
pattern of wiring useful with a plurality of differently
personalized layers.
8. The process in claim 1, wherein said altering comprises
selectively filling vias in said generic layer with an insulating
material.
9. The process in claim 1, wherein said altering comprises
selectively forming insulating caps adjacent selected ones of
conductive vias in said generic layer to render said selected ones
of said conductive vias non-conductive.
10. The process in claim 9, wherein said forming of said insulating
caps comprises screening a insulating paste.
11. The process in claim 9, wherein said forming of said insulating
caps comprises placing dry insulating material over said selected
ones of said conductive vias.
12. A process for personalizing a multi-layer substrate structure
comprising: supplying a layer having generic electrical features;
and altering said generic electrical features to produce a
personalized layer of said multi-layer substrate.
13. The process in claim 12, wherein said altering comprises
selectively filling vias in said layer with conductive
material.
14. The process in claim 12, wherein said altering comprises
removing portions of electrical wiring on said layer.
15. The process in claim 12, further comprising supplying a second
layer identical to said layer and altering said generic electrical
features of said second layer to produce a second personalized
layer different than said personalized layer.
16. The process in claim 12, wherein said altering changes said
layer into a plurality of differently personalized layers.
17. The process in claim 12, wherein said layer includes a generic
grid of vias useful with a plurality of differently personalized
layers.
18. The process in claim 12, wherein said layer includes a generic
pattern of wiring useful with a plurality of differently
personalized layers.
19. A multi-layer substrate structure comprising: at least one
layer having generic electrical features altered to personalize
said layer.
20. The multi-layer substrate structure in claim 19, wherein said
electrical features include vias selectively filled with conductive
material.
21. The multi-layer substrate structure in claim 19, wherein said
electrical features include a wiring pattern having portions
selectively removed.
22. The multi-layer substrate structure in claim 19, further
comprising a second layer similar to said layer and having said
generic electrical features altered differently than said layer to
personalize said second layer differently than said layer.
23. The multi-layer substrate structure in claim 19, wherein said
layer is for being changes into a plurality of differently
personalized layers.
24. The multi-layer substrate structure in claim 19, wherein said
layer includes a generic grid of vias useful with a plurality of
differently personalized layers.
25. The multi-layer substrate structure in claim 19, wherein said
layer includes a generic pattern of wiring useful with a plurality
of differently personalized layers.
26. The multi-layer substrate structure in claim 19, further
comprising: conductive vias; and insulating caps adjacent selected
ones of said conductive vias, wherein said insulating caps render
said selected ones of said conductive vias non-conductive.
27. The multi-layer substrate structure in claim 27, wherein said
insulating caps comprise a screened insulating paste.
28. The multi-layer substrate structure in claim 27, wherein said
insulating caps comprise a dry insulating material.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention generally relates to multilayer
ceramic substrates and a method of forming the same.
[0003] 2. Description of the Related Art
[0004] In traditional processing, a substrate contains signal or
redistribution layers (which contain connections between different
points) and voltage layers which look like mesh planes. Signal or
redistribution vias pass through, without connecting to, the mesh
plane. To the contrary, voltage vias connect with the mesh planes.
Conventionally, each layer is fabricated separately which makes the
process expensive and time consuming.
[0005] Ceramic packages for supporting semiconductor devices and
the like include ceramic substrates with printed conductive stripes
connected to the device and to input/output pins or other
connections which are joined to boards or the like. While many
techniques are known for forming such ceramic substrates, one of
the most popular procedures for such fabrication involves the
casting of what is termed a ceramic greensheet, personalizing
(i.e., punching and screening) the greensheet, stacking it with
other personalized greensheets and subsequently processing and
firing of the stack of ceramic greensheets. The method of producing
such multilayer ceramic (MLC) substrates for semiconductor
packaging and other electronics applications is well known as
illustrated in U.S. Pat. Nos. 4,234,367, 4,302,625 and 4,799,984,
each of which is incorporated herein by reference.
[0006] In the traditional method of building MLC substrates, each
personalized greensheet layer has a unique pattern which makes the
personalization process expensive and time consuming. Accordingly,
a new personalization process which is less expensive and time
consuming is desired.
[0007] Building multi-layer personalized substrates is expensive
and time consuming. For example, one part of the process involves
applying the signal patterns to each layer (e.g., each greensheet)
before lamination. A personalized via pattern must be drilled or
punched for each layer as well. A process is needed that would
improve the process time and reduce costs.
SUMMARY OF THE INVENTION
[0008] It is, therefore, an object of the present invention to
provide a structure and method for personalizing a multi-layer
substrate structure that includes supplying a generic layer having
electrical features and altering the electrical features to produce
a personalized layer of the multi-layer substrate. The altering
includes selectively filling vias in the generic layer with
conductive material and removing portions of electrical wiring on
the generic layer. The process further includes supplying a second
generic layer identical to the first generic layer and altering the
electrical features of the second generic layer to produce a second
personalized layer different than the first personalized layer. The
altering changes the generic layer into a plurality of differently
personalized layers. The generic layer includes a grid of vias
and/or a pattern of wiring useful with a plurality of differently
personalized layers.
[0009] Another embodiment of the invention is a process for
personalizing a multi-layer substrate structure that includes
supplying a layer having generic electrical features and altering
the generic electrical features to produce a personalized layer of
the multi-layer substrate. The altering includes selectively
filling vias in the layer with conductive material and removing
portions of electrical wiring on the layer. The process further
includes supplying a second layer identical to the first layer and
altering the generic electrical features of the second layer to
produce a second personalized layer different than the first
personalized layer. The altering changes the generic layer into a
plurality of differently personalized layers. The layer includes a
generic grid of vias and/or a generic pattern of wiring useful with
a plurality of differently personalized layers.
[0010] Yet another embodiment of the invention is a multi-layer
substrate structure that includes at least one layer having generic
electrical features altered to personalize the layer. The
electrical features include vias selectively filled with conductive
material and/or a wiring pattern having portions selectively
removed. The multi-layer substrate further includes a second layer
similar to the first layer and having the generic electrical
features altered differently than the first layer to personalize
the second layer differently from the first layer. The layer can be
changed into a plurality of differently personalized layers, and it
includes a generic grid of vias and/or a generic pattern of wiring
useful with a plurality of differently personalized layers.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The foregoing and other objects, aspects and advantages will
be better understood from the following detailed description of a
preferred embodiment of the invention with reference to the
drawings, in which:
[0012] FIG. 1A is a schematic diagram of two layers of a ceramic
substrate;
[0013] FIG. 1B is a schematic diagram path personalized on a pair
of sheets;
[0014] FIG. 2 is a flowchart representation of the process of
manufacturing multi-layer substrates.
[0015] FIGS. 3A-3C are schematic cross-sections of a ceramic sheet;
and
[0016] FIG. 4 is a perspective view of a ceramic sheet.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION
[0017] The present invention includes a process/structure which
personalizes generic signal or redistribution layers by severing
connections and forming conductive vias to create unique product
parts. The invention reduces the cost and time associated with
multi-layer ceramic (MLC) structures because generic electrical
features (e.g., wiring and via patterns) are used for multiple
products with different designs. Therefore, the cost associated
with forming unique via grids and screen printing unique wiring or
voltage patterns is avoided with the invention. In other words,
with the invention, the same generic wiring and via patterns can be
used for many different products by simply making different vias in
the pattern conductive and by severing different connections in the
wiring patterns.
[0018] Generally, vias are in certain locations (i.e., grids), and
signal layers contain wiring in only one direction (i.e., X or Y),
whereas voltage layers generally contain mesh patterns. One example
of the invention is the fabrication of voltage or reference layers
which use a common grid for many different products. The layers are
personalized for the different products by making certain vias
conductive and by severing connections on the layers (e.g.,
removing portions of the wiring patterns). Currently, in product
fabrication such as multi-layer ceramic greensheet structures, each
layer is personalized (e.g., uniquely screen printed, uniquely
punched with a via grid).
[0019] In a preferred embodiment, a family of products uses a
standard voltage pattern and each member of the family utilizes a
subset of the vias, which have been incorporated for various chip
sizes or chip footprints, to connect to the standard voltage
pattern. Therefore, with the invention, each member of the family
takes advantage of the common voltage or reference pattern.
[0020] In another embodiment, a common pattern for X, Y or
redistribution wiring is made for a given family of products. Each
layer is personalized by custom laser deletion of undesired
portions of the conductors. This methodology lends itself toward
both product specific personalization and to customized patterns
and provides a means of repair when used with patterned surface or
subsurface layers.
[0021] Referring now to FIG. 1A, two layers 10, 11 (sheet 1, X
wiring and sheet 2, Y wiring) of a ceramic substrate are shown. The
layers are pre-drilled with via holes 13 at regular grid locations.
Selected vias 12 (indicated by large circles) are filled with an
insulating material such that they do not make electrical contact
between the layers (sheets). The remainder of the vias are filled
with conductors and the conductive wiring pattern applied.
[0022] In FIG. 1B, a path is personalized on the pair of sheets by
filling certain vias with conductors and by removing certain
connections. As can be seen in FIG. 1B, the path begins at "A." A
wire segment is cut at point "B". A conductive via joins the
segments between sheets 1 and 2 at point "C". Segment C-D is
similarly isolated by cuts and connected to segment E-F with a
conductive via. E-F is similarly connected to G-H to complete the
path A-H. The layers are laminated and other layers are similarly
personalized and laminated to form the MLC substrate.
[0023] Referring now to FIG. 2, a flowchart illustrating an
embodiment of the invention is shown. In item 20 of the flowchart,
a standard (e.g., generic) array of via holes 13 are formed in a
sheet 10. Then, in item 21, selected ones of the vias 12 are filled
with a non-conductive material. Then, as shown in item 22, a
standard (e.g., generic) pattern of conductive wiring is applied
and the remaining via holes are filled with a conductive paste. As
shown in FIG. 1B, selected locations of the generic wiring pattern
are cut (item 23) to personalize the sheet. Then, the vias of sheet
10 are aligned with those of sheet 11, as shown in item 24.
Finally, in item 25 sheet 10 is laminated to sheet 11.
[0024] In the process described above, any conventional method can
be used to selectively fill the vias with a conductor or insulator,
as shown in FIG. 3A, to personalize the otherwise generic sheet.
Also illustrated in FIG. 3A are the cuts 30 in the generic wiring
pattern 31 which personalize the sheet. For example, a stencil,
mask or other similar device can be used to selectively fill the
vias with an insulator or conductor using any well known screening
process. Similarly, the electrical wiring connections 31 can be cut
30 using any well known process, such as laser cutting, physical
cutting, etching, sand blasting, punching, electrically blowing
links, grinding, etc. Alternatively, as illustrated in FIG. 3B, all
the vias are filled with a conductor 13 and insulating caps 32 are
formed over selected ones of the conductors 13 to personalize of
the sheet. As would be known by one ordinarily skilled in the art
given this disclosure, the caps 32 can be formed in any
conventional process, such as screening and other similar
processes.
[0025] Referring to FIG. 3C, all wiring (X or Y) layers, 11, have
all vias filled with conductive paste. In order to connect only
selected vias between two layers, an interposer layer 40 is used
with the selected vias, 42 (filled with conductive paste) and the
other (nonconducting) vias, 41, are left empty. Connections between
successive layers are made through selected vias. Sheet 40 may be
of different thickness to maintain overall substrate thickness.
This method offers several advantages: first a common punch pattern
could be used for all layers, second only simple through via masks
are required for interposer layers and third, no insulating
(nonconductive) paste screening is required.
[0026] Referring to FIG. 4, lines are screened such that
connections to all of the vias are made. Each layer is personalized
based on the design requirements. Connections to vias, 33, that are
not supposed to be connected are removed using methods such as
laser ablation, e-beam, sandblasting, etc. Advantages of this
method include use of common punch and screen pattern and
elimination of need for screening with insulating paste.
[0027] Thus, as described above, the invention uses common generic
pre-drilled/pre-wired substrate sheets that are personalized using
cuts (e.g., laser) and selective conductive via fills, as needed.
While a via interconnect system is described in the preferred
embodiment above, as would be known by one ordinarily skilled in
the art given this disclosure, other similar processing is possible
with the invention. For example, an insulator may be placed against
those vias that are not to be conductive thru vias as shown in FIG.
3B.
[0028] The invention allows for quicker build times for new
products and a reduction of punched sheet part numbers, which
results in larger batch size and reduced costs. It is ideal for
gang punching of a product. Minimal screening masks would be
required.
[0029] While the invention has been described in terms of preferred
embodiments, those skilled in the art will recognize that the
invention can be practiced with modification within the spirit and
scope of the appended claims.
* * * * *