Nayak; Jawahar P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Nayak; Jawahar P..The latest application filed is for "interconnected integrated circuit (ic) chip structure and packaging and method of forming same".

Company Profile

2.9.10

Nayak; Jawahar P. - Clifton Park NY
Nayak; Jawahar P. - Wappingers Falls NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Interconnected integrated circuit (IC) chip structure and packaging and method of forming same Grant 10,714,411 - Sauter , et al.	2020-07-14
Interconnected Integrated Circuit (ic) Chip Structure And Packaging And Method Of Forming Same App 20190287879 - Sauter; Wolfgang ; et al.	2019-09-19
Building metal pillars in a chip for structure support Grant 7,456,098 - Hichri , et al. November 25, 2	2008-11-25
Via barrier layers continuous with metal line barrier layers at notched or dielectric mesa portions in metal lines Grant 7,138,714 - Nguyen , et al. November 21, 2	2006-11-21
Building metal pillars in a chip for structure support App 20060190846 - Hichri; Habib ; et al.	2006-08-24
Reliability And Functionality Improvements On Copper Interconnects With Wide Metal Line Below The Via App 20060180930 - Nguyen; Du B. ; et al.	2006-08-17
Building metal pillars in a chip for structure support Grant 7,067,902 - Hichri , et al. June 27, 2	2006-06-27
Stacked via-stud with improved reliability in copper metallurgy App 20060014376 - Agarwala; Birendra N. ; et al.	2006-01-19
Stacked via-stud with improved reliability in copper metallurgy Grant 6,972,209 - Agarwala , et al. December 6, 2	2005-12-06
Building metal pillars in a chip for structure support App 20050118803 - Hichri, Habib ; et al.	2005-06-02
Halo-free non-rectifying contact on chip with halo source/drain diffusion Grant 6,750,109 - Culp , et al. June 15, 2	2004-06-15
Stacked via-stud with improved reliability in copper metallurgy App 20040101663 - Agarwala, Birendra N. ; et al.	2004-05-27
Halo-free non-rectifying contact on chip with halo source/drain diffusion App 20020149058 - Culp, James A. ; et al.	2002-10-17
Halo-free non-rectifying contact on chip with halo source/drain diffusion Grant 6,429,482 - Culp , et al. August 6, 2	2002-08-06
Pre-patterned substrate layers for being personalized as needed App 20020023779 - Gupta, Dinesh ; et al.	2002-02-28
Pre-patterned substrate layers for being personalized as needed Grant 6,341,417 - Gupta , et al. January 29, 2	2002-01-29
Process For Screening Features On An Electronic Substrate With A Low Viscosity Paste App 20020009539 - CASEY, JON A. ; et al.	2002-01-24
Single mask screening process and structure produced thereby App 20010006116 - Blazick, James M. ; et al.	2001-07-05
Single mask screening process Grant 6,238,741 - Blazick , et al. May 29, 2	2001-05-29

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