loadpatents
name:-0.02646803855896
name:-0.038342952728271
name:-0.015779972076416
Gupta; Dinesh Patent Filings

Gupta; Dinesh

Patent Applications and Registrations

Patent applications and USPTO patent grants for Gupta; Dinesh.The latest application filed is for "three-dimensional microelectronic package with embedded cooling channels".

Company Profile
15.36.23
  • Gupta; Dinesh - Hopewell Junction NY
  • Gupta; Dinesh - Sunnyvale CA
  • Gupta; Dinesh - Tullahoma TN
  • Gupta; Dinesh - San Jose CA US
  • Gupta; Dinesh - New Delhi IN
  • Gupta; Dinesh - South Windsor CT
  • Gupta; Dinesh - Prasad Nagar IN
  • Gupta, Dinesh - HopewellJunction NY
  • Gupta, Dinesh - S. Windsor CT
  • Gupta, Dinesh - Hopewell NY
  • Gupta; Dinesh - Poughkeepsie NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Direct bonded heterogeneous integration packaging structures
Grant 11,177,217 - Sikka , et al. November 16, 2
2021-11-16
Semiconductor microcooler
Grant 11,056,418 - Canaperi , et al. July 6, 2
2021-07-06
Semiconductor microcooler
Grant 11,049,789 - Canaperi , et al. June 29, 2
2021-06-29
Semiconductor wafer having trenches with varied dimensions for multi-chip modules
Grant 11,049,844 - Bonam , et al. June 29, 2
2021-06-29
Three-dimensional Microelectronic Package With Embedded Cooling Channels
App 20210118854 - Sikka; Kamal K. ;   et al.
2021-04-22
Planar Wafer Level Fan-out Of Multi-chip Modules Having Different Size Chips
App 20210091032 - Bonam; Ravi K. ;   et al.
2021-03-25
Planar wafer level fan-out of multi-chip modules having different size chips
Grant 10,943,883 - Bonam , et al. March 9, 2
2021-03-09
Three-dimensional microelectronic package with embedded cooling channels
Grant 10,937,764 - Sikka , et al. March 2, 2
2021-03-02
Semiconductor Wafer Having Trenches With Varied Dimensions For Multi-chip Modules
App 20210005573 - Bonam; Ravi K. ;   et al.
2021-01-07
Three-dimensional Microelectronic Package With Embedded Cooling Channels
App 20200294968 - Sikka; Kamal K. ;   et al.
2020-09-17
Semiconductor Microcooler
App 20200161216 - Canaperi; Donald F. ;   et al.
2020-05-21
Direct Bonded Heterogeneous Integration Packaging Structures
App 20200144187 - Sikka; Kamal K. ;   et al.
2020-05-07
Semiconductor Microcooler
App 20200118904 - Canaperi; Donald F. ;   et al.
2020-04-16
Direct bonded heterogeneous integration packaging structures
Grant 10,580,738 - Sikka , et al.
2020-03-03
Semiconductor Microcooler
App 20200051896 - Canaperi; Donald F. ;   et al.
2020-02-13
Semiconductor Microcooler
App 20200051886 - Canaperi; Donald F. ;   et al.
2020-02-13
Semiconductor microcooler
Grant 10,553,522 - Canaperi , et al. Fe
2020-02-04
Semiconductor microcooler
Grant 10,553,516 - Canaperi , et al. Fe
2020-02-04
Copper microcooler structure and fabrication
Grant 10,490,480 - Lie , et al. Nov
2019-11-26
Copper microcooler structure and fabrication
Grant 10,490,481 - Lie , et al. Nov
2019-11-26
Direct Bonded Heterogeneous Integration Packaging Structures
App 20190295952 - Sikka; Kamal K. ;   et al.
2019-09-26
Machine readable products for single pass parallel hierarchical timing closure of integrated circuit designs
Grant 9,165,098 - Bhardwaj , et al. October 20, 2
2015-10-20
Multi-phase models for timing closure of integrated circuit designs
Grant 9,152,742 - Gupta , et al. October 6, 2
2015-10-06
Catheter with Gills
App 20150265805 - Vakili; Ahmad D. ;   et al.
2015-09-24
Circuit design system and method of generating hierarchical block-level timing constraints from chip-level timing constraints
Grant 8,977,994 - Levitsky , et al. March 10, 2
2015-03-10
Methods for single pass parallel hierarchical timing closure of integrated circuit designs
Grant 8,935,642 - Bhardwaj , et al. January 13, 2
2015-01-13
Multi-phase models for timing closure of integrated circuit designs
Grant 8,640,066 - Gupta , et al. January 28, 2
2014-01-28
Systems for single pass parallel hierarchical timing closure of integrated circuit designs
Grant 8,539,402 - Bhardwaj , et al. September 17, 2
2013-09-17
Flow methodology for single pass parallel hierarchical timing closure of integrated circuit designs
Grant 8,365,113 - Bhardwaj , et al. January 29, 2
2013-01-29
Optical assemblies for transmitting and manipulating optical beams
Grant 8,089,133 - Gupta , et al. January 3, 2
2012-01-03
System and method of generating hierarchical block-level timing constraints from chip-level timing constraints
Grant 7,926,011 - Levitsky , et al. April 12, 2
2011-04-12
Methods and apparatus for deskewing VCAT/LCAS members
Grant 7,672,315 - Gupta , et al. March 2, 2
2010-03-02
Refractory metal core coatings
Grant 7,575,039 - Beals , et al. August 18, 2
2009-08-18
Combined hardware and software implementation of link capacity adjustment scheme (LCAS) in SONET (synchronous optical network) virtual concatenation (VCAT)
Grant 7,558,287 - Malik , et al. July 7, 2
2009-07-07
Refractory Metal Core Coatings
App 20090114797 - Beals; James T. ;   et al.
2009-05-07
Methods and apparatus for deskewing VCAT/LCAS members
App 20070047593 - Gupta; Dinesh ;   et al.
2007-03-01
Combined hardware and software implementation of link capacity adjustment scheme (LCAS) in SONET (synchronous optical network) virtual concatenation (VCAT)
App 20070047594 - Malik; Rakesh Kumar ;   et al.
2007-03-01
Optical assemblies for transmitting and manipulating optical beams
App 20050078376 - Gupta, Dinesh ;   et al.
2005-04-14
Optical assemblies for transmitting and manipulating optical beams
Grant 6,836,015 - Denneau , et al. December 28, 2
2004-12-28
Optical Assemblies For Transmitting And Manipulating Optical Beams
App 20040217464 - Denneau, Monty M. ;   et al.
2004-11-04
Apparatus and method for repairing electronic packages
Grant 6,713,686 - Becker , et al. March 30, 2
2004-03-30
Screening mask having a stress-relieving area
Grant 6,662,718 - Barrington , et al. December 16, 2
2003-12-16
Screening method for double pass screening
Grant 6,631,675 - Brody , et al. October 14, 2
2003-10-14
Hybrid thermal barrier coating and method of making the same
App 20030152814 - Gupta, Dinesh ;   et al.
2003-08-14
Apparatus and method for repairing electronic packages
App 20030136581 - Becker, Wiren D. ;   et al.
2003-07-24
Screening mask having a stress-relieving area
App 20030004076 - Barrington, Evelyn ;   et al.
2003-01-02
Mask and screening method for double pass screening
App 20020157546 - Brody, Jeffrey A. ;   et al.
2002-10-31
Pre-patterned substrate layers for being personalized as needed
App 20020023779 - Gupta, Dinesh ;   et al.
2002-02-28
Pre-patterned substrate layers for being personalized as needed
Grant 6,341,417 - Gupta , et al. January 29, 2
2002-01-29
Process For Screening Features On An Electronic Substrate With A Low Viscosity Paste
App 20020009539 - CASEY, JON A. ;   et al.
2002-01-24
Multilayer ceramic substrates having internal capacitor, and process for producing same
Grant 5,655,209 - Casey , et al. August 5, 1
1997-08-05
Method for making ceramic substrates from thin and thick ceramic greensheets
Grant 5,601,672 - Casey , et al. February 11, 1
1997-02-11
Process for producing circuitized layers and multilayer ceramic sub-laminates and composites thereof
Grant 5,480,503 - Casey , et al. January 2, 1
1996-01-02

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