U.S. patent application number 09/754924 was filed with the patent office on 2001-05-17 for capacitor structures.
Invention is credited to Breiner, Lyle D., Doan, Trung Tri, Ireland, Philip J., Rhodes, Howard E., Sandhu, Gurtej S., Sharan, Sujit.
Application Number | 20010001210 09/754924 |
Document ID | / |
Family ID | 23331061 |
Filed Date | 2001-05-17 |
United States Patent
Application |
20010001210 |
Kind Code |
A1 |
Rhodes, Howard E. ; et
al. |
May 17, 2001 |
Capacitor Structures
Abstract
Integrated circuitry capacitors and methods of forming the same
are described. In accordance with one implementation, a capacitor
plate is formed and a conductive layer of material is formed
thereover. Preferably, the conductive layer of material is more
conductive than the material from which the capacitor plate is
formed. In a preferred implementation, the conductive layer of
material comprises a titanium or titanium-containing layer. In
another preferred implementation, the capacitor plate comprises an
inner capacitor plate having an outer surface with a generally
roughened surface area. In one aspect of this implementation, the
roughened surface area comprises hemispherical grain polysilicon.
Capacitors formed in accordance with the invention are particularly
well suited for use in dynamic random access memory (DRAM)
circuitry.
Inventors: |
Rhodes, Howard E.; (Boise,
ID) ; Breiner, Lyle D.; (Meridian, ID) ;
Ireland, Philip J.; (Nampa, ID) ; Doan, Trung
Tri; (Boise, ID) ; Sandhu, Gurtej S.; (Boise,
ID) ; Sharan, Sujit; (Boise, ID) |
Correspondence
Address: |
WELLS ST JOHN ROBERTS GREGORY AND MATKIN
SUITE 1300
601 W FIRST AVENUE
SPOKANE
WA
992013828
|
Family ID: |
23331061 |
Appl. No.: |
09/754924 |
Filed: |
January 3, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09754924 |
Jan 3, 2001 |
|
|
|
09339890 |
Jun 25, 1999 |
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Current U.S.
Class: |
257/296 ;
257/309; 257/534; 257/E21.013; 257/E21.016; 257/E21.019;
257/E21.59; 257/E21.649; 257/E29.345; 438/239 |
Current CPC
Class: |
H01L 29/94 20130101;
H01L 28/87 20130101; H01L 28/91 20130101; H01L 27/10855 20130101;
H01L 21/76895 20130101; H01L 28/84 20130101 |
Class at
Publication: |
257/296 ;
438/239; 257/309; 257/534 |
International
Class: |
H01L 029/00; H01L
021/8242; H01L 027/108; H01L 029/94; H01L 029/76; H01L 031/119 |
Claims
1. A method of forming a capacitor comprising: forming a conductive
capacitor plate; forming a capacitor dielectric layer operably
proximate the capacitor plate; and forming a metal layer
intermediate the conductive capacitor plate and the capacitor
dielectric layer.
2. The method of claim 1, wherein the forming of the metal layer
comprises chemical vapor depositing an elemental metal layer over
the conductive capacitor plate prior to providing the capacitor
dielectric layer.
3. The method of claim 1, wherein the forming of the metal layer
comprises chemical vapor depositing a titanium layer over the
conductive capacitor plate.
4. The method of claim 1, wherein the forming of the metal layer
comprises chemical vapor depositing a titanium silicide layer over
the conductive capacitor plate.
5. The method of claim 1, wherein the forming of the metal layer
comprises chemical vapor depositing a platinum layer over the
conductive capacitor plate.
6. The method of claim 1, wherein the forming of the metal layer
comprises chemical vapor depositing a TiN layer over the conductive
capacitor plate.
7. The method of claim 1, wherein the conductive capacitor plate
comprises polysilicon and the forming of the metal layer comprises
chemical vapor depositing the metal layer onto the polysilicon.
8. The method of claim 1, wherein the conductive capacitor plate
comprises hemispherical grain polysilicon and the forming of the
metal layer comprises chemical vapor depositing a titanium layer
onto the hemispherical grain polysilicon.
9. A method of forming a capacitor comprising: forming a conductive
capacitor plate comprising polysilicon; forming a capacitor
dielectric layer operably proximate the conductive capacitor plate;
and forming a metal layer intermediate the conductive capacitor
plate and the capacitor dielectric layer.
10. The method of claim 9, wherein the metal layer is formed to be
at least in partial physical contacting relationship with the
capacitor dielectric layer.
11. The method of claim 9, wherein the forming of the metal layer
comprises chemical vapor depositing the metal layer over the
conductive capacitor plate.
12. The method of claim 9 further comprising: prior to the forming
of the metal layer, forming a doped polysilicon layer over a
substrate and a layer comprising roughened polysilicon over the
doped polysilicon layer to form the conductive capacitor plate; and
wherein the forming of the metal layer comprises chemical vapor
depositing the metal layer over the roughened polysilicon
layer.
13. The method of claim 9 further comprising: prior to the forming
of the metal layer, forming a doped polysilicon layer over a
substrate and a layer comprising undoped hemispherical grain
polysilicon over the doped polysilicon layer to form the conductive
capacitor plate; outdiffusing dopant from the doped polysilicon
layer into the hemispherical grain polysilicon layer; and wherein
the forming of the metal layer comprises chemical vapor depositing
a titanium layer over the hemispherical grain polysilicon
layer.
14. A method of forming a capacitor comprising: forming a capacitor
plate layer comprising conductively doped roughened polysilicon;
forming a dielectric material layer operably proximate the
capacitor plate layer; and interposing a conductive layer between
the capacitor plate layer and the dielectric material layer, the
conductive layer being more conductive than the capacitor plate
layer.
15. The method of claim 14, wherein the conductive layer consists
essentially of non-semiconductive material.
16. The method of claim 14, wherein the conductive layer comprises
titanium.
17. The method of claim 14, wherein the roughened polysilicon
comprises hemispherical grain polysilicon and the interposing of
the conductive layer comprises chemical vapor depositing a
titanium-containing layer over the hemispherical grain
polysilicon.
18. A method of forming a capacitor comprising: forming a
conductive capacitor plate comprising roughened polysilicon;
forming a capacitor dielectric layer operably proximate the
conductive capacitor plate; and forming a metal layer consisting
essentially of titanium intermediate the conductive capacitor plate
and the capacitor dielectric layer.
19. The method of claim 18, wherein the forming of the metal layer
comprises chemical vapor depositing the layer over the capacitor
plate.
20. The method of claim 18, wherein the roughened polysilicon layer
comprises hemispherical grain polysilicon and the forming of the
metal layer comprises chemical vapor depositing the layer over the
layer comprising hemispherical grain polysilicon.
21. A method of forming a capacitor comprising: forming a first
layer comprising conductive material over a substrate outer
surface; forming a second layer comprising conductive material over
the first layer of conductive material; forming a layer comprising
conductive metal over the second layer; and forming a layer of
dielectric material: and a cell plate layer operatively proximate
the conductive metal layer to form a capacitor.
22. The method of claim 21, wherein: the forming of the first layer
comprises forming conductively doped polysilicon over the substrate
outer surface; and the forming of the second layer comprises
forming a layer comprising roughened polysilicon over the first
layer and outdiffusing dopant from the first layer into the second
layer.
23. The method of claim 21, wherein: the forming of the first layer
comprises forming conductively doped polysilicon over the substrate
outer surface; and the forming of the second layer comprises
forming a layer comprising hemispherical grain polysilicon over the
first layer and outdiffusing dopant from the first layer into the
second layer.
24. The method of claim 21, wherein the forming of the layer
comprising the conductive metal comprises chemical vapor depositing
the metal over the second layer.
25. The method of claim 21, wherein: the forming of the second
layer comprises forming a layer comprising hemispherical grain
polysilicon over the first layer; and the forming of the layer
comprising the conductive metal comprises chemical vapor depositing
elemental titanium over the layer comprising hemispherical grain
polysilicon.
26. A method of forming a capacitor comprising: forming a doped
semiconductive material over a substrate, the material having a
first average conductivity; forming a conductive material over the
doped semiconductive material, the conductive material having a
second average conductivity which is greater than the first average
conductivity; forming a capacitor dielectric layer over the
conductive material; and forming an outer capacitor plate over the
capacitor dielectric layer.
27. The method of claim 26, wherein the conductive material is not
conductively doped semiconductive material.
28. The method of claim 26, wherein the forming of the conductive
material comprises forming a material other than doped
semiconductive material over the doped semiconductive material.
29. The method of claim 26, wherein the forming of the conductive
material comprises forming a layer of elemental metal over the
doped semiconductive material.
30. The method of claim 26, wherein the forming of the conductive
material comprises forming a metal alloy layer over the doped
semiconductive material.
31. The method of claim 26, wherein the forming of the conductive
material comprises forming a metal compound layer over the doped
semiconductive material.
32. The method of claim 26, wherein: the forming of the doped
semiconductive material comprises forming a layer comprising doped
polysilicon over the substrate and forming a layer of hemispherical
grain polysilicon over the layer comprising doped polysilicon; and
the forming of the conductive material comprises chemical vapor
depositing a layer of titanium over the layer of hemispherical
grain polysilicon.
33. A method of forming a capacitor comprising: forming a first
capacitor plate comprising an outer surface of hemispherical grain
polysilicon; forming an elemental titanium layer over the outer
surface; forming a capacitor dielectric layer over the elemental
titanium layer; forming a second capacitor plate over the capacitor
dielectric layer.
34. The method of claim 33, wherein the forming of the elemental
titanium layer comprises chemical vapor depositing the layer over
the hemispherical grain polysilicon.
35. The method of claim 33, wherein the forming of the first
capacitor plate comprises: forming a layer of conductively doped
polysilicon over a substrate; forming a layer of hemispherical
grain polysilicon over the layer of conductively doped polysilicon;
and outdiffusing dopant from the conductively doped polysilicon
into the hemispherical grain polysilicon.
36. A method of forming a DRAM storage capacitor comprising:
forming a capacitor opening relative to insulative layer formed
over a substrate, the capacitor opening being disposed
elevationally over a node location with which electrical connection
is to be made; forming a first polysilicon material layer within
the capacitor opening and in electrical communication with the node
location, the first polysilicon material layer having a first
conductivity; forming a second polysilicon material layer over the
first polysilicon material layer, the second polysilicon material
layer having an outermost surface with a generally roughened
surface area; forming a layer comprising a metal material over the
second polysilicon material layer's outermost surface, the metal
material layer having a second conductivity which is greater than
the first conductivity; forming a layer comprising a dielectric
material over the metal material layer; and forming a cell plate
layer over the dielectric material layer to form a storage
capacitor.
37. The method of claim 36, wherein the forming of the second
polysilicon material layer comprises forming a layer of
hemispherical grain polysilicon over the first polysilicon material
layer.
38. The method of claim 36, wherein the forming of the layer
comprising a metal material comprises chemical vapor depositing a
layer comprising titanium over the second polysilicon material
layer's outermost surface.
39. A capacitor comprising: a substrate having a node location; an
insulative layer disposed over the substrate and having an opening
over the node location; a first polysilicon material layer having a
first conductivity, the layer being disposed within the opening and
operably connected with the node location; a second polysilicon
material layer over the first polysilicon material layer, the
second polysilicon material layer having an outermost surface with
a generally roughened surface area; a non-polysilicon conductive
layer over the second polysilicon material layer's outermost
surface, the conductive layer having a second conductivity which is
greater than the first conductivity; a capacitor dielectric layer
over the conductive material layer; and a capacitor plate over the
capacitor dielectric layer.
40. The capacitor of claim 39, wherein the capacitor plate
comprises a cell plate layer which constitutes a portion of DRAM
circuitry.
41. The capacitor of claim 39, wherein the second polysilicon
material comprises hemispherical grain polysilicon.
42. The capacitor of claim 39, wherein the conductive material
layer comprises elemental titanium or a titanium alloy.
43. The capacitor of claim 39, wherein the conductive material
layer comprises TiN.
44. The capacitor of claim 39, wherein the conductive material
layer comprises platinum.
45. A capacitor comprising: a substrate having a node location; a
doped semiconductive material capacitor plate operably proximate
the node location; a metal layer disposed over and operably
proximate the first capacitor plate; a capacitor dielectric layer
disposed over the metal layer and spaced from the semiconductive
material capacitor plate; and a capacitor plate over the capacitor
dielectric layer.
46. A capacitor comprising: a substrate having a node location; a
conductive inner capacitor plate comprising polysilicon operably
proximate the node location; a metal layer disposed over and in
physical contact with the conductive capacitor plate; a capacitor
dielectric layer disposed over the metal layer and in physical
contact therewith; and an outer capacitor plate over the capacitor
dielectric layer.
47. A capacitor comprising: a substrate having a node location; an
inner conductive capacitor plate having a doped roughened
polysilicon outer surface, the plate being connected with the node
location and having a first average conductivity; a conductive
layer connected with the inner conductive capacitor plate and
having a second average conductivity which is greater than the
first average conductivity; a dielectric layer connected with the
conductive layer; and an outer conductive capacitor plate connected
with the dielectric layer.
48. A capacitor comprising: a substrate having a node location; an
inner conductive capacitor plate having a roughened outer surface
comprising hemispherical grain polysilicon; a metal layer
consisting essentially of titanium conformally proximate the
roughened outer surface and connected with the capacitor plate; a
capacitor dielectric layer over the metal layer; and an outer
conductive capacitor plate connected with the dielectric layer.
49. A capacitor comprising: a substrate having an outer surface; a
first layer comprising conductive material over the outer surface;
a second layer comprising conductive material over the first layer
of material, the first and second layers being different from one
another, the second layer having an outer roughened surface; a
conductive titanium-containing layer disposed in conformal physical
contacting relation with the second layer; a dielectric layer over
the titanium-containing layer; and a cell plate layer operatively
proximate the dielectric layer.
50. A capacitor comprising: a substrate having an outer surface; a
doped semiconductive material over the outer surface and having a
first average conductivity; a conductive material over the doped
semiconductive material, the conductive material having a second
average conductivity which is greater than the first average
conductivity, the doped semiconductive material and the conductive
material comprising an inner capacitor plate; a capacitor
dielectric layer over the conductive material; and an outer
capacitor plate over the capacitor dielectric layer.
51. A capacitor comprising: a first capacitor plate comprising an
outer surface of hemispherical grain polysilicon; an elemental
titanium layer over the outer surface; a capacitor dielectric layer
over the elemental titanium layer; and a second capacitor plate
over the capacitor dielectric layer.
Description
TECHNICAL FIELD
1. This invention relates to integrated circuitry capacitors and
methods of forming the same.
BACKGROUND OF THE INVENTION
2. One common goal in capacitor fabrication is to maximize the
capacitance for a given size capacitor. It is desirable that stored
charge be at a maximum immediately at the physical interface
between the respective electrodes or capacitor plates and the
capacitor dielectric material between the plates. Typical
integrated circuitry capacitors have electrodes or plates which are
formed from doped semiconductive material such as polysilicon. The
polysilicon is usually heavily doped to impart a desired degree of
conductivity for satisfactory capacitor plate operation.
3. One drawback of heavily doping polysilicon is that during
operation a charge depletion region develops at the interface where
charge maximization is desired. Hence, a desired level of charge
storage is achieved at a location which is displaced from the
interface between the capacitor plate and the dielectric
material.
4. Another drawback of heavily doping the polysilicon capacitor
plates is that during processing, some of the dopant can migrate
away from the polysilicon and into other substrate structures.
Dopant migration can adversely affect the performance of such
structures. For example, one type of integrated circuitry which
utilizes capacitors are memory cells, and more particularly dynamic
random access memory (DRAM) devices. Migratory dopants from doped
polysilicon capacitor plates can adversely impact adjacent access
transistors as by undesirably adjusting the threshold voltages.
5. As the memory cell density of DRAMs increases there is a
continuous challenge to maintain sufficiently high storage
capacitance despite decreasing cell area. Additionally there is a
continuing goal to further decrease cell area. The principal way of
increasing cell capacitance heretofore has been through cell
structure techniques. Such techniques include three dimensional
cell capacitors such as trench or stacked capacitors.
6. This invention arose out of concerns associated with improving
integrated circuitry capacitors. This invention also grew out of
concerns associated with maintaining and improving the capacitance
and charge storage capabilities of capacitors utilized in memory
cells comprising DRAM devices.
SUMMARY OF THE INVENTION
7. Integrated circuitry capacitors and methods of forming the same
are described. In accordance with one implementation, a capacitor
plate is formed and a conductive layer of material is formed
thereover. Preferably, the conductive layer of material is more
conductive than the material from which the capacitor plate is
formed. In a preferred implementation, the conductive layer of
material comprises a titanium or titanium-containing layer. Other
materials can be used such as chemical vapor deposited platinum,
TiN, and the like. In another preferred implementation, the
capacitor plate comprises an inner capacitor plate having an outer
surface with a generally roughened surface area. In one aspect of
this implementation, the roughened surface area comprises
hemispherical grain polysilicon. Capacitors formed in accordance
with the invention are particularly well suited for use in dynamic
random access memory (DRAM) circuitry.
BRIEF DESCRIPTION OF THE DRAWINGS
8. Preferred embodiments of the invention are described below with
reference to the following accompanying drawings.
9. FIG. 1 is a view of a semiconductor wafer fragment undergoing
processing in accordance with the invention.
10. FIG. 2 is a view of the FIG. 1 wafer fragment at a processing
step subsequent to that shown in FIG. 1.
11. FIG. 3 is a view of the FIG. 1 wafer fragment at a processing
step subsequent to that shown in FIG. 2.
12. FIG. 4 is a view of the FIG. 1 wafer fragment at a processing
step subsequent to that shown in FIG. 3.
13. FIG. 5 is a view of the FIG. 1 wafer fragment at a processing
step subsequent to that shown in FIG. 4.
14. FIG. 6 is a view of the FIG. 1 wafer fragment at a processing
step subsequent to that shown in FIG. 5.
15. FIG. 7 is a view of the FIG. 1 wafer fragment at a processing
step subsequent to that shown in FIG. 6.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
16. This disclosure of the invention is submitted in furtherance of
the constitutional purposes of the U.S. Patent Laws "to promote the
progress of science and useful arts" (Article 1, Section 8).
17. Referring to FIG. 1, a semiconductor wafer fragment in process
is indicated generally at 10 and includes a semiconductor substrate
12. In the context of this document, the term "semiconductor
substrate" is defined to mean any construction comprising
semiconductor material, including, but not limited to, bulk
semiconductor materials such as a semiconductor wafer (either alone
or in assemblies comprising other materials thereon), and
semiconductor material layers (either alone or in assemblies
comprising other materials). The term "substrate" refers to any
supporting structure, including, but not limited to, the
semiconductor substrates described above.
18. Isolation oxide regions 14 are formed relative to substrate 12
and define therebetween a substrate active area over which a
plurality of capacitors are to be formed. Conductive lines 16, 18,
20, and 22 are provided over substrate 12. Such lines typically
include, as shown for line 16, a thin oxide layer 24, a conductive
polysilicon layer 26, a silicide layer 28, a protective insulative
cap 30, and sidewall spacers 32. A plurality of diffusion regions
17, 19, and 21 are received within substrate 12 and constitute
source/drain regions for transistors which serve as access
transistors for the capacitors to be formed. Diffusion regions 17,
19 and 21 define substrate node locations with which electrical
communication is desired. An insulative layer 34 is formed over
substrate 12 and typically comprises an oxides such as
borophosphosilicate glass. Of course, other materials such as
phosphosilicate glass, borosilicate glass, and the like can be
used. Subsequently, insulative layer 34 is patterned and etched to
define openings 36, 38 over diffusion regions 17, 21 respectively,
and relative to which capacitors are to be formed. Insulative layer
34 defines a substrate outer surface 35.
19. A first layer 40 is formed over substrate outer surface 35. An
exemplary and preferred material for layer 40 comprises a
conductive or semiconductive material such as conductively doped
polysilicon. Layer 40 defines at least a portion of a first or
inner capacitor plate. Layer 40 also has a first conductivity and
defines a capacitor plate which is operably adjacent and in
electrical communication with the node locations defined by
diffusion regions 17 and 21. Accordingly, layer 40 is electrically
connected with the node locations defined by diffusion regions 17,
21.
20. Referring to FIG. 2, a second layer 42 is formed over first
layer 40. In a preferred implementation, second layer 42 comprises
a conductive material which constitutes roughened or rugged
polysilicon. An exemplary and preferred roughened or rugged
polysilicon is hemispherical grain polysilicon. Such is, in one
aspect, substantially undoped as formed over first layer 40.
Subsequently, and through suitable processing, outdiffusion of
dopant from conductively doped polysilicon layer 40 into layer 42
renders second layer 42 conductive. Together, layers 40 and 42
constitute a doped semiconductive material having a first average
conductivity. Accordingly, layers 40 and 42 constitute a first or
inner capacitor plate having an outermost surface 44 of
hemispherical grain polysilicon. Accordingly, outermost surface 44
defines a generally roughened surface area.
21. Referring to FIG. 3, a layer 46 is formed over substrate 12 and
outer surface 44 of layer 42. According to one aspect, layer 46
constitutes a conductive material having a second average
conductivity which is greater than the first average conductivity
of layers 40, 42. A preferred manner of forming layer 46 is through
suitable chemical vapor deposition thereof over layer 42.
Accordingly, such forms a generally conformal layer over the
roughened surface area of the preferred hemispherical grain
polysilicon layer 42. Hence, layer 46 is disposed over and operably
adjacent layers 40, 42.
22. Suitable materials for layer 46 include conductive metal
compounds, metal alloys, and elemental metals. Other suitable
materials include those which are preferably not conductively doped
semiconductive material such as polysilicon. Accordingly, layer 46
constitutes a material other than doped semiconductive material. An
exemplary and preferred material for layer 46 is elemental titanium
which is chemical vapor deposited over layer 42. Other materials
can be used such as chemical vapor deposited platinum, TiN, and the
like. Layer 46 is preferably chemical vapor deposited directly onto
the hemispherical grain polysilicon material of layer 42.
23. Referring to FIG. 4, layers 40, 42, and 46 are planarized to
electrically isolate the layers within respective opening 36, 38.
Exemplary planarization techniques include mechanical abrasion of
the substrate as by chemical mechanical polishing. Other techniques
are possible.
24. Referring to FIG. 5, a capacitor dielectric layer 48 is formed
operably proximate the first capacitor plate, over layer 46 and
within openings 36, 38. Accordingly, layer 48 is spaced from the
material of layers 40, 42 a distance which is defined by layer 46.
Exemplary materials for layer 48 are Si.sub.3N.sub.4 and SiO.sub.2
alone, or in combination. Other materials such as tantalum
pentoxide (Ta.sub.2O.sub.5), barium strontium titanate (BST), and
other dielectric materials can be used.
25. Alternately considered, the preferred metal layer 46 is formed
intermediate conductive capacitor plate 40, 42 and capacitor
dielectric layer 48 preferably by chemical vapor deposition prior
to providing capacitor dielectric layer 48. As formed, metal layer
46 is at least in partial physical contacting relationship with
capacitor dielectric layer 48. Accordingly, layer 46 is interposed
between capacitor plate 40, 42 and dielectric layer 48. In a most
preferred aspect, conductive layer 46 consists essentially of
non-semiconductive material such as titanium, or titanium
silicide.
26. Referring to FIG. 6, a second capacitor plate layer 50 is
formed over dielectric layer 48 and operatively proximate layer 46.
In a preferred implementation, layer 50 defines an outer capacitor
plate which defines a cell plate layer of a DRAM storage capacitor.
An exemplary material for capacitor plate layer 50 is
polysilicon.
27. Referring to FIG. 7, individual storage capacitors are
patterned and etched to form capacitors 52, 54. An insulative layer
56 is formed thereover and is subsequently patterned and etched to
form an opening which outwardly exposes diffusion region 19.
Subsequently formed conductive material 58 provides a conductive
bit line contact plug, and a subsequently formed conductive layer
60 provides a bit line in operative electrical contact therewith.
Accordingly, such defines, in the illustrated and preferred
embodiment, DRAM storage cells comprising storage capacitors 52,
54. The FIG. 7 construction illustrates but one example of DRAM
storage cell constructions. Of course, other constructions which
utilize the inventive methodology are possible
28. The above-described methodology and capacitor constructions
provide a desirable solution to concerns associated with charge
depletion effects at the interface between a capacitor plate and a
dielectric layer. The interpositioning of a layer of conductive
material relative to the capacitor plate and the dielectric layer,
which is more conductive than capacitor plate, effectively
relocates the location of the capacitor's stored charge to a more
desirable location. In addition, in implementations where doped
semiconductive material is utilized for an inner capacitor plate
and the "more conductive" interposed layer is formed thereover, a
lesser degree of doping can be utilized such that dopant migration
into other substrate structures is reduced. This is particularly
useful when the capacitor plate includes an additional layer which
is generally undoped as formed and subsequently rendered suitably
conductive by outdiffusion of dopant from an adjacent layer.
29. In compliance with the statute, the invention has been
described in language more or less specific as to structural and
methodical features. It is to be understood, however, that the
invention is not limited to the specific features shown and
described, since the means herein disclosed comprise preferred
forms of putting the invention into effect. The invention is,
therefore, claimed in any of its forms or modifications within the
proper scope of the appended claims appropriately interpreted in
accordance with the doctrine of equivalents.
* * * * *