Ireland; Philip J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ireland; Philip J..The latest application filed is for "electronic component guard ring".

Company Profile

1.65.58

Ireland; Philip J. - Nampa ID
Ireland; Philip J. - Boise ID

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Electronic component guard ring Grant 11,018,097 - Zhu , et al. May 25, 2	2021-05-25
Microelectronic devices with through-silicon vias and associated methods of manufacturing Grant 10,978,386 - Kirby , et al. April 13, 2	2021-04-13
Electronic Component Guard Ring App 20200194385 - Zhu; Hongbin ; et al.	2020-06-18
Electronic component guard ring Grant 10,504,859 - Zhu , et al. Dec	2019-12-10
Semiconductor constructions Grant 10,121,738 - Wood , et al. November 6, 2	2018-11-06
Electronic Component Guard Ring App 20180096955 - Zhu; Hongbin ; et al.	2018-04-05
Semiconductor Constructions App 20170125342 - Wood; Alan G. ; et al.	2017-05-04
Semiconductor constructions having through-substrate interconnects Grant 9,583,419 - Wood , et al. February 28, 2	2017-02-28
Apparatuses and methods for die seal crack detection Grant 9,557,376 - Dennison , et al. January 31, 2	2017-01-31
Microelectronic Devices With Through-silicon Vias And Associated Methods Of Manufacturing App 20160233160 - Kirby; Kyle K. ; et al.	2016-08-11
Apparatuses And Methods For Die Seal Crack Detection App 20160195581 - Dennison; Charles H. ; et al.	2016-07-07
Via chain testing structure and method Grant 9,347,985 - Ireland , et al. May 24, 2	2016-05-24
Microelectronic devices with through-silicon vias and associated methods of manufacturing Grant 9,343,362 - Kirby , et al. May 17, 2	2016-05-17
Apparatuses and methods for die seal crack detection Grant 9,287,184 - Dennison , et al. March 15, 2	2016-03-15
Apparatuses And Methods For Die Seal Crack Detection App 20150170979 - Dennison; Charles H. ; et al.	2015-06-18
Semiconductor Constructions Having Through-Substrate Interconnects App 20150130029 - Wood; Alan G. ; et al.	2015-05-14
Methods of forming through-substrate interconnects Grant 8,853,072 - Wood , et al. October 7, 2	2014-10-07
Microelectronic Devices With Through-silicon Vias And Associated Methods Of Manufacturing App 20140287584 - Kirby; Kyle K. ; et al.	2014-09-25
Microelectronic devices with through-silicon vias and associated methods of manufacturing Grant 8,753,981 - Kirby , et al. June 17, 2	2014-06-17
Sleeve insulators and semiconductor device including the same Grant 8,680,595 - Ireland , et al. March 25, 2	2014-03-25
Self-aligned, integrated circuit contact Grant 8,569,893 - Ireland October 29, 2	2013-10-29
Via structure Grant 8,482,131 - Ireland July 9, 2	2013-07-09
Interconnect regions Grant 8,410,612 - Kirby , et al. April 2, 2	2013-04-02
Via Chain Testing Structure And Method App 20130034119 - Ireland; Philip J. ; et al.	2013-02-07
Via Structure App 20130026647 - Ireland; Philip J.	2013-01-31
Interconnect Regions App 20120326283 - Kirby; Kyle K. ; et al.	2012-12-27
Semiconductor Constructions Having Through-Substrate Interconnects, and Methods of Forming Through-Substrate Interconnects App 20120306084 - Wood; Alan G. ; et al.	2012-12-06
Microelectronic Devices With Through-silicon Vias And Associated Methods Of Manufacturing App 20120267786 - Kirby; Kyle K. ; et al.	2012-10-25
Interconnect regions Grant 8,283,785 - Kirby , et al. October 9, 2	2012-10-09
Interconnect Regions App 20120068348 - Kirby; Kyle K. ; et al.	2012-03-22
Self-aligned, Integrated Circuit Contact App 20110278738 - Ireland; Philip J.	2011-11-17
Sleeve Insulators And Semiconductor Device Including The Same App 20110254163 - Ireland; Philip J. ; et al.	2011-10-20
Trench Interconnect Structure And Formation Method App 20110212618 - Ireland; Philip J.	2011-09-01
Self-aligned, integrated circuit contact Grant 7,989,957 - Ireland August 2, 2	2011-08-02
Method of fabricating a sleeve insulator for a contact structure Grant 7,968,403 - Ireland , et al. June 28, 2	2011-06-28
Trench interconnect structure and formation method Grant 7,943,503 - Ireland May 17, 2	2011-05-17
Self-aligned, Integrated Circuit Contact App 20100096672 - Ireland; Philip J.	2010-04-22
Self-aligned, integrated circuit contact Grant 7,646,099 - Ireland January 12, 2	2010-01-12
Photolithography process using multiple anti-reflective coatings Grant 7,387,866 - Ireland , et al. June 17, 2	2008-06-17
Capacitance reduction by tunnel formation for use with a semiconductor device Grant 7,352,019 - Ireland April 1, 2	2008-04-01
Photolithographic structures using multiple anti-reflecting coatings Grant 7,250,247 - Ireland , et al. July 31, 2	2007-07-31
Method and apparatus for a deposited fill layer App 20070141774 - Ireland; Philip J. ; et al.	2007-06-21
Method and apparatus for a deposited fill layer Grant 7,196,394 - Ireland , et al. March 27, 2	2007-03-27
Method of making a contact structure App 20070004199 - Ireland; Philip J. ; et al.	2007-01-04
Trench interconnect structure and formation method Grant 7,138,719 - Ireland November 21, 2	2006-11-21
Method of making a contact structure Grant 7,115,506 - Ireland , et al. October 3, 2	2006-10-03
Trench Interconnect Structure And Formation Method App 20060189135 - Ireland; Philip J.	2006-08-24
Chemistry for chemical vapor deposition of titanium containing films Grant 7,033,939 - Sharan , et al. April 25, 2	2006-04-25
Fill pattern generation for spin-on glass and related self-planarization deposition Grant 7,026,717 - Juengling , et al. April 11, 2	2006-04-11
Capacitance reduction by tunnel formation for use with a semiconductor device App 20050233574 - Ireland, Philip J.	2005-10-20
Capacitance reduction by tunnel formation for use with a semiconductor device Grant 6,909,128 - Ireland June 21, 2	2005-06-21
Integrated circuit with modified metal features and method of fabrication therefor Grant 6,879,045 - Ireland April 12, 2	2005-04-12
Metal line layout of an integrated circuit Grant 6,867,498 - Ireland March 15, 2	2005-03-15
Chemistry for chemical vapor deposition of titanium containing films App 20050020067 - Sharan, Sujit ; et al.	2005-01-27
Creation of subresolution features via flow characteristics Grant 6,846,736 - Ireland January 25, 2	2005-01-25
Fill pattern generation for spin-on glass and related self-planarization deposition App 20050001322 - Juengling, Werner ; et al.	2005-01-06
Self-aligned, integrated circuit contact App 20040217484 - Ireland, Philip J.	2004-11-04
Fill pattern generation for spin-on glass and related self-planarization deposition Grant 6,812,138 - Juengling , et al. November 2, 2	2004-11-02
Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture Grant 6,812,512 - Prall , et al. November 2, 2	2004-11-02
Fill pattern generation for spin-on glass and related self-planarization deposition Grant 6,809,389 - Juengling , et al. October 26, 2	2004-10-26
Passivation integrity improvements Grant 6,806,576 - Ireland , et al. October 19, 2	2004-10-19
Fill pattern generation for spin-on glass and related self-planarization deposition Grant 6,806,577 - Juengling , et al. October 19, 2	2004-10-19
Subresolution features for a semiconductor device Grant 6,806,575 - Ireland October 19, 2	2004-10-19
Methods of forming conductive interconnects Grant 6,800,517 - Sandhu , et al. October 5, 2	2004-10-05
Metal line layout of an integrated circuit App 20040188679 - Ireland, Philip J.	2004-09-30
Integrated circuit with modified metal features and method of fabrication therefor App 20040185652 - Ireland, Philip J.	2004-09-23
Methods of forming conductive interconnects App 20040166622 - Sandhu, Gurtej S. ; et al.	2004-08-26
Self-aligned, integrated circuit contact and formation method Grant 6,780,762 - Ireland August 24, 2	2004-08-24
Chemistry for chemical vapor deposition of titanium containing films Grant 6,777,330 - Sharan , et al. August 17, 2	2004-08-17
Fill pattern generation for spin-on-glass and related self-planarization deposition Grant 6,777,813 - Juengling , et al. August 17, 2	2004-08-17
Fill pattern generation for spin-on glass and related self-planarization deposition App 20040157137 - Juengling, Werner ; et al.	2004-08-12
Fill pattern generation for spin-on glass and related self-planarization deposition App 20040157428 - Juengling, Werner ; et al.	2004-08-12
Fill pattern generation for spin-on glass and related self-planarization deposition App 20040155319 - Juengling, Werner ; et al.	2004-08-12
Method and apparatus for a deposited fill layer App 20040135227 - Ireland, Philip J. ; et al.	2004-07-15
Methods of forming conductive interconnects Grant 6,750,089 - Sandhu , et al. June 15, 2	2004-06-15
Contact structure for integrated circuit devices Grant 6,740,916 - Ireland , et al. May 25, 2	2004-05-25
Integrated circuit with modified metal features and method of fabrication therefor Grant 6,737,346 - Ireland May 18, 2	2004-05-18
Capacitance reduction by tunnel formation for use with a semiconductor device App 20040056323 - Ireland, Philip J.	2004-03-25
Self-aligned, integrated circuit contact and formation method App 20040041185 - Ireland, Philip J.	2004-03-04
Integrated circuit with modified metal features and method of fabrication therefor App 20040041263 - Ireland, Philip J.	2004-03-04
Trench interconnect structure and formation method App 20040041204 - Ireland, Philip J.	2004-03-04
Design Layout Method For Metal Lines Of An Integrated Circuit App 20040043591 - Ireland, Philip J.	2004-03-04
Design layout method for metal lines of an integrated circuit Grant 6,696,359 - Ireland February 24, 2	2004-02-24
Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture Grant 6,686,288 - Prall , et al. February 3, 2	2004-02-03
Expanded implantation of contact holes Grant 6,667,554 - Rhodes , et al. December 23, 2	2003-12-23
Method and apparatus for a deposited fill layer Grant 6,667,531 - Ireland , et al. December 23, 2	2003-12-23
Passivation integrity improvements App 20030205782 - Ireland, Philip J. ; et al.	2003-11-06
Expanded implantation of contact holes Grant 6,632,727 - Rhodes , et al. October 14, 2	2003-10-14
Capacitance reduction by tunnel formation for use with semiconductor device Grant 6,627,529 - Ireland September 30, 2	2003-09-30
Fill pattern generation for spin-on glass and related self-planarization deposition App 20030168741 - Juengling, Werner ; et al.	2003-09-11
Photolithography process using multiple anti-reflective coatings App 20030155626 - Ireland, Philip J. ; et al.	2003-08-21
Subresolution features for a semiconductor device App 20030151142 - Ireland, Philip J.	2003-08-14
Capacitance Reduction By Tunnel Formation For Use With Semiconductor Device App 20030146513 - Ireland, Philip J.	2003-08-07
Methods of forming conductive interconnects App 20030119244 - Sandhu, Gurtej S. ; et al.	2003-06-26
Creation of subresolution features via flow characteristics App 20030003708 - Ireland, Philip J.	2003-01-02
Chemistry for chemical vapor deposition of titanium containing films App 20020132475 - Sharan, Sujit ; et al.	2002-09-19
Method of making a contact structure App 20020081841 - Ireland, Philip J. ; et al.	2002-06-27
Passivation integrity improvements App 20020045335 - Ireland, Philip J. ; et al.	2002-04-18
Photolithography process using multiple anti-reflective coatings App 20020039820 - Ireland, Philip J. ; et al.	2002-04-04
Passivation integrity improvements Grant 6,358,862 - Ireland , et al. March 19, 2	2002-03-19
Method of making a contact structure Grant 6,348,411 - Ireland , et al. February 19, 2	2002-02-19
Chemistry For Chemical Vapor Deposition Of Titanium Containing Films App 20020013050 - SHARAN, SUJIT ; et al.	2002-01-31
Expanded implantation of contact holes App 20020009879 - Rhodes, Howard E. ; et al.	2002-01-24
Expanded implantation of contact holes App 20020001942 - Rhodes, Howard E. ; et al.	2002-01-03
Method of forming DRAM trench capacitor with metal layer over hemispherical grain polysilicon Grant 6,291,289 - Rhodes , et al. September 18, 2	2001-09-18
Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture App 20010019893 - Prall, Kirk ; et al.	2001-09-06
Process for forming trenches and contacts during the formation of a semiconductor memory device App 20010014525 - Ireland, Philip J.	2001-08-16
Method Of Forming Dram Trench Capacitor With Metal Layer Over Hemispherical Grain Polysilicon App 20010012656 - RHODES, HOWARD E. ; et al.	2001-08-09
Creation of subresolution features via flow characteristics App 20010002072 - Ireland, Philip J.	2001-05-31
Capacitor Structures App 20010001210 - Rhodes, Howard E. ; et al.	2001-05-17
Contact formation using two anneal steps Grant 6,110,789 - Rhodes , et al. August 29, 2	2000-08-29
Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture Grant 5,990,021 - Prall , et al. November 23, 1	1999-11-23
Polysilicon pillar diode for use in a non-volatile memory cell Grant 5,751,012 - Wolstenholme , et al. May 12, 1	1998-05-12
Double mask process for forming trenches and contacts during the formation of a semiconductor memory device Grant 5,466,639 - Ireland November 14, 1	1995-11-14

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