Integrated circuit tag

Description

FIG. 1 is a perspective view of an integrated circuit tag showing our new design;

FIG. 2 is a front elevational view thereof;

FIG. 3 is a right side elevational view thereof;

FIG. 4 is a left side elevational view thereof;

FIG. 5 is a top plan view thereof; and

FIG. 6 is a bottom plan view thereof.

FIG. 7 is a reference front elevational view thereof;

FIG. 8 is a reference rear elevational view thereof;

FIG. 9 is a cross sectional view thereof cut along the line 9-9 of FIG. 7; and,

FIG. 10 is a reference rear elevational view thereof showing the translucent portion in gray.

The broken lines shown in the drawings represent portions of the integrated circuit tag that form no part of the claimed design.

Claims

CLAIM The ornamental design for an integrated circuit tag, as shown and described.

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Inventors:	Nakano; Tomoko (Kanagawa, JP), Fujisawa; Naohiro (Kanagawa, JP), Miyajima; Keiichi (Kanagawa, JP)
Applicant:	Name City State Country Type NOK CORPORATION Tokyo N/A JP
Assignee:	NOK Corporation (Tokyo, JP)
Appl. No.:	D/489,647
Filed:	May 1, 2014

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Foreign Application Priority Data

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Nov 5, 2013 [JP]			D2013-025852

Current U.S. Class:	D13/182
Current International Class:	1303
Field of Search:	;D13/110,123,133,182,199 ;D11/213,222 ;D20/22,28

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References Cited [Referenced By]

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Foreign Patent Documents

	2009-116633		May 2009		JP

Primary Examiner: Oswecki; Elizabeth J
Attorney, Agent or Firm: Michael Best & Friedrich LLP