Integrated circuit tag
Ishii September 26, 2
U.S. patent number D529,000 [Application Number D/201,582] was granted by the patent office on 2006-09-26 for integrated circuit tag. This patent grant is currently assigned to Riso Kagaku Corporation. Invention is credited to Hiroaki Ishii.
| United States Patent | D529,000 |
| Ishii | September 26, 2006 |
Integrated circuit tag
Claims
CLAIM The ornamental design for an integrated circuit tag, as shown and described.
| Inventors: | Ishii; Hiroaki (Ibaraki-ken, JP) |
|---|---|
| Assignee: | Riso Kagaku Corporation (Tokyo,
JP) |
| Appl. No.: | D/201,582 |
| Filed: | March 18, 2004 |
Foreign Application Priority Data
| Sep 18, 2003 [JP] | 2003-027209 | |||
| Current U.S. Class: | D13/182 |
| Current International Class: | 1303 |
| Field of Search: | ;D13/182 ;257/E27.114,E27.001 ;340/5.91,572.1,825.49 ;361/314,766,776,777 ;365/154 |
References Cited [Referenced By]
U.S. Patent Documents
| 4797785 | January 1989 | Jorgensen |
| D359476 | June 1995 | Sakashita et al. |
| 6072394 | June 2000 | Hasegawa et al. |
| 6091607 | July 2000 | McKeown et al. |
| 6327168 | December 2001 | Campbell |
| 6835412 | December 2004 | Burke |
| 2005/0183817 | August 2005 | Eckstein et al. |
Assistant Examiner: Sikder; Selina
Attorney, Agent or Firm: Frommer Lawrence & Haug LLP Ryan, Esq.; Matthew K.
Description
FIG. 1 is a front elevational view of and integrated circuit tag showing my new design;
FIG. 2 is a is top plan view thereof;
FIG. 3 is a left side elevational view thereof;
FIG. 4 is a right side elevational view thereof;
FIG. 5 is a rear elevational view thereof; and,
FIG. 6 is a bottom plan view thereof;
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