Arm for wafer transportation for manufacturing semiconductor

Description

FIG. 1 is perspective view of an arm for wafer transportation for manufacturing semiconductor showing our new design;

FIG. 2 is a top plan view thereof;

FIG. 3 is a bottom plan view thereof;

FIG. 4 is a front view thereof;

FIG. 5 is a rear view thereof;

FIG. 6 is a left side view thereof, the right side view being a mirror image;

FIG. 7 is an enlarged sectional view taken along line 7-7 of FIG. 2; and,

FIG. 8 is an enlarged sectional view taken along line 8-8 of FIG. 2.

The broken lines shown in the drawings represent portions of the arm for wafer transportation for manufacturing semiconductor that form no part of the claimed design.

Claims

CLAIM The ornamental design for arm for wafer transportation for manufacturing semiconductor, as shown and described.

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Inventors:	Iida; Naruaki (Koshi, JP), Kajiwara; Hideki (Koshi, JP)
Applicant:	Name City State Country Type Iida; Naruaki Kajiwara; Hideki Koshi Koshi N/A N/A JP JP
Assignee:	Tokyo Electron Limited (Minato-Ku, JP)
Appl. No.:	D/414,723
Filed:	March 2, 2012

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Foreign Application Priority Data

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Oct 20, 2011 [JP]			2011-024076

Current U.S. Class:	D13/182
Current International Class:	1303
Field of Search:	;D13/182 ;118/500,725,728,729 ;294/103.1 ;414/217,222.01,416.03,941

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References Cited [Referenced By]

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U.S. Patent Documents

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Primary Examiner: Oswecki; Elizabeth J
Attorney, Agent or Firm: Burr & Brown, PLLC