Baffle plate for manufacturing semiconductor

Description

FIG. 1 is a front view of a baffle plate of the present invention.

FIG. 2 is a rear view of the baffle plate of FIG. 1.

FIG. 3 is a top plan view of the baffle plate of FIG. 1.

FIG. 4 is a bottom view of the baffle plate of FIG. 1.

FIG. 5 is a right side view of the baffle plate of FIG. 1.

FIG. 6 is a left view of the baffle plate of FIG. 1.

FIG. 7 is a first perspective view of the baffle plate of FIG. 1.

FIG. 8 is a second perspective view of the baffle plate of FIG. 1; and,

FIG. 9 is a view of the baffle plate of FIG. 1 in use, wherein, for example, in a plasma processing device, gas entering a chamber is ionized, and a wafer is treated by an etching process with ions, and gas is exhausted from the chamber.

The features shown in broken lines depict environmental subject matter only and form no part of the claimed design.

Claims

CLAIM The ornamental design for a baffle plate for manufacturing semiconductor, as shown and described.

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Inventors:	Matsumoto; Naoki (Sendai, JP), Yoshikawa; Jun (Sendai, JP)
Applicant:	Name City State Country Type Matsumoto; Naoki Yoshikawa; Jun Sendai Sendai N/A N/A JP JP
Assignee:	Tokyo Electron Limited (Tokyo, JP)
Appl. No.:	D/416,082
Filed:	March 19, 2012

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Foreign Application Priority Data

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Sep 20, 2011 [JP]			D2011-021502

Current U.S. Class:	D15/144; D15/138
Current International Class:	1599
Field of Search:	;D13/182 ;D15/138,144,199 ;118/723 ;156/345,345.36,345.41,345.48 ;204/298.06,298.08,298.11,298.34 ;336/232

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References Cited [Referenced By]

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Other References

Notice of Allowance, Taiwanese Design Application No. 101301467, dated Jun. 26, 2012. cited by applicant.

Primary Examiner: Palasik; Patricia
Attorney, Agent or Firm: Leydig, Voit & Mayer Ltd.