Semiconductor device

Iwasaki , et al. February 25, 2

Patent Grant D470825

U.S. patent number D470,825 [Application Number D/159,531] was granted by the patent office on 2003-02-25 for semiconductor device. This patent grant is currently assigned to Mitsubishi Denki Kabushiki Kaisha. Invention is credited to Toru Iwagami, Mitsutaka Iwasaki, Hisashi Kawafuji.


United States Patent D470,825
Iwasaki ,   et al. February 25, 2003

Semiconductor device

Claims

The ornamental design for a semiconductor device, as shown and described.
Inventors: Iwasaki; Mitsutaka (Tokyo, JP), Iwagami; Toru (Tokyo, JP), Kawafuji; Hisashi (Fukuoka, JP)
Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP)
Appl. No.: D/159,531
Filed: April 24, 2002

Foreign Application Priority Data

Dec 28, 2001 [JP] 2001-038794
Dec 28, 2001 [JP] 2001-038795
Current U.S. Class: D13/182
Current International Class: 1303
Field of Search: ;D13/182 ;174/16.3,52.1,52.2,52.4 ;257/670,672,676,686,688,690-696,703,787 ;361/736,742,748,752,760,761,774,783,784,785,798,813,820

References Cited [Referenced By]

U.S. Patent Documents
5221859 June 1993 Kobayashi et al.
D357462 April 1995 Terasawa et al.
D357671 April 1995 Terasawa et al.
D360619 July 1995 Terasawa et al.
D394244 May 1998 Majumdar et al.
5757070 May 1998 Fritz
D401912 December 1998 Majumdar et al.
5877548 March 1999 Washida et al.
D421969 March 2000 Kawafuji et al.
D448739 October 2001 Iwasaki et al.
D459705 July 2002 Yokota et al.
Primary Examiner: Shooman; Ted
Assistant Examiner: Sikder; Selina
Attorney, Agent or Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.

Description



FIG. 1 is a front, top and right side perspective view of a semiconductor device, showing our new design;

FIG. 2 is a front, bottom and right side perspective view thereof;

FIG. 3 is a front elevational view thereof;

FIG. 4 is a rear elevational view thereof;

FIG. 5 is a top plan view thereof;

FIG. 6 is a bottom plan view thereof;

FIG. 7 is a right side elevational view thereof;

FIG. 8 is a left side elevational view thereof;

FIG. 9 is a cross-sectional view thereof, taken along line 9--9 of FIG. 5, with the internal system omitted;

FIG. 10 is a cross-sectional view thereof, taken along line 10--10 of FIG. 5, with the internal system omitted;

FIG. 11 is a front, top and right side perspective view of a second embodiment of the semiconductor device, showing our new design;

FIG. 12 is a front, bottom and right side perspective view thereof;

FIG. 13 is a front elevational view thereof;

FIG. 14 is a rear elevational view thereof;

FIG. 15 is a top plan view thereof;

FIG. 16 is a bottom plan view thereof;

FIG. 17 is a right side elevational view thereof;

FIG. 18 is a left side elevational view thereof;

FIG. 19 is a cross-sectional view thereof, taken along line 19--19 of FIG. 15, with the internal system omitted; and,

FIG. 20 is a cross-sectional view thereof, taken along line 20--20 of FIG. 15, with the internal system omitted.

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