Semiconductor package

Yokota , et al. July 2, 2

Patent Grant D459705

U.S. patent number D459,705 [Application Number D/142,698] was granted by the patent office on 2002-07-02 for semiconductor package. This patent grant is currently assigned to Shindengen Electric Manufacturing Co., Ltd.. Invention is credited to Yoshio Yokota, Nobuyuki Yokote.


United States Patent D459,705
Yokota ,   et al. July 2, 2002

Semiconductor package

Claims

The ornamental design for a semiconductor package, as shown and described.
Inventors: Yokota; Yoshio (Hanno, JP), Yokote; Nobuyuki (Hanno, JP)
Assignee: Shindengen Electric Manufacturing Co., Ltd. (Tokyo, JP)
Appl. No.: D/142,698
Filed: June 1, 2001

Foreign Application Priority Data

Mar 6, 2001 [JP] 2001-005455
Current U.S. Class: D13/182
Current International Class: 1303
Field of Search: ;D13/182 ;D14/114 ;174/52.1,52.2,52.4,52.5,16.3 ;206/710,719 ;257/254,659,697,730,738 ;324/755,765 ;361/752,798,820,718,730

References Cited [Referenced By]

U.S. Patent Documents
3602846 August 1971 Hauser
3846734 November 1974 Pauza et al.
4391408 July 1983 Hanlon et al.
4441119 April 1984 Link
D288922 March 1987 Olla
4951122 August 1990 Tsubosaki et al.
4979016 December 1990 Lee
4987474 January 1991 Yasuhara et al.
D317592 June 1991 Yoshizawa
5337216 August 1994 McIver
5387814 February 1995 Baudouin et al.
D357901 May 1995 Horman
5539250 July 1996 Kitano et al.
5646443 July 1997 Takahashi
D401567 November 1998 Farnworth et al.
D401912 December 1998 Majumdar et al.
5959842 September 1999 Leonard et al.
6018191 January 2000 Murakami et al.
6303982 October 2001 Murakami et al.

Other References

Japanese Design Application No. 929231, Publication Date: Jul. 6, 1995. .
Japanese Design Application No. 982886--Similar 1, Publication Date: Jun. 24, 1997. .
Japanese Design Application No. 982886, Publication Date: Jun. 17, 1997..

Primary Examiner: Shooman; Ted
Assistant Examiner: Sikder; Selina
Attorney, Agent or Firm: Antonelli, Terry, Stout & Kraus, LLP

Description



FIG. 1 is a front, plan and right side perspective view of a semiconductor package showing our new design;

FIG. 2 is a front elevational view thereof;

FIG. 3 is a rear elevational view thereof;

FIG. 4 is a top plan view thereof;

FIG. 5 is a bottom plan view thereof;

FIG. 6 is a left side elevational view thereof; and,

FIG. 7 is a right side elevational view thereof.

The broken lines are shown in the views for illustrative purposes only and form no part of the claimed design.

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