U.S. patent number 7,855,454 [Application Number 11/702,286] was granted by the patent office on 2010-12-21 for semiconductor device structures including nickel plated aluminum, copper, and tungsten structures.
This patent grant is currently assigned to Micron Technology, Inc.. Invention is credited to Salman Akram, William M. Hiatt, James M. Wark.
United States Patent |
7,855,454 |
Akram , et al. |
December 21, 2010 |
Semiconductor device structures including nickel plated aluminum,
copper, and tungsten structures
Abstract
A method of activating a metal structure on an intermediate
semiconductor device structure toward metal plating. The method
comprises providing an intermediate semiconductor device structure
comprising at least one first metal structure and at least one
second metal structure on a semiconductor substrate. The at least
one first metal structure comprises at least one aluminum
structure, at least one copper structure, or at least one structure
comprising a mixture of aluminum and copper and the at least one
second metal structure comprises at least one tungsten structure.
One of the at least one first metal structure and the at least one
second metal structure is activated toward metal plating without
activating the other of the at least one first metal structure and
the at least one second metal structure. An intermediate
semiconductor device structure is also disclosed.
Inventors: |
Akram; Salman (Boise, ID),
Wark; James M. (Boise, ID), Hiatt; William M. (Eagle,
ID) |
Assignee: |
Micron Technology, Inc. (Boise,
ID)
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Family
ID: |
35241013 |
Appl.
No.: |
11/702,286 |
Filed: |
February 5, 2007 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20070132105 A1 |
Jun 14, 2007 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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10934635 |
Oct 9, 2007 |
7279407 |
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Current U.S.
Class: |
257/750;
257/E23.158; 438/687; 257/765; 257/763; 257/764; 438/686; 438/685;
257/762; 257/E23.161; 257/766; 438/656; 438/648 |
Current CPC
Class: |
C23C
18/1831 (20130101); H01L 21/288 (20130101); H01L
21/76879 (20130101); C23C 18/1637 (20130101); C23C
18/1834 (20130101); C23C 18/1607 (20130101); H01L
21/76898 (20130101); Y10T 428/24917 (20150115); C23C
18/36 (20130101); Y10T 428/12528 (20150115); H01L
2924/00013 (20130101); C23C 18/34 (20130101); H01L
2924/00013 (20130101); H01L 2224/29099 (20130101) |
Current International
Class: |
H01L
23/48 (20060101); H01L 29/40 (20060101); H01L
23/52 (20060101) |
Field of
Search: |
;257/E21.009,E21.021,E21.168,E21.647,E21.332,E21.597,E23.011,686,723,774,705,621,750-752,762-764,766,770,E23.161,E23.158
;438/3,240,648,565,667,637 ;216/18,105,41
;174/257,258,255,260,262-266 ;27/846 ;361/790,792 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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0455915 |
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Nov 1991 |
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EP |
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WO-03/019651 |
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Mar 2003 |
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WO |
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Other References
International Search Report for International Application No.
PCT/US2005/030228, dated Jul. 12, 2007 (6 pages). cited by other
.
Law et al., "The Effect of Passivation Defect on Electroless Nickel
Under Bump Metallization Plating Process," www.ee.vst.hk/
--flipchip/ctu.sub.--simon.doc. cited by other.
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Primary Examiner: Gurley; Lynne A
Assistant Examiner: Li; Meiya
Attorney, Agent or Firm: TraskBritt
Parent Case Text
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a divisional of application Ser. No.
10/934,635, filed Sep. 2, 2004, now U.S. Pat. No. 7,279,407, issued
Oct. 9, 2007, and is also related to application Ser. No.
11/516,193, filed Sep. 6, 2006, now abandoned. The disclosure of
each of the previously referenced U.S. patent applications is
hereby incorporated by reference in its entirety.
Claims
What is claimed is:
1. An intermediate semiconductor device structure, comprising: a
semiconductor substrate comprising at least one structure formed
from aluminum or copper and at least one via extending through the
at least one structure formed from aluminum or copper and into the
semiconductor substrate, sidewalls of the at least one via lined
with an oxide material, a tungsten material, and a first nickel
material wherein a first surface of each of the oxide material, the
tungsten material, and the first nickel material is co-planar with
a first surface of the at least one structure formed from aluminum
or copper; and a second nickel material on the at least one
structure formed from aluminum or copper, wherein the second nickel
material is discontiguous with the first nickel material.
2. The intermediate semiconductor device structure of claim 1,
wherein the at least one structure formed from aluminum or copper
comprises at least one aluminum bond pad or at least one copper
bond pad.
3. The intermediate semiconductor device structure of claim 1,
wherein the oxide material, the tungsten material, and the first
nickel material extend from the first surface of the at least one
structure formed from aluminum or copper through the at least one
via.
4. The intermediate semiconductor device structure of claim 3,
wherein the at least one via lined with the oxide material, the
tungsten material, and the first nickel material comprises a
through-wafer-interconnect wherein a second surface of each of the
oxide material, the tungsten material, and the first nickel
material is co-planar with a second surface of the semiconductor
substrate.
5. The intermediate semiconductor device structure of claim 3,
wherein the at least one via lined with the oxide material, the
tungsten material, and the first nickel material comprises a
blind-wafer-interconnect having the oxide material, the tungsten
material, and the first nickel material therewithin.
6. The intermediate semiconductor device structure of claim 1,
wherein at least one of the first nickel material and the second
nickel material is formed by formulating a nickel plating chemistry
selective for one of the at least one structure formed from
aluminum or copper and the tungsten material in the at least one
via.
7. The intermediate semiconductor device structure of claim 6,
wherein the nickel plating chemistry selective for the at least one
structure formed from aluminum or copper comprises an aluminum
activator or copper activator and an electroless nickel plating
solution.
8. The intermediate semiconductor device structure of claim 7,
wherein the aluminum activator or copper activator comprises an
aqueous zincate solution comprising zinc oxide and sodium
hydroxide.
9. The intermediate semiconductor device structure of claim 7,
wherein the electroless nickel plating solution comprises a nickel
salt selected from the group consisting of nickel sulfite, nickel
chloride, nickel sulfate, nickel bromide, nickel fluoroborate,
nickel sulfonate, nickel sulfamate, and nickel alkyl sulfonate and
a reducing agent selected from the group consisting of sodium
hypophosphite, dimethylamine borane, sodium borohydride, and
dimethylaminobenzaldehyde.
10. The intermediate semiconductor device structure of claim 6,
wherein the nickel plating chemistry selective for the at least one
via lined with the oxide material, the tungsten material, and the
first nickel material comprises a tungsten activator and an
electroless nickel plating solution.
11. The intermediate semiconductor device structure of claim 10,
wherein the electroless nickel plating solution comprises a nickel
salt selected from the group consisting of nickel sulfite, nickel
chloride, nickel sulfate, nickel bromide, nickel fluoroborate,
nickel sulfonate, nickel sulfamate, and nickel alkyl sulfonate and
a reducing agent selected from the group consisting of sodium
hypophosphite, dimethylamine borane, sodium borohydride, and
dimethylaminobenzaldehyde.
12. The intermediate semiconductor device structure of claim 10,
wherein the tungsten activator comprises an aqueous solution of
palladium (II) ions.
13. An intermediate semiconductor device structure, comprising: at
least one bond pad on a semiconductor substrate, the at least one
bond pad formed from at least one of aluminum and copper; at least
one via partially filled with an oxide material and a metal
consisting of tungsten, the oxide material in direct contact with
sidewalls of the semiconductor substrate and sidewalls of the at
least one bond pad, and the metal consisting of tungsten in direct
contact with the oxide material, wherein the oxide material and the
metal consisting of tungsten extend through the at least one bond
pad and at least partially into the semiconductor substrate; a
first nickel material in contact with at least a portion of the at
least one bond pad; and a second nickel material in the at least
one via, the second nickel material discontiguous with the first
nickel material and in direct contact with the metal consisting of
tungsten.
14. The intermediate semiconductor device structure of claim 13,
further comprising another oxide material overlying a surface of
the semiconductor substrate and underlying the at least one bond
pad.
15. The intermediate semiconductor device structure of claim 13,
further comprising solder in the at least one via.
16. An intermediate semiconductor device structure, comprising: at
least one metal structure on a semiconductor substrate, the at
least one metal structure comprising aluminum, copper, or a
combination of aluminum and copper; a first nickel material
overlying the at least one metal structure; at least one via
extending through the at least one metal structure and into the
semiconductor substrate; an oxide material within the at least one
via and overlying a sidewall of the at least one metal structure
and a sidewall of the semiconductor substrate; at least one
structure consisting of tungsten within the at least one via and
overlying the oxide material; and a second nickel material within
the at least one via, the second nickel material overlying the at
least one structure consisting of tungsten and discontiguous with
the first nickel material, wherein the second nickel material, the
at least one structure consisting of tungsten, and the oxide
material partially fill the at least one via and are parallel to
sidewalls of the at least one via.
17. The intermediate semiconductor device structure of claim 16,
wherein the at least one metal structure comprises a bond pad.
18. The intermediate semiconductor device structure of claim 16,
wherein the at least one structure consisting of tungsten comprises
the at least one via extending at least partially through the
semiconductor substrate, the at least one via partially filled with
tungsten.
19. The intermediate semiconductor device structure of claim 16,
further comprising solder in the at least one via.
20. An intermediate semiconductor device structure, comprising: a
semiconductor substrate comprising at least one structure formed
from aluminum or copper and at least one via lined with a tungsten
material, the at least one via and the tungsten material extending
through the at least one structure formed from aluminum or copper
and into the semiconductor substrate; a first nickel material on
the at least one structure formed from aluminum or copper; and a
second nickel material overlying the tungsten material and
discontiguous with the first nickel material, the second nickel
material and the tungsten material partially filling the at least
one via.
21. The intermediate semiconductor device structure of claim 20,
wherein solder fills the at least one via.
Description
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to semiconductor fabrication. More
specifically, the present invention relates to a method of
selectively plating aluminum, copper, or tungsten structures with
nickel.
Semiconductor devices that have integrated circuits are produced by
fabricating a large plurality of identical circuit patterns on a
semiconductor wafer using photolithography in combination with
various other processes. It is a continual goal of semiconductor
manufacturers to increase the density of semiconductor devices
fabricated on a given size of semiconductor substrate to achieve
increased yield of semiconductor devices and enhanced performance
thereof. In recent years, efforts to increase the density of
semiconductor devices in a semiconductor assembly have also
intensified. One way to increase the density of semiconductor
devices in a semiconductor assembly is to stack semiconductor dies
upon one another. The semiconductor dies are interconnected by
forming vias or through holes in the semiconductor dies. The vias
are filled with an electrically conductive material to electrically
connect the vias to integrated circuitry fabricated on an active
surface of the semiconductor die. Thus, the vias provide a
conductive pathway from the active surface of the semiconductor die
to its respective back surface, enabling interconnection of the
back surface of the semiconductor die to external electrical
contacts of another semiconductor die or a carrier substrate. The
vias are formed by etching, laser ablation or drilling, or a
combination thereof. Etching the vias utilizes photolithographic
processing of a photoresist followed by wet (chemical) or dry
(reactive ion) etching. Laser drilling has been used to form vias
by ablating semiconductor material to form through holes extending
through the entire thickness of a semiconductor die.
The vias electrically interconnect various metal interconnection
structures on the semiconductor die, such as annular rings, bond
pads, component leads, metal wires, or other metal layers, to one
another. Bond pads on the semiconductor dies are typically formed
from aluminum, copper, or aluminum-copper alloys having less than
about 0.5% copper. Aluminum is used in bond pads because of its low
resistivity, superior adhesion qualities, high thermal stability,
and ease of workability. However, one disadvantage of aluminum is
that it readily oxidizes to form aluminum oxides, which decrease
quality of the electrical connection and the efficiency of the bond
pads. To protect the bond pads, the aluminum is etched to remove
the aluminum oxides and covered with a barrier metal, such as a
nickel layer. Tungsten is also commonly used as an interconnection
material because it has a thermal expansion coefficient that is
similar to that of silicon and has a good filling capability in
semiconductor structures with high aspect ratios. Tungsten is
typically used to fill or line a surface of an opening produced
during formation of a via. The tungsten lining in the via is
subsequently covered with a metal layer, such as a nickel layer.
The bond pads are typically nickel plated after vias have been
plated with nickel because etchants used to remove the aluminum
oxides also remove nickel plating from inside the vias.
BRIEF SUMMARY OF THE INVENTION
The present invention relates to a method of selectively plating
nickel on an intermediate semiconductor device structure. The
method comprises providing an intermediate semiconductor device
structure comprising at least one aluminum or copper structure and
at least one tungsten structure on a semiconductor substrate. One
of the at least one aluminum or copper structure and the at least
one tungsten structure is nickel plated while the other of the at
least one aluminum or copper structure and the at least one
tungsten structure remains unplated. The nickel may be plated
electrolessly. The at least one aluminum or copper structure may be
at least one aluminum or copper bond pad and the at least one
tungsten structure may be at least one via having a layer of
tungsten therewithin. In one embodiment, the at least one aluminum
or copper bond pad may be nickel plated while the at least one via
having a layer of tungsten therewithin remains unplated. In another
embodiment, the at least one via having a layer of tungsten
therewithin may be plated with nickel while the at least one
aluminum or copper bond pad remains unplated.
One of the at least one aluminum or copper structure and the at
least one tungsten structure may be plated while the other remains
unplated by selecting a nickel plating chemistry selective for one
of aluminum, copper, and tungsten. To nickel plate one of the at
least one aluminum or copper structure and the at least one
tungsten structure while the other remains unplated, one of the at
least one aluminum or copper structure and the at least one
tungsten structure may be activated toward nickel plating. The at
least one aluminum or copper structure may be activated by exposing
the intermediate semiconductor device structure to a zincate
solution. The zincate solution may be an aqueous solution
comprising zinc oxide and sodium hydroxide. The at least one
tungsten structure may be activated toward nickel plating by
exposing the intermediate semiconductor device structure to a
palladium solution. The palladium solution may be an aqueous
solution comprising palladium (II) ions.
The activated one of the at least one aluminum or copper structure
and the at least one tungsten structure may be nickel plated by
immersing the intermediate semiconductor device structure in an
electroless nickel plating solution that comprises a nickel salt
selected from the group consisting of nickel sulfite, nickel
chloride, nickel sulfate, nickel bromide, nickel fluoroborate,
nickel sulfonate, nickel sulfamate, and nickel alkyl sulfonate and
a reducing agent selected from the group consisting of sodium
hypophosphite, dimethylamine borane, sodium borohydride, and
dimethylaminobenz-aldehyde ("DMAB"). The unplated one of the at
least one aluminum or copper structure and the at least one
tungsten structure may subsequently be nickel plated by activating
the unplated structure and then nickel plating the activated
structure.
The present invention also relates to an intermediate semiconductor
device structure that comprises a semiconductor substrate
comprising at least one aluminum or copper structure and at least
one tungsten structure. One of the at least one aluminum or copper
structure and the at least one tungsten structure is plated with
nickel while the other of the at least one aluminum or copper
structure and the at least one tungsten structure remains unplated.
The at least one aluminum or copper structure may be at least one
aluminum or copper bond pad and the at least one tungsten structure
may be at least one via having a layer of tungsten therewithin. The
at least one via having a layer of tungsten therewithin may be a
through-wafer-interconnect or a blind-wafer-interconnect.
The present invention also relates to an intermediate semiconductor
device structure that comprises a semiconductor substrate
comprising at least one aluminum or copper structure having a first
nickel layer plated thereon and at least one tungsten structure
having a second nickel layer plated thereon. At least one of the
first nickel layer and the second nickel layer is formed by
formulating a nickel plating chemistry selective for one of the at
least one aluminum or copper structure and the at least one
tungsten structure. The at least one aluminum or copper structure
may be at least one aluminum or copper bond pad and the at least
one tungsten structure may be at least one via having a layer of
tungsten therewithin. The at least one via having a layer of
tungsten therewithin may be a through-wafer-interconnect or a
blind-wafer-interconnect.
The nickel plating chemistry selective for the at least one
aluminum or copper structure may include an aluminum or copper
activator and an electroless nickel plating solution. The aluminum
or copper activator may be a zincate solution, as previously
described, and the electroless nickel plating solution may be as
previously described. The nickel plating chemistry selective for
the at least one tungsten structure may include a tungsten
activator and an electroless nickel plating solution. The tungsten
activator may be a palladium solution, as previously described, and
the electroless nickel plating solution may be as previously
described.
The present invention also relates to a method of plating nickel on
an intermediate semiconductor device structure. The method
comprises providing an intermediate semiconductor device structure
comprising at least one aluminum or copper structure and at least
one tungsten structure on a semiconductor substrate. The at least
one aluminum or copper structure and the at least one tungsten
structure are simultaneously plated with nickel. The at least one
aluminum or copper structure and the at least one tungsten
structure may be nickel plated by activating a surface of the at
least one aluminum or copper structure and the at least one
tungsten structure. To activate the surface of the at least one
aluminum or copper structure, the intermediate semiconductor device
structure may be exposed to a zincate solution, as previously
described. To activate the surface of the at least one tungsten
structure, the intermediate semiconductor device structure may be
exposed to a palladium solution, as previously described. The
activated, at least one aluminum or copper structure and the
activated, at least one tungsten structure are simultaneously
plated with nickel by immersing the intermediate semiconductor
device structure in an electroless nickel plating solution, as
described above.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
While the specification concludes with claims particularly pointing
out and distinctly claiming that which is regarded as the present
invention, the advantages of this invention may be more readily
ascertained from the following description of the invention when
read in conjunction with the accompanying drawings in which:
FIGS. 1, 3-8, 10, 12, 14, and 16 schematically illustrate a cross
sectional view of one embodiment of an integrated circuit in which
a through-wafer-interconnect is formed;
FIGS. 17-20 schematically illustrate a cross sectional view of
another embodiment of an integrated circuit in which a
through-wafer-interconnect is formed; and
FIGS. 2, 9, 11, 13, and 15 schematically illustrate a cross
sectional view of an embodiment of an integrated circuit in which a
blind-wafer-interconnect is formed.
DETAILED DESCRIPTION OF THE INVENTION
A method of selectively plating nickel on either an aluminum
structure or a tungsten structure present on a semiconductor
substrate is disclosed. The semiconductor substrate includes both
the aluminum structure and the tungsten structure. In one
embodiment, the aluminum structure is plated with nickel without
depositing nickel on the tungsten structure. The aluminum structure
is nickel plated with a nickel plating chemistry that is selective
for aluminum. As used herein, the term "nickel plating chemistry"
includes chemistries that are used to clean the structures,
activate the structures, or plate the structures with nickel. In
another embodiment, the tungsten structure may be plated with
nickel without nickel plating the aluminum structure utilizing a
nickel plating chemistry that is selective for tungsten. In another
embodiment, the tungsten structure and the aluminum structure may
be substantially simultaneously plated with nickel.
The nickel may be deposited on either the aluminum structure or the
tungsten structure by electroless plating. To deposit the nickel,
either the aluminum structure or the tungsten structure may be
activated toward nickel plating by exposing the structures to an
activator that is selective for either aluminum or tungsten. For
instance, if the aluminum structure is to be nickel plated, the
activator may be selective for aluminum. Conversely, if the
tungsten structure is to be nickel plated, the activator may be
selective for tungsten. A surface of the activated structure may
then be plated with nickel while a surface of the unactivated
structure remains unplated. The unplated surface may subsequently
be plated with nickel by exposing the structures to a different
nickel plating chemistry, such as a different activator, that is
selective for the unplated surface. Once activated, the unplated
surface may be nickel plated.
By exposing the structures to the activator selective for aluminum
or tungsten, the aluminum structure or the tungsten structure may
be activated and plated with nickel while the unactivated structure
remains unplated. For instance, if the structures are exposed to an
activator that is selective for aluminum, nickel may be
electrolessly plated on the aluminum structure without nickel
plating the tungsten structure. After nickel plating the aluminum
structure, nickel may be plated on the tungsten structure using a
different nickel plating chemistry. Similarly, if the structures
are exposed to an activator that is selective for tungsten, nickel
may be electrolessly plated on the tungsten structure without
plating the aluminum structure. Nickel may subsequently be plated
on the aluminum structure using a different nickel plating
chemistry.
While the embodiments disclosed herein describe that the aluminum
structure is an aluminum bond pad and the tungsten structure is a
tungsten-lined via, the present invention may also be used to
selectively plate nickel on additional aluminum or tungsten
structures.
The nickel may be selectively plated on an intermediate
semiconductor device structure 2 that has at least one aluminum
structure and at least one tungsten structure. The tungsten
structure may be a via 4 lined with tungsten and the aluminum
structure may be a bond pad 6, as shown in FIGS. 1 and 2. As used
herein, the term "via" refers to an opening in a semiconductor
substrate 8 that is subsequently filled or lined with a conductive
material to provide a conductive pathway through the semiconductor
substrate 8. For the sake of clarity, one via 4 and two bond pads 6
are shown in FIGS. 1 and 2. However, the intermediate semiconductor
device structure 2 may include a plurality of vias 4 and a
plurality of bond pads 6. The via 4 and the bond pads 6 may both be
present on an exterior or exposed surface of the intermediate
semiconductor device structure 2 and, as such, may both be exposed.
The bond pad 6 may be formed on the semiconductor substrate 8 from
a conductive metal, such as aluminum, by conventional techniques.
The bond pad 6 may have a thickness ranging from approximately 1.0
.mu.m to approximately 1.5 .mu.m. The via 4 may be filled or lined
with the conductive material to provide the conductive pathway. The
via 4 may extend through an entire thickness of the semiconductor
substrate 8, as shown in FIG. 1, or may form a blind hole in the
semiconductor substrate 8, as shown in FIG. 2. If the via 4 extends
through the thickness of the semiconductor substrate 8, the via 4
may be referred to as a through-wafer-interconnect ("TWI"). The TWI
may electrically connect integrated circuits on one side of the
semiconductor substrate to another component or apparatus on the
opposing side. If the via 4 forms a blind hole in the semiconductor
substrate, the via 4 may be referred to as a
blind-wafer-interconnect ("BWI").
The intermediate semiconductor device structure 2 may also include
a semiconductor substrate 8, a first oxide layer 10 covering a
surface of the semiconductor substrate 8, and a passivation layer
12 covering portions of the first oxide layer 10, as shown in FIG.
3. The semiconductor substrate 8 may be a semiconductor wafer or
other bulk substrate that includes a layer of semiconductive
material. The term "bulk substrate" as used herein includes not
only silicon wafers (e.g. monocrystalline silicon or
polycrystalline silicon), but silicon on insulator ("SOI")
substrates, silicon on sapphire ("SOS") substrates, silicon on
glass ("SOG") substrates, epitaxial layers of silicon on a base
semiconductor foundation, and other semiconductor materials, such
as silicon-germanium, germanium, ruby, quartz, sapphire, gallium
arsenide, diamond, silicon carbide, or indium phosphide. The first
oxide layer 10 may be a silicon oxide layer, such as a layer of
phosphorus silicate glass ("PSG"), borosilicate glass ("BSG"),
borophosphosilicate glass ("BPSG"), or spin-on dielectric ("SOD").
In one embodiment, the first oxide layer 10 is a BPSG layer. The
passivation layer 12 may be formed from silicon dioxide
("SiO.sub.2"), silicon nitride ("SiN"), silicon oxynitride, BPSG,
PSG, BSG, a polyimide, benzocyclobutene, mixtures thereof, or
another nonconductive material as known in the art. In one
embodiment, the passivation layer 12 is a sandwich structure of
SiO.sub.2 and SiN, as known in the art. The passivation layer 12
may have a thickness ranging from approximately 0.5 .mu.m to 10
.mu.m. The first oxide layer 10 and the passivation layer 12 may
have been previously formed on the semiconductor substrate 8 by
conventional techniques.
If the via 4 is to be a TWI, the via 4 may be formed in the
intermediate semiconductor device structure 2 by forming at least
one opening 14 that extends through a thickness of the
semiconductor substrate 8, as illustrated in FIGS. 3-7. The opening
14 may be formed by laser drilling or ablation, dry etching, such
as a reactive ion etch, photochemical etching, masking and
anisotropic etching, mechanical drilling, or any other known
process of forming openings in semiconductor substrates 8. For the
sake of example only, the opening 14 may be formed by depositing a
photoresist layer 16 over the bond pads 6 and the passivation layer
12. The photoresist layer 16 may be etched to expose at least a
portion of the bond pad 6, as shown in FIG. 4. The photoresist
layer 16 may be a conventional photoresist and is deposited by
conventional techniques. The exposed portion of the bond pad 6 may
be removed to expose at least a portion of the first oxide layer
10. The exposed portion of the first oxide layer 10 may be removed
as shown in FIG. 5 to expose a portion of the semiconductor
substrate 8, which is subsequently removed to form the opening 14,
as shown in FIG. 6. Remaining portions of the photoresist layer 16
may then be removed as shown in FIG. 7. Alternatively, the exposed
portion of the first oxide layer 10 and an underlying portion of
the semiconductor substrate 8 may be etched substantially
simultaneously to form the opening 14. The resulting opening 14 may
have a high aspect ratio ranging from approximately 4:1 (substrate
thickness:via diameter) to approximately 30:1.
Alternatively, the opening 14 may be formed by etching a hole
through the bond pad 6 using a wet etch chemistry, as known in the
art. The hole may be extended using a dry oxide etch, such as by
reactive ion etching ("RIE"), to etch the first oxide layer 10 and
expose the semiconductor substrate 8. A dimple may be formed in the
semiconductor substrate 8 with a wet etch chemistry that includes a
solution of tetramethylammonium hydroxide ("TMAH") and an organic
solvent, such as propylene glycol. The dimple may range in size
from approximately 10 .mu.m to approximately 15 .mu.m. The etch
solution may include from approximately 1% by weight to
approximately 10% by weight of TMAH and from approximately 90% by
weight to approximately 99% by weight of the organic solvent. In
one embodiment, the etch solution includes approximately 6% TMAH
and approximately 94% propylene glycol.
The hole may be extended through the semiconductor substrate 8 by
laser ablating a portion of the semiconductor substrate 8. The
semiconductor substrate 8 may be laser ablated by directing a laser
beam toward the dimple from a back surface of the semiconductor
substrate 8. The dimple may keep energy produced by the laser beam
from an active surface of the integrated circuit. The energy from
the laser beam may ablate the portion of the semiconductor
substrate 8, extending the hole and forming the opening 14.
However, the energy from the laser beam may unduly heat the
semiconductor substrate 8 surrounding the opening 14 and produce a
heat affected zone ("HAZ"), which is an area of damaged silicon
surrounding the opening 14. The material of the HAZ is commonly
referred to as a "slag" and may include silicon and oxygen. The
dimple formed in the semiconductor substrate 8 may also prevent
slag from being deposited on the active surface of the integrated
circuit. The HAZ may be removed so that the opening 14 has a
sufficient width or diameter to form the necessary conductive path.
The HAZ may be removed using the TMAH and propylene glycol etch
solution previously described. This etch solution may selectively
remove the HAZ without damaging other portions of the integrated
circuit, such as the bond pad 6 or the first oxide layer 10.
The photoresist layer 16, the exposed portions of the bond pads 6,
the exposed portions of the first oxide layer 10, and the exposed
portions of the semiconductor substrate 8 may be removed from the
intermediate semiconductor device structure 2 by using conventional
dry etch chemistries, conventional wet etch chemistries, or a laser
etch. The etching techniques and conditions may be selected by one
of ordinary skill in the art based on the materials used in each of
these layers. Therefore, the etching techniques and conditions are
not discussed in detail herein. For sake of example only, the first
oxide layer 10 may be etched using a plasma etch with a
tetrafluoromethane ("CF.sub.4") chemistry or a trifluoromethane
("CHF.sub.3") and oxygen ("O.sub.2") chemistry. Alternatively, the
first oxide layer 10 may be etched with an aqueous solution of
dilute hydrogen fluoride ("HF"). The semiconductor substrate 8 may
be etched using a plasma etch with a NF.sub.3, HBr/Cl,
C.sub.2F.sub.4, or SF.sub.6 chemistry.
The opening 14 may be lined with a second oxide layer 18 to seal
portions of the semiconductor substrate 8 that are exposed when the
opening 14 is formed. The second oxide layer 18 may be formed from
a low stress or low Si oxide ("LSO"), which is deposited on the
semiconductor substrate 8 by conventional techniques. The second
oxide layer 18 may be deposited at a thickness ranging from 0.1
.mu.m to approximately 5 .mu.m, such as from approximately 1 .mu.m
to approximately 2 .mu.m. A tungsten layer 20 may be formed over
the second oxide layer 18 to provide a seed layer upon which the
nickel is subsequently deposited. The tungsten layer 20 may have a
thickness ranging from approximately 0.02 .mu.m to approximately 1
.mu.m. The tungsten layer 20 may be formed by atomic layer
deposition ("ALD"), electroless deposition, electroplating,
chemical vapor deposition ("CVD"), plasma-enhanced CVD ("PECVD"),
or physical vapor deposition ("PVD"), as known in the art. An
adhesion layer may optionally be present between the tungsten layer
20 and the second oxide layer 18 to more firmly adhere the tungsten
layer 20 to the second oxide layer 18. The adhesion layer may be
formed by ALD, CVD, PECVD, PVD, vacuum evaporation, or sputtering.
In one embodiment, the adhesion layer is formed from titanium
nitride ("TiN"). The adhesion layer may have a thickness ranging
from approximately 50 .ANG. to approximately 200 .ANG.. The
adhesion layer may be used in the opening 14 depending on a
thickness of the tungsten layer 20. If the tungsten layer 20 is
less than approximately 500 .ANG. thick, the adhesion layer may not
be needed to adhere the tungsten layer 20 to the second oxide layer
18. However, if the tungsten layer 20 is greater than approximately
500 .ANG. thick, the adhesion layer may be used to adequately
adhere the tungsten layer 20 to the second oxide layer 18.
If the via 4 is to be a BWI, the via 4 may be formed in the
intermediate semiconductor device structure 2 by forming at least
one opening 14 that extends a selected depth into the semiconductor
substrate 8, as shown in FIG. 2. In this situation, the opening 14
may be formed as described above, except that the opening 14 does
not extend through the entire thickness of the semiconductor
substrate 8. The opening 14 may be lined with the second oxide
layer 18 and the tungsten layer 20, as described above.
As shown in FIGS. 8 and 9, the second oxide layer 18, the tungsten
layer 20, and the adhesion layer (if present) of the intermediate
semiconductor device structure 2 may be etched to remove portions
of these layers overlying the bond pads 6 and the passivation layer
12. Portions of the second oxide layer 18 and the tungsten layer 20
may remain in the via 4. This etch step is referred to herein as a
"spacer etch." The etching techniques and conditions used to remove
the second oxide layer 18, the tungsten layer 20, and the adhesion
layer (if present) may be selected by one of ordinary skill in the
art based on the materials in these layers and, therefore, are not
discussed in detail herein. For sake of example only, the tungsten
layer 20 and the adhesion layer (if present) may be removed with a
conventional dry etch. The second oxide layer 18 may be removed
with a conventional wet etch.
A first nickel layer 22 may then be plated on the exposed bond pads
6 without plating nickel on the tungsten layer 20, as shown in
FIGS. 10 and 11. To form the first nickel layer 22, the surface of
the bond pads 6 may be cleaned to remove aluminum oxides. By way of
example, a cleaning solution used to remove the aluminum oxides may
be an aqueous solution of sodium hydroxide ("NaOH") and nitric acid
("HNO.sub.3") or phosphoric acid. The NaOH may dissolve the
aluminum oxides on the surface of the bond pads 6 while the
HNO.sub.3 or phosphoric acid may etch the surface of the bond pads
6 to provide a clean aluminum surface upon which the first nickel
layer 22 is ultimately plated. The cleaning solution may include
from approximately 1% to approximately 5% NaOH and approximately
50% HNO.sub.3, with the remainder being water. The bond pads 6 may
be cleaned by immersing the intermediate semiconductor device
structure 2 in the cleaning solution or by spraying the
intermediate semiconductor device structure 2 with the cleaning
solution. The bond pads 6 may then be rinsed with deionized water
to remove the NaOH and HNO.sub.3 or phosphoric acid. Other wet
etches known in the art to remove the aluminum oxide formed on the
bond pads 6 may also be employed.
After removing the aluminum oxides, the surface of the bond pads 6
may be activated toward nickel plating using an activator that is
selective for aluminum. Since the aluminum activator is selective
for aluminum, the surface of the tungsten layer 20 may not be
activated toward nickel plating. The aluminum activator may be an
aqueous zincate solution that includes a zinc source material, such
as zinc oxide ("ZnO"), and a caustic base, such as NaOH or another
alkali metal hydroxide. At alkaline pH, the zinc source material
may be present in the zincate solution as Zn(OH).sub.4. The
intermediate semiconductor device structure 2 may be exposed to the
zincate solution for an amount of time sufficient to deposit a
zinc-containing layer on the surface of the bond pads 6. The
zinc-containing layer may include from approximately one monolayer
to approximately two monolayers of a layer rich in zinc. The
zinc-containing layer may function as a seed layer to the first
nickel layer 22. The intermediate semiconductor device structure 2
may be exposed to the zincate solution for from approximately 10
seconds to approximately 1 minute. Zincate solutions are
commercially available from various manufacturers, such as from
LeaRonal Inc. (Buffalo, N.Y.) or PacTech GmbH (Berlin, Germany).
The bond pads 6 of the intermediate semiconductor device structure
2 may be activated by immersing the intermediate semiconductor
device structure 2 in the aluminum activator or spraying the
intermediate semiconductor device structure 2 with the aluminum
activator. The aluminum activator may be maintained at a
temperature ranging from approximately 20.degree. C. to
approximately 40.degree. C.
Once the bond pads 6 are activated toward nickel plating, the
intermediate semiconductor device structure 2 may he rinsed with
deionized water and immersed in a bath containing the electroless
nickel plating solution to form the first nickel layer 22. The
first nickel layer 22 may act as a wetting layer that enables
molten solder to more effectively fill the via 4. The first nickel
layer 22 may also act as a barrier layer. Electroless nickel
plating solutions are known in the art, such as electroless
nickel-phosphorus plating solutions or electroless nickel-boron
plating solutions. Such electroless nickel plating solutions are
commercially available, such as NicPac 2.1, NicPac 2.2, and NicPac
2.3, which are available from PacTech GmbH (Berlin, Germany) and
RONAMAX.RTM. SMT, DURAPOSIT.RTM., NIPOSIT.RTM., NIPLATE.TM., which
are available from Rohm and Haas Electronic Materials
(Philadelphia, Pa.). These electroless nickel plating solutions
include nickel salts, such as nickel sulfite, nickel chloride,
nickel sulfate, nickel bromide, nickel fluoroborate, nickel
sulfonate, nickel sulfamate, and nickel alkyl sulfonates as a
source of the nickel ion. The electroless nickel plating solution
may also include a reducing agent, such as a phosphorus compound or
a boron compound. Examples of reducing agents include sodium
hypophosphite, dimethylamine borane, sodium borohydride, and DMAB.
The electroless nickel plating solution may also include NaOH to
maintain the pH of the solution and complexing agents, such as
citric acid, lactic acid, or malic acid. The pH of the electroless
nickel plating solution may be maintained from approximately 4 to
approximately 6. During the electroless plating, nickel ions are
reduced to nickel by oxidation of the reducing agent. In one
embodiment, the electroless nickel plating solution includes nickel
chloride, sodium hydroxyacetate, and sodium hypophosphite. In
another embodiment, the electroless nickel plating solution
includes nickel sulfate and sodium hypophosphite. The electroless
nickel plating solution in the bath may be maintained at a
temperature ranging from approximately 60.degree. C. to
approximately 100.degree. C., such as from approximately 80.degree.
C. to approximately 90.degree. C.
A thickness of the first nickel layer 22 on the bond pads 6 may
depend on the concentration of nickel in the electroless nickel
plating solution and an amount of time the intermediate
semiconductor device structure 2 is immersed in the electroless
nickel plating solution. The first nickel layer 22 may have a
thickness ranging from approximately 500 .ANG. to approximately 10
.mu.m. In one embodiment, the first nickel layer 22 has a thickness
of approximately 1 .mu.m. The intermediate semiconductor device
structure 2 may be immersed in the electroless nickel plating
solution for an amount of time sufficient to deposit the desired
thickness of the first nickel layer 22 on the bond pad 6, such as
from approximately 1 minute to approximately 5 minutes. During the
nickel plating, the zinc-containing layer on the bond pad 6 may be
replaced with the first nickel layer 22. Since the nickel plating
chemistry is selective for aluminum, the bond pad 6 may be
substantially plated with nickel, while substantially no nickel is
plated on the tungsten layer 20 in the via 4.
Since the nickel plating chemistry may be used to plate directly on
copper, bond pads 6 formed from copper may be selectively plated
with nickel without nickel plating the tungsten layer 20.
Activation of the bond pads 6 formed from copper may occur
substantially as described above in regard to the aluminum bond pad
6. Alternatively, the copper bond pad 6 may be activated with a
palladium solution before nickel plating, rather than with the
zincate solution.
After the first nickel layer 22 has been formed over the bond pads
6, the second nickel layer 24 may be deposited in the opening 14 to
line the via 4, as shown in FIGS. 12 and 13. The second nickel
layer 24 may act as a wetting layer to enable the molten solder to
more effectively fill the via 4. The second nickel layer 24 may be
deposited over the tungsten layer 20 after first removing oxides
from the tungsten layer 20. The tungsten layer 20 may be cleaned
chemically, such as by using an aqueous potassium hydroxide ("KOH")
solution.
The tungsten layer 20 may then be activated toward nickel plating
with an activator that is selective for tungsten. Since the
tungsten activator is selective for tungsten, the bond pads 6 may
not be activated toward nickel plating. The tungsten activator may
be an aqueous palladium solution that includes palladium (II) ions.
The intermediate semiconductor device structure 2 may be exposed to
the tungsten activator for a sufficient amount of time to deposit a
thin layer of palladium on the surface of the tungsten layer 20.
For instance, the intermediate semiconductor device structure may
be exposed to the tungsten activator for from approximately 10
seconds to approximately 1 minute. The tungsten layer 20 of the
intermediate semiconductor device structure 2 may be activated by
immersing the intermediate semiconductor device structure 2 in the
tungsten activator or spraying the intermediate semiconductor
device structure 2 with the tungsten activator.
After the tungsten layer 20 is activated toward nickel plating, the
intermediate semiconductor device structure 2 may be immersed in a
bath containing the electroless nickel plating solution to form the
second nickel layer 24 on the tungsten layer 20. The electroless
nickel plating solution may be a conventional nickel plating
solution. The electroless nickel plating solution may be the same
electroless nickel plating solution as used to plate the first
nickel layer 22 or may be a different electroless nickel plating
solution. The electroless nickel plating solutions are as
previously described. The second nickel layer 24 may have a
thickness ranging from approximately 500 .ANG. to approximately 10
.mu.m. In one embodiment, the second nickel layer 24 has a
thickness ranging from approximately 3 .mu.m to approximately 5
.mu.m. The intermediate semiconductor device structure 2 may be
immersed in the electroless nickel plating solution for an amount
of time sufficient to deposit the desired thickness of the second
nickel layer 24 on the bond pad 6, such as from approximately 1
minute to approximately 5 minutes. During the nickel plating, the
layer of palladium on the tungsten layer 20 may be replaced with
the second nickel layer 24. Since the electroless nickel plating
solution is selective for tungsten, the tungsten layer 20 may be
substantially plated with nickel while substantially no nickel is
plated on the bond pads 6.
The via 4 may then be filled with solder 26 to provide the
conductive pathway, as shown in FIGS. 14 and 15. The solder may be
a conventional solder formulation that includes tin, lead, indium,
antimony, silver, copper, and mixtures thereof. The solder may be
capable of wetting or filling the via 4. Suitable solder
formulations may include, but are not limited to 95% lead/5% tin,
60% lead/40% tin, 63% indium/37% tin, 100% tin, and 62% lead/36%
tin/2% silver. To fill the via 4 with the solder 26, the solder 26
may be heated to a temperature sufficient to melt the solder 26,
such as from 180.degree. C. to approximately 300.degree. C. The
molten solder may then be deposited in the via 4 or near the bond
pads 6. If the molten solder is deposited near the bond pads 6, it
may be reflowed into the via 4 to provide the conductive path. The
solder 26 may also be deposited using a wave solder process in
which the molten solder is applied to a back surface of the
intermediate semiconductor device structure 2, if the via 4 is a
TWI. The molten solder may then be drawn into the via 4 by
capillary action and wetting forces.
If the via 4 is a BWI, a mass of solder, such as a solder ball, may
be placed at the mouth of the via 4, melted, and drawn into the via
4 by capillary action. A back surface of the semiconductor
substrate 8 may be removed, as shown in FIG. 16, to expose the via
4. The back surface of the semiconductor substrate 8 may be removed
by backgrinding, as known in the art. Backgrinding of the
semiconductor substrate 8 may be achieved by chemical mechanical
polishing ("CMP") or by abrasive means. After removing the back
surface, the via 4 may extend through the thickness of the
semiconductor substrate 8, forming a TWI. As such, the TWI may be
formed directly or may be formed after first forming the BWI.
Alternatively, the first nickel layer 22 may be formed over the
bond pads 6, as shown in FIG. 17. The first nickel layer 22 may be
formed as previously described. Then, the opening 14 may be formed
in the semiconductor substrate 8, as shown in FIG. 18. The opening
14 may be formed as previously described. The second oxide layer
18, the tungsten layer 20, and, optionally, the adhesion layer, may
then be deposited in the opening 14 to form the via 4 as shown in
FIG. 19. The second oxide layer 18, the tungsten layer 20, and the
adhesion layer (if present) may be removed from the surface of the
intermediate semiconductor device structure 2 using the spacer
etch. The second nickel layer 24 may then be plated over the
tungsten layer 20, as shown in FIG. 20. The second nickel layer 24
may be plated as previously described. The via 4 may then be filled
with solder 26, as previously described in regard to FIG. 14. By
depositing the first nickel layer 22 over the bond pads 6 before
the via 4 is formed, nickel may not be deposited on portions of the
semiconductor substrate 8 that are exposed after the opening 14 is
formed.
By depositing the first nickel layer 22 on the aluminum structure
before depositing the second nickel layer 24 on the tungsten
structure, the aluminum structure may be protected during
subsequent processing steps. For instance, the first nickel layer
22 may act as a nickel mask to protect the aluminum structure from
exposure to the tungsten activator. The tungsten structure may then
be nickel plated without further protecting the aluminum structure.
In addition, since the tungsten structure is nickel plated after
nickel plating the aluminum structure, nickel is not removed from
the tungsten structure by the cleaning, activating, and plating
chemistries used to plate the aluminum structure. In other words,
the etching chemistry used to remove the aluminum oxides may not
remove portions of the second nickel layer 24 from inside the via
4.
As previously mentioned, in another embodiment, the tungsten
structure is plated with nickel before nickel plating the aluminum
structure. The tungsten structure may be selectively plated with
nickel by activating the tungsten structure toward nickel plating
and subsequently depositing the nickel, as previously described.
The aluminum structure may then be nickel plated by activating the
aluminum structure toward nickel plating and subsequently
depositing the nickel, as previously described.
In another embodiment, the tungsten structure and the aluminum
structure are plated with nickel substantially simultaneously by
activating the surfaces of both the tungsten structure and the
aluminum structure before nickel plating. The aluminum structure
may be activated by exposing the intermediate semiconductor device
structure 2 to the zincate solution, as previously described. The
intermediate semiconductor device structure 2 may then be exposed
to the tungsten activator to activate the tungsten structure. The
activated tungsten structure and the aluminum structure may then be
nickel plated, as previously described.
In addition to selectively plating one of the aluminum structure
and the tungsten structure with nickel, the method of the present
invention may also be used to selectively plate one of a copper
structure and the tungsten structure with nickel. As such, the bond
pad 6 may be formed from copper or mixtures of aluminum and copper.
Since conventional nickel plating chemistries may be plated
directly onto copper, the bond pad 6 formed from copper may be
selectively plated with nickel.
While the invention may be susceptible to various modifications and
alternative forms, specific embodiments have been shown by way of
example in the drawings and have been described in detail herein.
However, it should be understood that the invention is not intended
to be limited to the particular forms disclosed. Rather, the
invention is to cover all modifications, equivalents, and
alternatives falling within the spirit and scope of the invention
as defined by the following appended claims.
* * * * *
References