U.S. patent application number 17/688647 was filed with the patent office on 2022-06-16 for formation method of chip package.
This patent application is currently assigned to Taiwan Semiconductor Manufacturing Company, Ltd.. The applicant listed for this patent is Taiwan Semiconductor Manufacturing Company, Ltd.. Invention is credited to Shuo-Mao CHEN, Po-Yao CHUANG, Shin-Puu JENG, Po-Hao TSAI, Ming-Chih YEW.
Application Number | 20220189884 17/688647 |
Document ID | / |
Family ID | |
Filed Date | 2022-06-16 |
United States Patent
Application |
20220189884 |
Kind Code |
A1 |
CHUANG; Po-Yao ; et
al. |
June 16, 2022 |
FORMATION METHOD OF CHIP PACKAGE
Abstract
A method for forming a chip package is provided. The method
includes forming a plurality of conductive structures over a
carrier substrate. The method also includes disposing a
semiconductor die over the carrier substrate such that the
conductive ti structures surround the semiconductor die. The method
further includes disposing a shielding element over the
semiconductor die and the conductive structures. The shielding
element is electrically connected to the conductive structures.
Inventors: |
CHUANG; Po-Yao; (Hsin-Chu,
TW) ; TSAI; Po-Hao; (Zhongli City, TW) ; JENG;
Shin-Puu; (Hsinchu, TW) ; CHEN; Shuo-Mao; (New
Taipei City, TW) ; YEW; Ming-Chih; (Hsinchu City,
TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Taiwan Semiconductor Manufacturing Company, Ltd. |
Hsinchu |
|
TW |
|
|
Assignee: |
Taiwan Semiconductor Manufacturing
Company, Ltd.
Hsinchu
TW
|
Appl. No.: |
17/688647 |
Filed: |
March 7, 2022 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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16284630 |
Feb 25, 2019 |
11270953 |
|
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17688647 |
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62725675 |
Aug 31, 2018 |
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International
Class: |
H01L 23/552 20060101
H01L023/552; H01L 23/538 20060101 H01L023/538; H01L 23/31 20060101
H01L023/31; H01L 21/48 20060101 H01L021/48; H01L 25/065 20060101
H01L025/065; H01L 25/00 20060101 H01L025/00; H01L 21/56 20060101
H01L021/56; H05K 1/02 20060101 H05K001/02; H01L 23/498 20060101
H01L023/498; H01L 25/16 20060101 H01L025/16 |
Claims
1. A method for forming a chip package, comprising: forming a
plurality of conductive structures over a carrier substrate;
disposing a semiconductor die over the carrier substrate such that
the conductive structures surround the semiconductor die; and
disposing a shielding element over the semiconductor die and the
conductive structures, wherein the shielding element is
electrically connected to the conductive structures.
2. The method as claimed in claim 1, further comprising: forming a
protective layer to surround the conductive structures and the
semiconductor die; and bonding a protective substrate to the
conductive structures before the a protective layer is formed.
3. The method as claimed in claim 2, further comprising forming the
shielding element over the protective substrate before bonding the
protective substrate to the conductive structures.
4. The method as claimed in claim 2, further comprising forming an
antenna element over the protective substrate.
5. The method as claimed in claim 4, wherein the antenna element is
formed over the protective substrate before bonding the protective
substrate to the conductive structures.
6. The method as claimed in claim 2, wherein the protective
substrate is bonded to the conductive structures through
tin-containing solder elements.
7. The method as claimed in claim 2, further comprising:
introducing a polymer material between the protective substrate and
the carrier substrate; and curing the polymer material to form the
protective layer.
8. The method as claimed in claim 2, further comprising forming a
redistribution structure over the carrier substrate before the
conductive structures are formed.
9. The method as claimed in claim 8, further comprising: removing
the carrier substrate; and forming conductive bumps over the
redistribution structure, wherein the redistribution structure is
between the protective layer and the conductive bumps.
10. The method as claimed in claim 2, further comprising disposing
an additional semiconductor die over the carrier substrate before
the protective layer is formed, wherein the additional
semiconductor die is outside of an area surrounded by the
conductive structures.
11. The method as claimed in claim 1, wherein the shielding element
comprises a conductive plate, a conductive mesh, or a combination
thereof.
12. The method as claimed in claim 1, wherein two of the conductive
structures are separated from each other by a distance, and the
distance is smaller than half a wavelength of an electromagnetic
wave generated by the semiconductor die.
13. A method for forming a chip package, comprising: forming a
plurality of conductive structures over a redistribution structure;
and disposing a semiconductor die over the redistribution structure
such that the conductive structures surround the semiconductor die;
wherein two of the conductive structures are separated from each
other by a distance, and the distance is smaller than half a
wavelength of an electromagnetic wave generated by the
semiconductor die.
14. The method as claimed in claim 13, wherein each of the
conductive structures has a width in a range from about 5 .mu.m to
about ten times the distance.
15. The method as claimed in claim 13, further comprising: forming
a protective layer to surround the conductive structures and the
semiconductor die; and bonding a protective substrate to the
conductive structures before the protective layer is formed.
16. The method as claimed in claim 15, further comprising forming a
shielding element over the protective substrate before bonding the
protective substrate to the conductive structures.
17. A method for forming a chip package, comprising: disposing a
first semiconductor die and a second semiconductor die over the a
redistribution structure; and disposing a plurality of conductive
structures over the redistribution structure; wherein the
conductive structures surround an area where the first
semiconductor die is positioned, and the second semiconductor die
is positioned outside of the area.
18. The method as claimed in claim 17, wherein two of the
conductive structures are separated from each other by a distance,
and the distance is smaller than half a wavelength of an
electromagnetic wave generated by the first semiconductor die.
19. The method as claimed in claim 17, further comprising disposing
a shielding element over the first semiconductor die, wherein the
shielding element is electrically connected to the conductive
structures.
20. The method as claimed in claim 19, wherein the shielding
element comprises a conductive mesh having a plurality of
through-holes, and each of the through-holes has a width that is
smaller than half the wavelength of the electromagnetic wave
generated by the first semiconductor die.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a Divisional of U.S. patent application
Ser. No. 16/284,630, filed Feb. 25, 2019, which claims the benefit
of U.S. Provisional Application No. 62/725,675, filed Aug. 31,
2018, the entirety of which is incorporated by reference herein
BACKGROUND OF THE INVENTION
Field of the Invention
[0002] The present invention relates to devices and methods for
forming a chip package.
Description of the Related Art
[0003] Semiconductor devices are used in a variety of electronic
applications, such as personal computers, cell phones, digital
cameras, and other electronic equipment. The fabrication of the
semiconductor devices involves sequentially depositing insulating
or dielectric layers, conductive layers, and semiconductor layers
over a semiconductor substrate, and patterning the various material
layers using lithography and etching processes to form circuit
components and elements on the semiconductor substrate.
[0004] The semiconductor industry continues to improve the
integration density of various electronic components (e.g.,
transistors, diodes, resistors, capacitors, etc.) by continual
reductions in minimum feature size, which allows more components to
be integrated into a given area. The number of input and output
(I/O) connections is significantly increased. Smaller package
structures, which utilize less area or have lower heights, are
developed to package the semiconductor devices.
[0005] New packaging technologies have been developed to improve
the density and functionality of semiconductor devices. These
relatively new types of packaging technologies for semiconductor
devices face manufacturing challenges.
BRIEF SUMMARY OF THE INVENTION
[0006] According to some embodiments, a method for forming a chip
package is provided. The method includes forming a plurality of
conductive structures over a carrier substrate. The method also
includes disposing a semiconductor die over the carrier substrate
such that the conductive structures surround the semiconductor die.
The method further includes disposing a shielding element over the
semiconductor die and the conductive structures. The shielding
element is electrically connected to the conductive structures.
[0007] According to some embodiments, a method tier forming a chip
package is provided. The method includes forming a plurality of
conductive structures over a redistribution structure. The method
also includes disposing a semiconductor die over the redistribution
structure such that the conductive structures surround the
semiconductor die. Two of the conductive structures are separated
from each other by a distance, and the distance is smaller than
half a wavelength of an electromagnetic wave generated by the
semiconductor die.
[0008] According to some embodiments, a method for forming a chip
package is provided. The method includes disposing a first
semiconductor die and a second semiconductor die over the a
redistribution structure. The method also includes disposing a
plurality of conductive structures over the redistribution
structure. The conductive structures surround an area where the
first semiconductor die is positioned, and the second semiconductor
die is positioned outside of the area.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Aspects of the present disclosure are best understood from
the following detailed description when read with the accompanying
figures. It should be noted that, in accordance with the standard
practice in the industry, various features are not drawn to scale.
In fact, the dimensions of the various features may be arbitrarily
increased or reduced for clarity of discussion.
[0010] FIGS. 1A-1F are cross-sectional views of various stages of a
process for forming a chip package, in accordance with some
embodiments.
[0011] FIGS. 2A-2E are cross-sectional views of various stages of a
process for forming a chip package, in accordance with some
embodiments.
[0012] FIG. 3 is a top view of an intermediate stage of a process
for forming a chip package, in accordance with some
embodiments.
[0013] FIG. 4 is a top view of an intermediate stage of a process
for forming a chip package, in accordance with some
embodiments.
[0014] FIG. 5 is a top view of an intermediate stage of a process
for forming a chip package, in accordance with some
embodiments.
[0015] FIG. 6 is a top view of an intermediate stage of a process
for forming a chip package, in accordance with some
embodiments.
[0016] FIG. 7 is a top view of an intermediate stage of a process
for forming a chip package, in accordance with some
embodiments.
[0017] FIGS. 8A-8C are cross-sectional views of various stages of a
process for forming a chip package, in accordance with some
embodiments.
[0018] FIG. 9 is a cross-sectional view of a chip package, in
accordance with some embodiments.
[0019] FIG. 10 is a cross-sectional view of a chip package, in
accordance with some embodiments.
[0020] FIG. 11 is a cross-sectional view of a chip package, in
accordance with some embodiments.
[0021] FIG. 12 is a cross-sectional view of a chip package, in
accordance with some embodiments.
[0022] FIG. 13 is a cross-sectional view of a chip package, in
accordance with some embodiments.
[0023] FIG. 14 is a top view of a shielding element of a chip
package, in accordance with some embodiments.
[0024] FIG. 15 is a top view of a shielding element of a chip
package, in accordance with some embodiments.
DETAILED DESCRIPTION OF THE INVENTION
[0025] The following disclosure provides many different
embodiments, or examples, for implementing different features of
the provided subject matter. Specific examples of components and
arrangements are described below to simplify the present
disclosure. These are, of course, merely examples and are not
intended to be limiting. For example, the formation of a first
feature over or on a second feature in the description that follows
may include embodiments in which the first and second features are
formed in direct contact, and may also include embodiments in which
additional features may be formed between the first and second
features, such that the first and second features may not be in
direct contact. In addition, the present disclosure may repeat
reference numerals and/or letters in the various examples. This
repetition is for the purpose of simplicity and clarity and does
not in itself dictate a relationship between the various
embodiments and; or configurations discussed.
[0026] Further, spatially relative terms, such as "beneath,"
"below," "lower," "above," "upper" and the like, may be used herein
for ease of description to describe one element or feature's
relationship to another element(s) or feature(s) as illustrated in
the figures. The spatially relative terms are intended to encompass
different orientations of the device in use or operation in
addition to the orientation depicted in the figures. The apparatus
may be otherwise oriented (rotated 90 degrees or at other
orientations) and the spatially relative descriptors used herein
may likewise be interpreted accordingly.
[0027] Embodiments of the disclosure may be applied in 3D packaging
or 3D IC devices. Other features and processes may also be
included. For example, testing structures may be included to aid in
the verification testing of the 3D packaging or 3DIC devices. The
testing structures may include, for example, test pads formed in a
redistribution layer or on a substrate that allows the testing of
the 3D packaging or 3DIC, the use of probes and/or probe cards, and
the like. The verification testing may be performed on intermediate
structures as ;ell as the final structure. Additionally, the
structures and methods disclosed herein may be used in conjunction
with testing methodologies that incorporate intermediate
verification of known good dies to increase the yield and decrease
costs.
[0028] Some embodiments of the disclosure are described. Additional
operations can be provided before, during, and/or after the stages
described in these embodiments. Some of the stages that are
described can be replaced or eliminated for different embodiments.
Additional features can be added to the semiconductor device
structure. Some of the features described below can be replaced or
eliminated for different embodiments. Although some embodiments are
discussed with operations performed in a particular order, these
operations may be performed in another logical order.
[0029] FIGS. 1A-1F are cross-sectional views of various stages of a
process for forming a chip package, in accordance with some
embodiments. As shown in FIG. 1A, an interconnection structure 102
is formed over the carrier substrate 100, in accordance with some
embodiments. The interconnection structure 102 may be used as a
redistribution structure for routing. The interconnection structure
102 includes multiple insulating layers 104 and multiple conductive
features 106, as shown in FIG. 1A. The conductive features 106 may
include conductive lines, conductive vias, and/or conductive pads.
The interconnection structure 102 also includes conductive features
107 that are used to hold or receive other elements such as
conductive pillars or semiconductor dies.
[0030] In some embodiments, some of the conductive features 107 are
exposed at or protrude from the topmost surface of the insulating
layers 104. The exposed or protruding conductive features 107 may
serve as bonding pads where conductive bumps (such as
tin-containing solder bumps) and/or conductive pillars (such as
copper pillars) will be formed later.
[0031] The insulating layers 104 may be made of or include one or
more polymer materials. The polymer materials) may include
polybenzoxazole (PBO), polyimide (PI), one or snore other suitable
polymer materials, or a combination thereof. In some embodiments,
the polymer material is photosensitive. In some embodiments, some
or all of the insulating layers 104 are made of or include
dielectric materials other than polymer materials. The dielectric
material may include silicon oxide, silicon carbide, silicon
nitride, silicon oxynitride, one or more other suitable materials,
or a combination thereof.
[0032] The conductive features 106 may include conductive lines
providing electrical connection in horizontal directions and
conductive vias providing electrical connection in vertical
directions. The conductive features 106 may be made of or include
copper, aluminum, gold, cobalt, titanium, graphene, one or more
other suitable conductive materials, or a combination thereof.
[0033] The formation of the interconnection structure 102 may
involve multiple deposition or coating processes, multiple
patterning processes, and/or multiple planarization processes.
[0034] The deposition or coating processes may be used to form
insulating layers and/or conductive layers. The deposition or
coating processes may include a spin coating process, an
electroplating process, an electroless process, a chemical vapor
deposition (CVD) process, a physical vapor deposition (PAID)
process, an atomic layer deposition (ALD) process, one or more
other applicable processes, or a combination thereof.
[0035] The patterning processes may be used to pattern the formed
insulating layers and/or the formed conductive layers. The
patterning processes may include a photolithography process, an
energy beam drilling process (such as a laser beam drilling
process, an ion beam drilling process, or an electron beam drilling
process), an etching process, a mechanical drilling process, one or
more other applicable processes, or a combination thereof.
[0036] The planarization processes may be used to provide the
formed insulating layers and/or the formed conductive layers with
planar top surfaces to facilitate subsequent processes. The
planarization processes may include a mechanical grinding process,
a chemical mechanical polishing (CMP) process, one or more other
applicable processes, or a combination thereof.
[0037] However, marry variations and/or modifications can be made
to embodiments of the disclosure in some other embodiments, the
interconnection structure 102 is not formed.
[0038] Afterwards, conductive structures 108 and 108S are formed
over some of the conductive features 107, as shown in FIG. 1A in
accordance with some embodiments. In some embodiments, the
conductive structures 108 are used for signal transmission. In some
embodiments, the conductive structures 108S are used as a shielding
structure capable of preventing electromagnetic interference (EMI)
caused by a semiconductor die that will be disposed later.
[0039] In some embodiments, the conductive structures 108 and 108S
are conductive pillars. In some embodiments. the conductive
structures 108 and 108S have substantially straight sidewalls. The
sidewalls of the conductive structures 108 and 108S may be
substantially perpendicular to the top surface of the camel
substrate 100. The conductive structures 108 and 108S may be made
of or include copper, aluminum, titanium, cobalt, gold,
tin-containing alloys, one or more other suitable materials, or a
combination thereof.
[0040] The conductive structures 108 and 108S may be formed using
an electroplating process, an electroless plating process, a PVD
process, a CVD process, one or more other applicable processes, or
a combination thereof. In some other embodiments, the conductive
structures 108 and 108S are picked and placed onto the exposed
conductive features 107. Tin-containing solder elements may be used
to affix the conductive structures 108 and 108S. In some
embodiments, the conductive structures 108 and 108S are
simultaneously formed. In some other embodiments, the conductive
structures 108 and 108S are separately formed. For example, the
conductive structures 108 are formed before the conductive
structures 108S. Alternatively, the conductive structures 108S are
formed before the conductive structures 108.
[0041] As shown in FIG. 1B semiconductor device such as a
semiconductor dies 110A and 110B are disposed over the carrier
substrate 100, in accordance with some embodiments, The
semiconductor die 110B is disposed outside of an area that is
surrounded by the conductive structures 108S, as shown in FIG.
1B.
[0042] In some embodiments, the semiconductor dies 110A and 110B
are disposed onto some of the exposed conductive features 107. The
semiconductor dies 110A and 110B may be a system-on-chip (SoC)
chip. In some other embodiments, the element 110A or 110B is a
system on integrated circuit (SoIC) device that includes two or
more chips with integrated function. In these cases, the reference
number "110A or 110B" is used to designate a semiconductor device.
The semiconductor device may include one die, multiple dies, or
system-on-integrated-circuit chip device. For example, one or two
of the elements 110A and 110B include a stack of multiple
semiconductor dies.
[0043] In some embodiments, the semiconductor die 110A includes
radio-frequency integrated circuits (RF-IC) such as radio-frequency
front end (RFFE) modules. The operation frequency of the
semiconductor die 110A is in the radio-frequency range. An
electromagnetic wave having the wavelength corresponding to the
operation frequency may be generated by the semiconductor die 110A
during operation.
[0044] For example, the operation frequency of the semiconductor
die 110A may be about 28 GHz. In these cases, electromagnetic wave
having a wavelength of about 10.7 mm may be generated by the
semiconductor die 110A during operation. For example, the
electromagnetic wave may be transmitted through the protective
substrate 20. In some cases, the generated electromagnetic wave may
negatively affect the operation of nearby device elements (such as
the semiconductor die 110B or mother device element in another
nearby chip package). In some embodiments, shielding structures
and/or shielding elements are fort ed later to prevent the
generated electromagnetic wave from reaching nearby device elements
and affecting the operation of the nearby device elements.
[0045] In sonic embodiments, the semiconductor die 110B includes
low-noise amplifier (LNA) modules, low-loss filter modules, power
amplifier (PA) modules, baseband modules, power management
integrated circuit (PMIC), memory modules, micro-electromechanical
system (MEMS) modules, nano-electromechanical systems (NEMS)
modules, one or more other suitable circuits, or a combination
thereof. In some embodiments, the semiconductor die 110B does not
include any radio-frequency integrated circuit.
[0046] In some embodiments, the semiconductor dies 110A and 110B
are disposed over the interconnection structure 102 formed over the
carrier substrate 100. In some embodiments, the semiconductor dies
110A and 110B are bonded to some of the conductive features 107 of
the interconnection structure 102 through bonding structures 114.
The bonding structures 114 may physically and electrically connect
some of the conductive features 107 and conductive features 112 of
the semiconductor dies 110A and 110B. The conductive features 112
of the semiconductor dies 110A and 110B may include conductive
pads, conductive pillars, conductive traces, or the like.
[0047] In some embodiments, the bonding structures 114 are or
include solder bumps such as tin-containing solder bumps. The
tin-containing solder bumps may further include copper, silver,
gold, aluminum, lead, one or more other suitable materials, or a
combination thereof. In some embodiments, the tin-containing solder
bump is lead free. The formation of the bonding structures 114 may
involve one or more reflow processes and/or one or more plating
processes.
[0048] As show n in FIG. 1B, underfill elements 116 are formed to
protect the bonding structures 114, in accordance with some
embodiments. The underfill elements 116 are made of or include one
or more polymer materials. The underfill elements 116 may include
an epoxy-based resin. In some embodiments, the underfill elements
116 further include fillers dispersed in the epoxy-based resin. In
some embodiments, the formation of the underfill elements 116
involves an injecting process, a dispensing process, a film
lamination process, an application process, one or more other
applicable processes, or a combination thereof. In some
embodiments, a thermal curing process is then used to complete the
formation of the underfill elements 116.
[0049] As shown in FIG. 1C a protective substrate 20 is provided or
received and is ready to be bonded onto the conductive structures
108 and 108S, in accordance with some embodiments. In some
embodiments, the protective substrate 20 includes a board 200 and a
shielding element 208. In some embodiments, the protective
substrate 20 also includes conductive elements 214 and 214S. In
some embodiments, the protective substrate 20 includes antenna
elements, main patch elements, parasitic patch elements, ground
elements, one or more other suitable elements, or a combination
thereof.
[0050] FIGS. 2A-2E are cross-sectional views of various stages of a
process for forming a chip package, in accordance with some
embodiments. In some embodiments, the protective substrate 20 in
FIG. 1C is formed using the process illustrated in FIGS. 2A-2E.
[0051] As shown in FIG. 2A, conductive films 202A and 202B are
formed over opposite surfaces of the board 200, in accordance with
some embodiments. The conductive films 202A and 202B may be used to
assist in a subsequent electroplating process. The board 200 may be
made of or include a polymer material, a ceramic material, a metal
material, a semiconductor material, one or more other suitable
materials, or a combination thereof For example, the board 200
includes resin, prepreg, glass, and/or ceramic.
[0052] The conductive films 202A and 202B may be made of or include
aluminum, copper, cobalt, gold, titanium, one or more other
suitable materials, or a combination thereof. The conductive films
202A and 202B may be formed using a thermal compression process, a
PVD process, a CND process, a lamination process, a printing
process, one or more other application processes, or a combination
thereof.
[0053] However, embodiments of the disclosure are not limited
thereto. In some other embodiments, the conductive films 202A and
202B are not formed.
[0054] As shown in FIG. 2B, the conductive films 202A and 202B and
the board 200 are partially removed to form openings 204, in
accordance with some embodiments. In some embodiments, the openings
204 completely penetrate through the board 200 and the conductive
films 202A and 202B. The openings 204 may be formed using an energy
beam drilling process, a mechanical drilling process,
photolithography and etching processes, one or more other
applicable processes, or a combination thereof. The energy beam
drilling process may include a laser drilling process, an ion beam
drilling process, an electron beam drilling process, a plasma beam
drilling process, one or more other applicable processes, or a
combination thereof.
[0055] Afterwards, a seed layer is deposited over the structure
shown in FIG. 2B in accordance with some embodiments. The seed
layer extends over the conductive films 202A and 202B. The seed
layer further extends over sidewalk of the opening 204. Afterwards,
patterned photoresist layers are formed on the seed layer. The
patterned photoresist layers have openings that partially expose
the seed layer and define patterns of conductive features to be
formed on the board 200 later. Then, one or more conductive
materials are electroplated on the portions of the seed layer not
covered by the patterned photoresist layers. Afterwards, the
patterned photoresist layers are removed. One or more etching
processes are used to remove the portions of the seed laser
originally covered by the patterned photoresist layers. The
portions of the conductive films 202A and 202B originally covered
by the patterned photoresist layers are also removed during the one
or more etching processes.
[0056] As a result, the board 200 is partially exposed, as show t
in FIG. 2C, in accordance with some embodiments. The remaining
portions of the electroplated conductive material, the remaining
seed layer, and the remaining conductive films 202A and 202B
together form conductive features 206 with desired patterns. Some
of the conductive features 206 penetrate through the board 200 to
provide electrical connections between elements to be positioned on
the opposite surfaces of the board.
[0057] In some embodiments, some of the conductive features 206
together form one (or more) antenna element 207, as shown in FIG.
2C. The pattern of the antenna element 207 may be fine-tuned to
provide desired functions. In some embodiments, the antenna element
207 is a patch antenna that is used to receive and/or transmit
electromagnetic signals in normal direction. In some other
embodiments. the antenna element 207 is an end-fire antenna that is
used to receive and/or transmit electromagnetic signals in side
direction. In some embodiments, multiple antenna elements with
different functions are formed over the board 200.
[0058] As shown in FIG. 2C, a shielding element 208 is formed over
the bottom surface of the board 200, in accordance with some
embodiments. In some embodiments, one or more of the conductive
features 206 form the shielding element 208. In these cases, the
antenna element 207 and the shielding element 208 are formed from
patterning the same conductive material layer. The antenna element
207 and the shielding element 208 are made of the same material. In
some other embodiments, the. shielding element 208 and the
conductive features 206 are formed using different processes. In
some embodiments, the shielding element 208 and the antenna element
207 are made of different materials.
[0059] As shown in FIG. 2D, protective layers 210 and 212 are
formed over the opposite surfaces of the board 200, in accordance
with some embodiments. The protective layers 210 and 212 may be
made of or include epoxy-based resin, polyimide, polybenzoxazole,
one or t lore other suitable materials, or a combination thereof.
The protective layers 210 and 212 have multiple openings that
partially expose the conductive features 206. For example, the
antenna element 207 and the shielding element 208 are partially
exposed, as shown in FIG. 2D. The formation of the protective
layers 210 and 212 may involve a coating process and a
photolithography process. The coating process may include a spin
coating process, a spray coating process, a lamination process, one
or more other applicable processes, or a combination thereof.
[0060] As shown in FIG. 2E, conductive bumps 214 are formed over
some of the conductive features 206, in accordance with some
embodiments. In some embodiments, conductive bumps 214S are formed
over the exposed portions of the shielding element 208, as shown in
FIG. 2E. In some embodiments, the conductive bumps 214 and 214S are
made of the same material. In some embodiments, the conductive
bumps 214 and 214S are tin-containing solder elements. The
tin-containing solder elements may further include copper, silver,
gold, aluminum, lead, one or more other suitable materials, or a
combination thereof. In some embodiments, the tin-containing solder
elements are lead free. The formation of the conductive bumps 214
and 214S may involve one or more plating processes (such as
electroplating processes) and/or one or more reflow processes.
Afterwards, a singulation process may be carried out to saw through
the structure. As a result, multiple substrates 20 are formed. In
FIG. 2E, one of the substrates 20 is shown.
[0061] Referring back to FIG. 1C, the protective substrate 20 is
positioned to allow the conductive elements 214 to be substantially
aligned with the conductive structures 108, in accordance with some
embodiments. The protective substrate 20 is also positioned to
allow the conductive elements 214S to be substantially aligned with
the conductive structures 108S. As mentioned above, in some
embodiments, the conductive elements 214 and 214S are
tin-containing solder elements which may facilitate a subsequent
bonding process.
[0062] As shown in FIG. 1D, the protective substrate 20 is bonded
to the conductive structures 108 and 108S, in accordance with some
embodiments. In some embodiments, the protective substrate 20 is
bonded to the conductive structures 108 and 108S through the
conductive bumps 214 and 214S. As mentioned above, in some
embodiments, the conductive humps 214 and 214S are tin-containing
solder elements. A reflow process may be used to bond the
conductive bumps 214 and 214S to the conductive structures 108 and
108S, respectively. In some embodiments, after the protective
substrate 20 is bonded onto the conductive structures 214 and 214S,
the shielding element 208 is also disposed over the semiconductor
die 110A. The shielding element 208 is electrically connected to
the conductive structures 108S through the conductive bumps
214S.
[0063] The conductive structures 108S (which together function as a
shielding structure) and the shielding element 208 may be used to
prevent the electromagnetic wave generated by the semiconductor die
110A from affecting the operation of nearby device elements, such
as the semiconductor die 110B or another nearby package. In some
other cases where the conductive structures 108S or the shielding
element 208 are not formed, the electromagnetic wave ;venerated by
the semiconductor die 110A may negatively affect the operation of
the semiconductor die 110B or the operation of another nearby
device elements.
[0064] FIG. 3 is a top view of an intermediate stage of a process
for forming a chip package, in accordance with some embodiments. In
some embodiments, FIG. 3 shows the top view of the structure shower
in FIG. 1B. For simplicity and clarity, only the shielding
structure, the topmost insulating layer 104, and the semiconductor
dies 110A and 110B are illustrated.
[0065] As shown in FIG. 3, the conductive structures 108S surround
or encircle a space where the semiconductor die 110A is positioned,
in accordance with some embodiments. The semiconductor die 110B is
disposed outside of an area that is surrounded by the conductive
structures 108S. In some embodiments, the top view of each of the
conductive structures 108S has a circular profile. The conductive
structures 108S together form a shielding structure. The shielding
structure has multiple openings G that expose the space containing
the semiconductor die 110A. Therefore, during a subsequent
formation process of a protective layer, a portion of the
protective layer could penetrate through the openings G to surround
and protect the semiconductor die 110A.
[0066] In some embodiments, two nearby conductive structures 108S
are separated from each other by a distance W1, as shown in FIG. 3.
The distance W1 may be in a range from about 10 .mu.m to half the
wavelength of the electromagnetic wave generated by the
semiconductor die 110A. Each of the conductive structures 108S has
a width W2, as shown in FIG. 3. In some embodiments, the width W2
is in a range from about 5 .mu.m to about ten times the distance W1
to ensure sufficient shielding efficiency.
[0067] In some cases, if the distance W1 is smaller than about 10
.mu.m, the subsequently formed protective layer might not be able
to penetrate through the openings to protect the semiconductor die
110A. Alternatively, the subsequently formed protective layer might
not be able to completely surround and protect the semiconductor
die 110A. The reliability and quality of the chip package may be
negatively affected.
[0068] In some other cases, if the distance W1 is greater than half
the wavelength of the electromagnetic wave generated by the
semiconductor die 110A, the shielding efficiency may not be
sufficient. As a result, the electromagnetic wave generated by the
semiconductor die 110A during operation may not be well shielded
and may reach the nearby device elements (such as the semiconductor
die 110B or another e package) to negatively affect the
operation.
[0069] For example, the operation frequency of the semiconductor
die 110A may be about 28 GHz. In these cases, electromagnetic wave
having a wavelength of about 10.7 mm may be generated by the
semiconductor die 110A during operation. In these cases, half the
wavelength of the electromagnetic wave generated by the
semiconductor die 110A is about 5.35 mm. In some embodiments, the
distance W1 is designed to be in a range from about 10 .mu.m to
about 5.35 mm to ensure sufficient shielding efficiency and to
ensure sufficient protection of the semiconductor die 110A. In some
embodiments, the width W2 is designed to be in a range from about 5
.mu.m to about 53.5 mm.
[0070] However, embodiments of the disclosure are not limited
thereto. Many variations and/or modifications can be made to
embodiments of the disclosure. The top views of different
conductive structures may have different shapes.
[0071] FIG. 4 is a top view of an intermediate stage of a process
for forming a chip package, in accordance with some embodiments. In
some embodiments, FIG. 4 shows the top view of the structure shown
in FIG. 1B. For simplicity and clarity, only the shielding
structure, the topmost insulating layer 104, and the semiconductor
dies 110A and 110B are illustrated.
[0072] As shown in FIG. 4, the semiconductor die 110A is surrounded
by not only the conductive structures 108S but also the conductive
walls 108S', in accordance with some embodiments. In some
embodiments, a lateral extending direction of the conductive wails
108S' is substantially parallel to a lateral extending direction of
the side of the semiconductor die 110A. The conductive structures
108S and the conductive walls 108S' together function as a
shielding structure.
[0073] The shielding structure has multiple openings G that expose
the space containing the semiconductor die 110A. Therefore, during
a subsequent formation process of a protective layer, a portion of
the protective layer could penetrate through the openings G to
surround and protest the semiconductor die 110A. In some
embodiments, the distance between any nearby conductive structures
108S and/or conductive walls 108S' is in a range from about 10
.mu.m to half the wavelength of the electromagnetic wave generated
by the semiconductor die 110A.
[0074] Many variations and/or modifications can be made to
embodiments of the disclosure. FIG. 5 is a top view of an
intermediate stage of a process for forming a chip package, in
accordance with some embodiments. In some embodiments, FIG. 5 shows
the top view of the structure shown in FIG. 1B. For simplicity and
clarity, only the shielding structure, the topmost insulating layer
104, and the semiconductor dies 110A and 110B are illustrated.
[0075] In some embodiments, the top view of each of the conductive
structures 108S has an oval profile, as shown in FIG. 5. The
conductive structures 108S together form a shielding structure. The
shielding structure has multiple openings G that expose the space
containing the semiconductor die 110A. Therefore, during a
subsequent formation process of a protective layer, a portion of
the protective layer could penetrate through the openings G to
surround and protect the semiconductor die 110A. In some
embodiments, the distance between any nearby conductive structures
108S and/or conductive walls 108S' is in a range from about 10
.mu.m to half the wavelength of the electromagnetic leave generated
by the semiconductor die 110A.
[0076] Many variations and/or modifications can be made to
embodiments of the disclosure. FIG. 6 is a top view of an
intermediate stage of a process for forming a chip package, in
accordance with some embodiments. In some embodiments, FIG. 6 shows
the top view of the structure shown in FIG. 1B. For simplicity and
clarity, only the shielding structure, the topmost insulating layer
104, and the semiconductor dies 110A and 110B are illustrated.
[0077] In some embodiments, the semiconductor die 110 A is
surrounded by a single conductive wall 108S'' that functions as a
shielding structure. The shielding structure has an openings G that
expose the space containing the semiconductor die 110A. Therefore,
during a subsequent formation process of a protective layer, a
portion of the protective layer could penetrate through the
openings G to surround and protect the semiconductor die 110A. In
some embodiments, the width of the opening G is in a range from
about 10 .mu.m to half the wavelength of the electromagnetic wave
generated by the semiconductor die 110A.
[0078] Many variations and/or modifications can be made to
embodiments of the disclosure. FIG. 7 is a top view of an
intermediate stage of a process for forming a chip package, in
accordance with some embodiments. In some embodiments, FIG. 7 shows
the top view of the structure shown in FIG. 1B. For simplicity and
clarity, only the shielding structure, the topmost insulating layer
104, and the semiconductor dies 110A and 110B are illustrated.
[0079] In some embodiments, the top view of each of the conductive
structures 108S has an oval profile, as shown in FIG. 7. In some
embodiments, the long axis of one or each of the conductive
structures 108S extends along a direction that is substantially
parallel to the extending direction of the corresponding side of
the semiconductor die 110A, as shown in FIG. 7.
[0080] The conductive, structures 108S together form a shielding
structure. The shielding structure has multiple openings G that
expose the space containing the semiconductor die 110A. Therefore,
during a subsequent formation process of a protective layer, a
portion of the protective layer could penetrate through the
openings G to surround and protect the semiconductor die 110A. In
some embodiments, a distance between any nearby conductive
structures 108S and/or conductive walls 108S' is in a range from
about 10 .mu.m to half the wavelength of the electromagnetic wave
generated by the semiconductor die 110A.
[0081] In some embodiments, as mentioned above, the shielding
structure and the shielding element 208 are electrically connected
to each other. Therefore, the shielding structure (including the
conductive structures 108S and/or the conductive walls 108S') and
the shielding element 208 may together reduce or prevent the
electromagnetic interference (EMI) effect caused by the
semiconductor die 110A. Many variations and/or modifications can be
made to the shielding element 208, in accordance with some
embodiments. For example, the top view of the shielding element 208
has many variations.
[0082] FIG. 14 is a top view of a shielding element of a chip
package, in accordance with some embodiments. In some embodiments,
FIG. 14 shows the top view of the shielding element 208 shown in
FIG. 1D. In some embodiments, the shielding element 208 is a
conductive plate. In some embodiments, the conductive plate has no
opening or through-hole. In some embodiments, the shielding element
208 covers the shielding structure (including the conductive
structures 108S and/or the conductive walls 108S') and the
semiconductor die 110A.
[0083] Many variations and/or modifications can be made to
embodiments of the disclosure. FIG. 15 is a top view of a shielding
element of a chip package, in accordance with some embodiments. In
some embodiments, the shielding element 208 is a conductive mesh
with many through-holes G'. In some embodiments, each of the
through-holes G' is designed to have a width W3 that is in a range
from about 10 .mu.m to half the wavelength of the electromagnetic
Nave generated by the semiconductor die 110A. Therefore, the
shielding efficiency of the shielding element 208 is ensured.
[0084] In some other embodiments, the shielding element 208
includes a combination of a conductive plate and a conductive mesh.
For example, a portion of the shielding element 208 is a conductive
plate without through-holes G', and another portion of the
shielding element 208 is a conductive mesh with through-holes
G'.
[0085] Referring to FIG. 1E, a protective layer 118 is formed to
surround the semiconductor dies 110A and 110B and the conductive
structures 108S and 108, in accordance with some embodiments. In
some embodiments, the protective layer 118 penetrates through the
openings G (as shown in FIG. 3, 4, 5. 6, or 7) between the
conductive structures 108S to surround the semiconductor die 110A.
In some embodiments, the protective layer 118 is in direct contact
with the conductive structures 108 and 108S. In some embodiments,
the protective layer 118 is in direct contact with the
semiconductor dies 110A and 110B. In some embodiments, a portion of
the protective layer 118 is between the semiconductor die 110A and
the shielding element 208.
[0086] In some embodiments, the material of the protective layer
118 is different from that of the board 200. In some embodiments,
the protective layer 118 has a greater dielectric constant than
that of the board 200. In some embodiments, the protective layer
118 has a greater dissipation factor than that of the board
200.
[0087] In some embodiments, the protective layer 118 is made of or
includes a molding compound material. The molding compound material
nay include a polymer material, such as an epoxy-based resin with
fillers dispersed therein. In some embodiments, a liquid molding
compound material is introduced or injected between the protective
substrate 20 and the carrier substrate 100. The liquid molding
compound material may flow into the openings G to encapsulate the
semiconductor die 110A. A thermal process is then used to cure the
liquid molding compound material and to transform it into the
protective layer 118.
[0088] As shown in FIG. 1F, the carrier substrate 100 is removed,
and conductive bumps 120 are formed, in accordance with some
embodiments. In some embodiments, the conductive bumps 120 are or
include solder humps such as tin-containing solder humps. The
tin-containing solder bumps may further include copper, silver,
gold, aluminum, lead, one or more other suitable materials, or a
combination thereof. In some embodiments, the tin-containing solder
hump is lead free. In some embodiments, solder balls (or solder
elements) are disposed onto the exposed conductive features 106
after the removal of the carrier substrate 100. A reflow process is
then carrier out to melt the solder balls into the conductive humps
120. In some other embodiments, under bump metallization (UBM)
elements are formed over the exposed conductive features 106 before
the solder balls are disposed. In some other embodiments, solder
elements are electroplated onto the exposed conductive features
106. Afterwards, a reflow process is used to melt the solder
element to form the conductive bumps 120. In some embodiments, a
singulation process is then carrier out to saw through the formed
structure. As a result, multiple separate chip packages are formed.
In FIG. 1F, one of the chip packages is shown.
[0089] Many variations and/or modifications can be made to
embodiments of the disclosure. FIGS. 8A-8C are cross-sectional
views of various stages of a process for forming a chip package, in
accordance with some embodiments. As shown in FIG. 8A, a structure
similar to the structure shown in FIG. 1C is provided or formed, in
accordance with some embodiments.
[0090] In some embodiments, adhesive elements 802 are formed over
the semiconductor dies 110A and 110B before the protective
substrate 20 is bonded to the conductive structures 108 and 108S,
as shown in FIG. 8A. The adhesive elements 802 may include adhesive
tapes, adhesive glue, or other suitable elements.
[0091] As shown in FIG. 8B, the protective substrate 20 is bonded
to the conductive structures 108 and 108S, in accordance with some
embodiments. In some embodiments, the protective substrate 20 is
bonded to the conductive structures 108 and 108S through the
conductive bumps 214 and 214S. The adhesive elements 802 may assist
in the bonding process to prevent misalignment and/or undesired
displacement.
[0092] Afterwards, the processes the same as or similar to those
illustrated in FIGS. 1E and 1F are used to form a chip package, as
shown in FIG. 8C in accordance with some embodiments.
[0093] Many variations and/or modifications can be made to
embodiments of the disclosure. FIG. 9 is a cross-sectional view of
a chip package, in accordance with some embodiments. In some
embodiments, the chip package includes a single semiconductor die
(the semiconductor die 110A) that is surrounded by the conductive
structures 108S and the shielding element 208.
[0094] Many variations and/or modifications can be made to
embodiments of the disclosure. FIG. 10 is a cross-sectional view of
a chip package, in accordance with some embodiments. In some
embodiments, the chip package includes a single semiconductor die
(the semiconductor die 110A) that is surrounded by the conductive
structures 108S and the shielding element 208. As shown in FIG. 10.
the adhesive element 802 is formed between the semiconductor die
110A and the shielding element 208.
[0095] Many variations and/or modifications can be made to
embodiments of the disclosure. FIG. 11 is a cross-sectional view of
a chip package, in accordance with some embodiments. In some
embodiments, a structure the same as or similar to the structure
shown in FIG. 8C is provided or formed. Afterwards, the structure
is bonded onto a circuit board 804. In some embodiments, the
circuit board 804 is a printed circuit board. In some embodiments,
the circuit board 804 includes a shielding element 806.
[0096] Similar to the shielding element 208, the shielding element
806 may be a conductive plate, a conductive mesh, or a combination
thereof. The shielding element 806 may be used to further enhance
shielding efficiency. The conductive structures 108S (which
together function as a shielding structure), the shielding element
208, and the shielding element ma together be used to prevent the
electromagnetic wave generated by the semiconductor die 110A from
affecting the operation of nearby device elements, such as the
semiconductor the 110B or another nearby package
[0097] In some embodiments, the shielding element 208 is formed
between the board 200 and the semiconductor die 110A. However,
embodiments of the disclosure are not limited thereto. Many
variations and/or modifications can be made to embodiments of the
disclosure. In some other embodiments, the shielding element is
formed at another position.
[0098] FIG. 12 is a cross-sectional view of a chip package, in
accordance with some embodiments. In some embodiments, a shielding
element 208' is formed. The shielding element 208' has a first
portion positioned above the board 200 and a second portion
penetrating through the board 200. Therefore, in these cases, the
board 200 is positioned between the first portion of the shielding
element 208' and the semiconductor die 110A. The first portion of
the shielding element 208' is electrically connected to the
conductive structures 108S through conductive element 214S and the
second portion of the shielding element 208'. The material and
formation method of the shielding element 208' may be the same as
or similar to those of the shielding element 208 and/or the
conductive feature 206. Similar to the shielding element 208, the
shielding element 806 may be a conductive plate, a conductive mesh,
or a combination thereof.
[0099] Many variations and/or modifications can be made to
embodiments of the disclosure. FIG. 13 is a cross-sectional view of
a chip package, in accordance some embodiments. FIG. 13 shows a
cross-sectional view of a chip package that is similar to that
shown in FIG. 11. In some embodiments, the chip package further
includes one (or more) passive component 902. The passive component
902 may include a resistor, a capacitor, an inductor, one or more
other suitable elements, or a combination thereof.
[0100] Many variations and/or modification can be made to
embodiments of the disclosure. For example, the position and/or the
number of the antenna element may be modified. In some embodiments,
some of the conductive features 106 together function as an antenna
element. In some embodiments, some of the conductive structures 108
function as an antenna element. In some embodiments, multiple
antenna elements are formed.
[0101] Embodiments of the disclosure form a chip package with a
shielding structure. One or more conductive structures are formed
to surround an area where a semiconductor die is designed to be
positioned. The semiconductor die may include radio-frequency
circuits and would generate electromagnetic wave during operation.
The conductive structures surround the semiconductor die and
function as the shielding structure. Therefore, the generated
electromagnetic wave may be prevented from negatively affecting the
operation of nearby device elements. The quality and performance of
the chip package are significantly improved.
[0102] According to some embodiments, a method for forming a chip
package is provided. The method includes forming a plurality of
conductive structures over a carrier substrate. The method also
includes disposing a semiconductor die over the carrier substrate
such that the conductive structures surround the semiconductor die.
The method further includes disposing a shielding element over the
semiconductor die and the conductive structures. The shielding
element is electrically connected to the conductive structures.
[0103] In some embodiments, the method further includes for a
protective layer to surround the conductive structures and the
semiconductor die and bonding a protective substrate to the
conductive structures before the protective layer is formed. In
some embodiments, the method further includes forming the shielding
element over the protective substrate before bonding the protective
substrate to the conductive structures. In some embodiments, the
method further includes forming an antenna element over the
protective substrate. In some embodiments, the antenna. element is
formed over the protective substrate before bonding the protective
substrate to the conductive structures. In some embodiments, the
protective substrate is bonded to the conductive structures through
tin-containing solder elements.
[0104] In some embodiments, the method further includes introducing
a polymer material between the protective substrate and the carrier
substrate and curing the polymer material to form the protective
layer. In some embodiments, the method further includes forming a
redistribution structure over the carrier substrate before the
conductive structures are formed. In some embodiments, the method
further includes removing the carrier substrate and forming
conductive bumps over the redistribution structure, wherein the
redistribution structure is between the protective layer and the
conductive bumps. In some embodiments, the method further includes
disposing an additional semiconductor die over the carrier
substrate before the protective layer is formed, wherein the
additional semiconductor die is outside of an area surrounded by
the conductive structures. In some embodiments, the shielding
element includes a conductive plate, a conductive mesh, or a
combination thereof. In some embodiments, two of the conductive
structures are separated from each other by a distance, and the
distance is smaller than half a wavelength of an electromagnetic
wave generated by the semiconductor die.
[0105] According to some embodiments, a method for forming a chip
package is provided. The method includes forming a plurality of
conductive structures over a redistribution structure. The method
also includes disposing a semiconductor die over the redistribution
structure such that the conductive structures surround the
semiconductor die. Two of the conductive structures are separated
from each other by a distance, and the distance is smaller than
half a wavelength of an electromagnetic wave generated by the
semiconductor die.
[0106] In some embodiments, each of the conductive structures has a
width in a range from about 5 .mu.m to about ten times the
distance. In some embodiments, the method further includes forming
a protective layer to surround the conductive structures and the
semiconductor die and bonding a protective substrate to the
conductive structures before the protective layer is formed. In
some embodiments, the method further includes forming a shielding
element over the protective substrate before bonding the protective
substrate to the conductive structures.
[0107] According to some embodiments, a method for forming a chip
package is provided. The method includes disposing a first
semiconductor die and a second semiconductor die over the a
redistribution structure. The method also includes disposing a
plurality of conductive structures over the redistribution
structure. The conductive structures surround an area where the
first semiconductor die is positioned, and the second semiconductor
die is positioned outside of the area.
[0108] In some embodiments, two of the conductive structures are
separated from each other by a distance, and the distance is
smaller than half a wavelength of an electromagnetic wave generated
by the first semiconductor die. In some embodiments, the method
further includes disposing a shielding element over the first
semiconductor die, and the shielding element is electrically
connected to the conductive structures. In some embodiments, the
shielding element includes a conductive mesh having a plurality of
through-holes, and each of the through-holes has a width that is
smaller than half the wavelength of the electromagnetic wave
generated by the first semiconductor die.
[0109] The foregoing outlines features of several embodiments so
that those skilled in the art may better understand the aspects of
the present disclosure. Those skilled in the art should appreciate
that they may readily use the present disclosure as a basis for
designing or modifying other processes and structures for carrying
out the same purposes and/or achieving the same advantages of the
embodiments introduced herein. Those skilled in the art should also
realize that such equivalent constructions do not depart from the
spirit and scope of the present disclosure, and that they may make
various changes, substitutions, and alterations herein without
departing from the spirit and scope of the present disclosure.
* * * * *