U.S. patent application number 16/728452 was filed with the patent office on 2021-07-01 for trench capacitor profile to decrease substrate warpage.
The applicant listed for this patent is Taiwan Semiconductor Manufacturing Co., Ltd.. Invention is credited to Yu-Chi Chang, Hsin-Li Cheng, Tuo-Hsin Chien, Ting-Chen Hsu, Shih-Fen Huang, Alexander Kalnitsky, Jyun-Ying Lin, Shu-Hui Su, Felix Ying-Kit Tsui, Shi-Min Wu.
Application Number | 20210202761 16/728452 |
Document ID | / |
Family ID | 1000004589408 |
Filed Date | 2021-07-01 |
United States Patent
Application |
20210202761 |
Kind Code |
A1 |
Cheng; Hsin-Li ; et
al. |
July 1, 2021 |
TRENCH CAPACITOR PROFILE TO DECREASE SUBSTRATE WARPAGE
Abstract
Various embodiments of the present disclosure are directed
towards an integrated circuit (IC) including a pillar structure
abutting a trench capacitor. A substrate has sidewalls that define
a trench. The trench extends into a front-side surface of the
substrate. The trench capacitor includes a plurality of capacitor
electrode layers and a plurality of capacitor dielectric layers
that respectively line the trench and define a cavity within the
substrate. The pillar structure is disposed within the substrate.
The pillar structure has a first width and a second width less than
the first width. The first width is aligned with the front-side
surface of the substrate and the second width is aligned with a
first point disposed beneath the front-side surface.
Inventors: |
Cheng; Hsin-Li; (Hsin Chu,
TW) ; Lin; Jyun-Ying; (Wujie Township, TW) ;
Kalnitsky; Alexander; (San Francisco, CA) ; Huang;
Shih-Fen; (Jhubei, TW) ; Su; Shu-Hui; (Tucheng
City, TW) ; Hsu; Ting-Chen; (Taichung City, TW)
; Chien; Tuo-Hsin; (Zhubei City, TW) ; Tsui; Felix
Ying-Kit; (Cupertino, CA) ; Wu; Shi-Min;
(Changhua County, TW) ; Chang; Yu-Chi; (Kaohsiung
City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Taiwan Semiconductor Manufacturing Co., Ltd. |
Hsin-Chu |
|
TW |
|
|
Family ID: |
1000004589408 |
Appl. No.: |
16/728452 |
Filed: |
December 27, 2019 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/66181 20130101;
H01L 21/32139 20130101; H01L 29/945 20130101; H01L 21/02236
20130101; H01L 21/02164 20130101; H01L 28/92 20130101; H01L 28/91
20130101; H01L 23/562 20130101; H01L 21/764 20130101 |
International
Class: |
H01L 29/94 20060101
H01L029/94; H01L 49/02 20060101 H01L049/02; H01L 23/00 20060101
H01L023/00; H01L 21/764 20060101 H01L021/764; H01L 21/02 20060101
H01L021/02; H01L 21/3213 20060101 H01L021/3213; H01L 29/66 20060101
H01L029/66 |
Claims
1. An integrated circuit (IC) comprising: a substrate comprising
sidewalls that define a trench, wherein the trench extends into a
front-side surface of the substrate; a trench capacitor comprising
a plurality of capacitor electrode layers and a plurality of
capacitor dielectric layers that respectively line the trench and
define a cavity within the substrate; and a pillar structure
disposed within the substrate and abutting the trench, wherein the
pillar structure has a first width and a second width less than the
first width, wherein the first width is aligned with the front-side
surface of the substrate and the second width is aligned with a
first point disposed beneath the front-side surface.
2. The IC of claim 1, wherein the width of the pillar structure
continuously increases from the first point to a second point,
wherein the second point is disposed beneath the first point.
3. The IC of claim 2, wherein the width of the pillar structure
continuously decreases from the second point to a third point,
wherein the third point is disposed beneath the second point, and
wherein the third point is aligned with a lower surface of the
substrate that defines a bottom of the trench.
4. (canceled)
5. (canceled)
6. The IC of claim 1, wherein the plurality of capacitor dielectric
layers comprises an uppermost capacitor dielectric layer that
continuously lines the trench and seals the cavity within the
trench.
7. The IC of claim 1, further comprising: an insulator layer that
continuously extends from the front-side surface of the substrate
to the sidewalls of the substrate that define the trench, wherein
the insulator layer is disposed between the trench capacitor and
the substrate, wherein a thickness of the insulator layer is
greater than a thickness of the capacitor electrode layers and the
capacitor dielectric layers, respectively.
8. The IC of claim 7, wherein the insulator layer continuously
extends along sidewalls and an upper surface of the pillar
structure.
9. The IC of claim 7, wherein the insulator layer comprises a first
dielectric material and the capacitor dielectric layers comprise a
second dielectric material different than the first dielectric
material.
10. A semiconductor structure comprising: a substrate; a trench
capacitor comprising a plurality of capacitor electrode layers and
a plurality of capacitor dielectric layers overlying a front-side
surface of the substrate, wherein the capacitor electrode layers
and the capacitor dielectric layers define a first trench segment
and a second trench segment protruding into the substrate and
further define a first cavity and a second cavity recessed into the
substrate respectively at the first and second trench segments; and
a pillar structure disposed laterally between the first trench
segment and the second trench segment, wherein a width of the
pillar structure continuously decreases in a first direction from
the front-side surface towards a bottom surface of the first and
second trench segments.
11. The semiconductor structure of claim 10, wherein the pillar
structure comprises a first slanted sidewall segment, a second
slanted sidewall segment, and a third slanted sidewall segment,
wherein the second slanted sidewall segment is disposed vertically
between the first and third slanted sidewall segments, wherein the
first and third slanted sidewall segments are angled in a same
direction that is opposite a direction of an angle of the second
slanted sidewall segment.
12. The semiconductor structure of claim 10, wherein widths of the
first and second cavities continuously increase in the first
direction.
13. The semiconductor structure of claim 10, wherein the pillar
structure continuously decreases in the first direction along a
first vertical distance, wherein a first width of the pillar
structure is greater than the first vertical distance, and wherein
the first width is aligned with the front-side surface of the
substrate.
14. The semiconductor structure of claim 10, further comprising: an
insulator layer disposed between the substrate and the first and
second trench segments, wherein the insulator layer continuously
extends along sidewalls and an upper surface of the pillar
structure, wherein a thickness of the insulator layer continuously
increases in the first direction.
15. The semiconductor structure of claim 14, wherein the insulator
layer comprises silicon dioxide and the capacitor dielectric layers
respectively comprise a high-k dielectric material.
16. The semiconductor structure of claim 14, wherein a first
thickness of the insulator layer disposed along an upper surface of
the pillar structure is less than a second thickness of the
insulator layer disposed along a sidewall of the pillar
structure.
17. (canceled)
18. A method for forming a trench capacitor, the method comprising:
performing a first patterning process on a front-side surface of a
substrate to define an upper portion of a trench and an upper
portion of a pillar structure, wherein the first patterning process
is performed such that a width of the pillar structure decreases
from the front-side surface to a first point below the front-side
surface; performing a second patterning process on the substrate to
expand the trench and increase a height of the pillar structure;
and forming a plurality of capacitor dielectric layers and a
plurality of capacitor electrode layers within the trench such that
a cavity is defined between sidewalls of an uppermost capacitor
dielectric layer, wherein the cavity is disposed within the trench,
and wherein the uppermost capacitor dielectric layer seals the
cavity.
19. The method of claim 18, further comprising: forming a sidewall
protection layer along sidewalls of the substrate that define the
trench, wherein the sidewall protection layer is formed after the
first patterning process and before the second patterning
process.
20. The method of claim 18, wherein the second patterning process
is performed such that the width of the pillar structure
continuously decreases from a second point to a lower surface of
the substrate, wherein the second point is disposed vertically
beneath the first point and the lower surface of the substrate
defines a bottom surface of the trench.
21. The IC of claim 6, wherein the uppermost capacitor dielectric
layer comprises inner sidewalls that define the cavity.
22. The IC of claim 1, wherein a width of the cavity continuously
decreases from the first point in a direction towards a bottom
surface of the trench capacitor.
23. The semiconductor structure of claim 10, wherein the plurality
of capacitor dielectric layers comprises an uppermost capacitor
dielectric layer that abuts the first cavity and the second cavity,
wherein the uppermost capacitor dielectric layer seals the first
cavity and the second cavity.
Description
[0001] FIG. 1 illustrates a cross-sectional view of some
embodiments of an integrated circuit (IC) including a trench
capacitor disposed within a trench and laterally adjacent to a
cavity within the trench.
[0002] FIGS. 7-14 illustrate cross-sectional views of some
embodiments of a method of forming an integrated chip (IC) having a
trench capacitor disposed within a trench and laterally adjacent to
a cavity within the trench.
[0003] FIG. 15 illustrates a flowchart of some embodiments of a
method for forming an IC having a trench capacitor disposed within
a trench and laterally adjacent to a cavity within the trench.
[0004] In some embodiments, the pillar structure 101 has a first
width w1 that is aligned with the front-side surface 102f of the
semiconductor substrate 102, and further has a second width w2 that
is disposed vertically at a first point beneath the front-side
surface 102f. The first width w1 is greater than the second width
w2. In further embodiments, a width of the pillar structure 101
continuously decreases from the front-side surface 102f of the
semiconductor substrate 102 to the first point. This, in part,
ensures that a cavity 103 will exist in each of the trenches 102t.
For example, during fabrication of the trench capacitor 106, the
capacitor electrode layers 110a-d and the capacitor dielectric
layers 112a-d are deposited (e.g., by one or more ALD processes)
such that they will conform to a shape of the pillar structure 101.
Because the first width w1 of the pillar structure 101 is greater
than the second width w2 of the pillar structure 101, the cavity
103 will be present in each trench 102t after depositing the
capacitor electrode layers 110a-d and the capacitor dielectric
layers 112a-d.
[0005] In some embodiments, the first width w1 of the pillar
structure 101 is within a range of about 0.1 to 0.2 micrometers. In
further embodiments, if the first width w1 is less than about 0.1
micrometers, then the pillar structure 101 is too thin such that it
may collapse due to force applied by layers of the trench capacitor
106. In yet further embodiments, if the first width w1 is greater
than about 0.2 micrometers, then a number of trenches 102t that may
be formed within the semiconductor substrate 102 is reduced and/or
an opening of each trench 102t is too small to facilitate proper
deposition of layers of the trench capacitor 106 within the
trenches 102t. In various embodiments, the second width w2 of the
pillar structure 101 is within a range of about 0.07 to 0.17
micrometers. In further embodiments, if the second width w2 is less
than about 0.07 micrometers, then the pillar structure 101 is too
thin such that it may collapse due to force applied by layers of
the trench capacitor 106. In yet further embodiments, if the second
width w2 is greater than about 0.17 micrometers, then a size of the
cavity 103 may be reduced. In such embodiments, reduction of the
size of the cavity 103 increases a stress applied to the
semiconductor substrate 102 as the capacitor electrode layers
110a-d and capacitor dielectric layers 112a-d expand, thereby
resulting in warpage and/or cracking of the semiconductor substrate
102. In various embodiments, the first width w1 is greater than the
second width w2. In further embodiments, a difference between the
first width w1 and the second width w2 (e.g., w1-w2) is greater
than about 30 nanometers. In some embodiments, if the difference
between the first width w1 and the second width w2 is less than
about 30 nanometers, then the size of the cavity 103 may be
reduced, thereby resulting in warpage and/or cracking of the
semiconductor substrate 102.
[0006] The IC 200 includes an interconnect structure 117 overlying
a front-side surface 102f of a semiconductor substrate 102. In some
embodiments, the semiconductor substrate 102 may, for example, be
or comprise a bulk substrate (e.g., bulk silicon), a
silicon-on-insulator (SOI) substrate, or another suitable substrate
and/or may comprise a first doping type (e.g., p-type). A doped
region 104 is disposed within the semiconductor substrate 102 and
may comprise the first doping type with a higher doping
concentration than the semiconductor substrate 102. The
interconnect structure 117 includes an interconnect dielectric
structure 122, a plurality of conductive vias 118, and a plurality
of conductive wires 120. The interconnect dielectric structure 122
may, for example, include one or more inter-level dielectric (ILD)
layers. The one or more ILD layers may, for example, respectively
be or comprise an oxide, such as silicon dioxide, a low-k
dielectric material, an extreme low-k dielectric material, any
combination of the foregoing, or another suitable dielectric
material. The plurality of conductive vias and wires 118, 120 are
configured to electrically couple semiconductor devices disposed
over and/or within the semiconductor substrate 102 to one another.
In further embodiments, the conductive vias and wires 118, 120 may,
for example, respectively be or comprise tungsten, copper,
aluminum, titanium nitride, tantalum nitride, any combination of
the foregoing, or the like.
[0007] The pillar structure 101 has a first width w1 that is
horizontally aligned with the front-side surface 102f of the
semiconductor substrate 102, and further has a second width w2 that
is disposed at a first point 202 vertically offset from the
front-side surface 102f. In some embodiments, the first width w1 is
greater than the second width w2. Further, the width of the pillar
structure 101 may continuously decrease from the front-side surface
102f of the semiconductor substrate 102 to the first point 202. In
further embodiments, a first height h1 of the pillar structure 101
is defined from the front-side surface 102f of the semiconductor
substrate 102 to the first point 202. In yet further embodiments,
the first height h1 is, for example, greater than 0.05 micrometers
or within a range of about 0.05 to 4 micrometers. In further
embodiments, if, for example, the first height h1 is less than 0.05
micrometers, then a size of the cavity 103 may be reduced which may
increase an amount of stress induced on the semiconductor substrate
102. In yet further embodiments, the width of the pillar structure
101 continuously decreases across the first height h1 in a
direction away from the front-side surface 102f of the
semiconductor substrate 102. In some embodiments, the first width
w1 of the pillar structure 101 is within a range of about 0.1 to
0.2 micrometers. In various embodiments, the second width w2 of the
pillar structure 101 is within a range of about 0.07 to 0.17
micrometers. In some embodiments, a first length L1 of the trench
102t is within a range of about 0.3 to 0.4 micrometers. The first
length L1 is aligned with the front-side surface 102f of the
semiconductor substrate 102 and may define an opening of the trench
102t. In some embodiments, if the first length L1 is less than
about 0.3 micrometers, then an opening of the trench 102t is too
small such that layers of the trench capacitor 106 may not properly
be deposited within the trench 102t. In further embodiments, if the
first length L1 is greater than about 0.4 micrometers, then a
number of trenches 102t that may be formed within the semiconductor
substrate 102 is reduced and/or the first width w1 is reduced such
that the pillar structure 101 is too thin and may collapse due to
force applied by layers of the trench capacitor 106. In some
embodiments, a trench pitch of the trench 102t is equal to the sum
of the first width w1 of the pillar structure 101 and the first
length L1 of the trench 102t (e.g., w1+L1). In some embodiments,
the trench pitch is within a range of about 0.4 to 0.6 micrometers.
In further embodiments, if the trench pitch is less than about 0.4
micrometers, then the opening of the trench 102t may be too small
such that the layers of the trench capacitor may not properly fill
the trench 102t. In yet further embodiments, if the trench pitch is
greater than about 0.6 micrometers, then a capacitance density of
the trench capacitor 106 may be reduced.
[0008] A second height h2 of the pillar structure 101 is defined
from the front-side surface 102f of the semiconductor substrate 102
to a second point 204. The second point 204 is disposed vertically
beneath the first point 202 in a direction away from the front-side
surface 102f. In some embodiments, the second height h2 is, for
example, about 6 micrometers, or within a range of about 0.595 to
7.65 micrometers. In some embodiments, a width of the pillar
structure 101 continuously increases from the first point 202 to
the second point 204. A third height h3 of the pillar structure 101
is defined from the front-side surface 102f of the semiconductor
substrate 102 to a third point 206. The third point 206 may be
aligned with a lower surface 102ls of the semiconductor substrate
102. In some embodiments, the lower surface 102ls of the
semiconductor substrate 102 defines a bottom surface of the trench
102t and/or is aligned with a bottom surface of the trench segments
106ts. In some embodiments, the third height h3 may be about 7
micrometers, about 8.5 micrometers, or within a range of about 6.5
to 8.5 micrometers. A second length L2 of the trench 102t is
aligned with the second point 204. In some embodiments, the second
length L2 is within a range of about 0.21 to 0.36 micrometers. In
further embodiments, the second length L2 is within a range of
about 70 to 90 percent of the first length L1 (e.g., within a range
of about 0.7*L1 to 0.9*L1). A third length L3 of the trench 102t is
aligned with the third point 206 and/or is aligned with the lower
surface 102ls of the semiconductor substrate 102. In some
embodiments, the third length L3 is within a range of about 0.3 to
0.4 micrometers or within a range of about 0.24 to 0.4 micrometers.
In further embodiments, the third length L3 is within a range of
about 80 to 100 percent of the first length L1 (e.g., within a
range of about 0.8*L1 to L1). Thus, in some embodiments, the third
length L3 is substantially equal to the first length L1. In some
embodiments, if the third length L3 is less than about 0.8*L1, then
a size of the cavity 103 is reduced which may increase an amount of
stress induced on the semiconductor substrate 102. In further
embodiments, if the third length L3 is greater than the first
length L1, then the layers of the trench capacitor 106 may not be
properly disposed along a corner of the trench 102t. This, in part,
may result in delamination between the capacitor dielectric layers
112a-d and/or the capacitor electrode layers 110a-d.
[0009] A third angle 902 is defined between a sidewall of the
pillar structure 101 and a substantially horizontal line 904. In
some embodiments, the substantially horizontal line 904 is
horizontally aligned with the second point 204 and is parallel with
the front-side surface 102f of the semiconductor substrate 102. In
some embodiments, the third angle 902 is within a range of about 90
to 93 degrees. The third height h3 of the pillar structure 101 is
defined from the front-side surface 102f of the semiconductor
substrate 102 to the third point 206. The third point 206 may be
aligned with the lower surface 102ls of the semiconductor substrate
102. In some embodiments, the third height h3 may be about 7
micrometers, about 8.5 micrometers, or within a range of about 6.5
to 8.5 micrometers. In yet further embodiments, after performing
the one or more dry etches of FIG. 9, a removal process (e.g., a
wet etch) may be performed to remove the sidewall protection layer
802. In further embodiments, the sidewall protection layer 802 may
remain in place during the patterning process of FIG. 9, such that
the sidewall protection layer 802 may prevent damage to sidewalls
of the semiconductor substrate 102 that define an upper portion of
the trench 102t and/or the pillar structure 101 (e.g., the region
between the front-side surface 102f and the second point 204). This
in turn may ensure the dimensions (e.g., w1, w2, L1, h1, h2, and/or
L2) defined by the patterning process of FIG. 7 are not
substantially changed during the patterning process of FIG. 9. In
further embodiments, the patterning processes of FIGS. 7 and 9 are
performed such that the trenches 102t respectively have a high
aspect ratio (e.g., an aspect ratio greater than about 20:1).
[0010] As illustrated in cross-sectional view 1100 of FIG. 11, the
capacitor electrode layers 110a-d and/or capacitor dielectric
layers 112a-d are patterned, thereby defining a trench capacitor
106. In some embodiments, a process for patterning each capacitor
electrode layer 110a-d and/or capacitor dielectric layer 112a-d
includes: forming a masking layer (not shown) over the target
capacitor electrode layer and/or capacitor dielectric layer;
exposing unmasked regions of the target capacitor electrode layer
and/or capacitor dielectric layer to one or more etchants, thereby
reducing a width of the target layer(s); and performing a removal
process (e.g., a wet etch process) to remove the masking layer. For
example, a first patterning process according to a first masking
layer (not shown) may be performed on a first capacitor electrode
layer 110a, a second patterning process according to a second
masking layer (not shown) may be performed on a second capacitor
electrode layer 110b and a first capacitor dielectric layer 112a,
and additional patterning processes may be performed for the
remaining capacitor layers. Further, an etch stop layer 116 is
formed over an upper surface of the trench capacitor 106. In some
embodiments, the etch stop layer 116 may be deposited by CVD, PVD,
ALD, or another suitable growth or deposition process. In some
embodiments, the etch stop layer 116 may, for example, be or
comprise silicon nitride, silicon carbide, or another suitable
dielectric material.
[0011] FIG. 15 illustrates a method 1500 of forming an integrated
circuit (IC) including a trench capacitor disposed within a trench
and laterally adjacent to a cavity within the trench according to
the present disclosure. Although the method 1500 is illustrated
and/or described as a series of acts or events, it will be
appreciated that the method is not limited to the illustrated
ordering or acts. Thus, in some embodiments, the acts may be
carried out in different orders than illustrated, and/or may be
carried out concurrently. Further, in some embodiments, the
illustrated acts or events may be subdivided into multiple acts or
events, which may be carried out at separate times or concurrently
with other acts or sub-acts. In some embodiments, some illustrated
acts or events may be omitted, and other un-illustrated acts or
events may be included.
* * * * *