U.S. patent application number 16/240166 was filed with the patent office on 2020-07-09 for fin trim plug structures for imparting channel stress.
The applicant listed for this patent is Intel Corporation. Invention is credited to Tahir GHANI, Biswajeet GUHA, Leonard GULER, Nick LINDERT, Swaminathan SIVAKUMAR.
Application Number | 20200220016 16/240166 |
Document ID | / |
Family ID | 71104446 |
Filed Date | 2020-07-09 |
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United States Patent
Application |
20200220016 |
Kind Code |
A1 |
GULER; Leonard ; et
al. |
July 9, 2020 |
FIN TRIM PLUG STRUCTURES FOR IMPARTING CHANNEL STRESS
Abstract
Fin trim plug structures for imparting channel stress are
described. In an example, an integrated circuit structure includes
a fin including silicon, the fin having a top and sidewalls. The
fin has a trench separating a first fin portion and a second fin
portion. A first gate structure including a gate electrode is over
the top of and laterally adjacent to the sidewalls of the first fin
portion. A second gate structure including a gate electrode is over
the top of and laterally adjacent to the sidewalls of the second
fin portion. An isolation structure is in the trench of the fin,
the isolation structure between the first gate structure and the
second gate structure. The isolation structure includes a first
dielectric material laterally surrounding a recessed second
dielectric material distinct from the first dielectric material,
the recessed second dielectric material laterally surrounding an
oxidation catalyst layer.
Inventors: |
GULER; Leonard; (Hillsboro,
OR) ; LINDERT; Nick; (Portland, OR) ; GUHA;
Biswajeet; (Hillsboro, OR) ; SIVAKUMAR;
Swaminathan; (Beaverton, OR) ; GHANI; Tahir;
(Portland, OR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Intel Corporation |
Santa Clara |
CA |
US |
|
|
Family ID: |
71104446 |
Appl. No.: |
16/240166 |
Filed: |
January 4, 2019 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 27/0886 20130101;
H01L 21/823431 20130101; H01L 29/66795 20130101; H01L 29/7846
20130101; H01L 29/6681 20130101; H01L 29/0653 20130101; H01L
29/41791 20130101; H01L 29/7854 20130101; H01L 29/785 20130101;
H01L 29/7849 20130101 |
International
Class: |
H01L 29/78 20060101
H01L029/78; H01L 29/417 20060101 H01L029/417; H01L 21/8234 20060101
H01L021/8234; H01L 29/06 20060101 H01L029/06; H01L 29/66 20060101
H01L029/66; H01L 27/088 20060101 H01L027/088 |
Claims
1. An integrated circuit structure, comprising: a fin comprising
silicon, the fin having a top and sidewalls, wherein the fin has a
trench separating a first fin portion and a second fin portion; a
first gate structure comprising a gate electrode over the top of
and laterally adjacent to the sidewalls of the first fin portion; a
second gate structure comprising a gate electrode over the top of
and laterally adjacent to the sidewalls of the second fin portion;
and an isolation structure in the trench of the fin, the isolation
structure between the first gate structure and the second gate
structure, wherein the isolation structure comprises a first
dielectric material laterally surrounding a recessed second
dielectric material distinct from the first dielectric material,
the recessed second dielectric material laterally surrounding an
oxidation catalyst layer.
2. The integrated circuit structure of claim 1, wherein the
oxidation catalyst layer comprises aluminum oxide.
3. The integrated circuit structure of claim 1, wherein the
oxidation catalyst layer comprises lanthanum oxide.
4. The integrated circuit structure of claim 1, wherein the
isolation structure further comprises a third dielectric material
laterally surrounded by an upper portion of the first dielectric
material, the third dielectric material on an upper surface of the
oxidation catalyst layer.
5. The integrated circuit structure of claim 4, wherein the third
dielectric material is further on an upper surface of the second
dielectric material.
6. The integrated circuit structure of claim 1, wherein the
oxidation catalyst layer has an upper surface co-planar with an
upper surface of the second dielectric material.
7. The integrated circuit structure of claim 1, wherein the
oxidation catalyst layer has an upper surface above an upper
surface of the second dielectric material.
8. An integrated circuit structure, comprising: a fin comprising
silicon, the fin having a top and sidewalls, wherein the top has a
longest dimension along a direction; a first isolation structure
over a first end of the fin; a gate structure comprising a gate
electrode over the top of and laterally adjacent to the sidewalls
of a region of the fin, wherein the gate structure is spaced apart
from the first isolation structure along the direction; and a
second isolation structure over a second end of the fin, the second
end opposite the first end, the second isolation structure spaced
apart from the gate structure along the direction, wherein the
first isolation structure and the second isolation structure both
comprise a first dielectric material laterally surrounding a
recessed second dielectric material distinct from the first
dielectric material, the recessed second dielectric material
laterally surrounding an oxidation catalyst layer.
9. The integrated circuit structure of claim 8, wherein the
isolation structure further comprises a third dielectric material
laterally surrounded by an upper portion of the first dielectric
material, the third dielectric material on an upper surface of the
oxidation catalyst layer.
10. The integrated circuit structure of claim 9, wherein the third
dielectric material is further on an upper surface of the second
dielectric material.
11. The integrated circuit structure of claim 8, wherein the
oxidation catalyst layer has an upper surface co-planar with an
upper surface of the second dielectric material.
12. The integrated circuit structure of claim 8, wherein the
oxidation catalyst layer has an upper surface above an upper
surface of the second dielectric material.
13. The integrated circuit structure of claim 8, wherein the first
and second isolation structures induce a compressive stress on the
fin.
14. The integrated circuit structure of claim 13, wherein the gate
electrode is a P-type gate electrode.
15. The integrated circuit structure of claim 8, wherein the first
isolation structure has a width along the direction, the gate
structure has the width along the direction, and the second
isolation structure has the width along the direction.
16. The integrated circuit structure of claim 15, wherein a center
of the gate structure is spaced apart from a center of the first
isolation structure by a pitch along the direction, and a center of
the second isolation structure is spaced apart from the center of
the gate structure by the pitch along the direction.
17. The integrated circuit structure of claim 8, wherein the first
and second isolation structures are both in a corresponding trench
in an inter-layer dielectric layer.
18. The integrated circuit structure of claim 8, further
comprising: a first source or drain region between the gate
structure and the first isolation structure; and a second source or
drain region between the gate structure and the second isolation
structure.
19. The integrated circuit structure of claim 18, wherein the first
and second source or drain regions are embedded source or drain
regions comprising silicon and germanium.
20. The integrated circuit structure of claim 8, wherein the gate
structure further comprises a high-k dielectric layer between the
gate electrode and the fin and along sidewalls of the gate
electrode.
21. The integrated circuit structure of claim 8, wherein the
oxidation catalyst layer comprises aluminum oxide or lanthanum
oxide.
22. A method of fabricating an integrated circuit structure, the
method comprising: forming a fin comprising silicon; exposing a
portion of the fin; etching the portion of the fin to form a trench
separating a first fin portion and a second fin portion; forming a
layer comprising silicon in the trench; forming an oxidation
catalyst layer on the layer comprising silicon; and oxidizing the
layer comprising silicon in the presence of the oxidation catalyst
layer.
23. The method of claim 22, further comprising: recessing the layer
comprising silicon in the trench prior to forming the oxidation
catalyst layer.
24. The method of claim 22, wherein oxidizing the layer comprising
silicon in the presence of the oxidation catalyst layer comprises
using a wet oxidation process.
Description
TECHNICAL FIELD
[0001] Embodiments of the disclosure are in the field of advanced
integrated circuit structure fabrication and, in particular, fin
trim plug structures for imparting channel stress and methods of
fabricating fin trim plug structures for imparting channel
stress.
BACKGROUND
[0002] For the past several decades, the scaling of features in
integrated circuits has been a driving force behind an ever-growing
semiconductor industry. Scaling to smaller and smaller features
enables increased densities of functional units on the limited real
estate of semiconductor chips. For example, shrinking transistor
size allows for the incorporation of an increased number of memory
or logic devices on a chip, lending to the fabrication of products
with increased capacity. The drive for ever-more capacity, however,
is not without issue. The necessity to optimize the performance of
each device becomes increasingly significant.
[0003] Variability in conventional and currently known fabrication
processes may limit the possibility to further extend them into the
10 nanometer node or sub-10 nanometer node range. Consequently,
fabrication of the functional components needed for future
technology nodes may require the introduction of new methodologies
or the integration of new technologies in current fabrication
processes or in place of current fabrication processes.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] FIGS. 1A and 1B illustrate plan views representing various
operations in a method of patterning of fins with multi-gate
spacing for forming a local isolation structure, in accordance with
an embodiment of the present disclosure.
[0005] FIGS. 2A-2D illustrate plan views representing various
operations in a method of patterning of fins with single gate
spacing for forming a local isolation structure, in accordance with
another embodiment of the present disclosure.
[0006] FIG. 3 illustrates a cross-sectional view of an integrated
circuit structure having a fin with multi-gate spacing for local
isolation, in accordance with an embodiment of the present
disclosure.
[0007] FIG. 4A illustrates a cross-sectional view of an integrated
circuit structure having a fin with single gate spacing for local
isolation, in accordance with another embodiment of the present
disclosure.
[0008] FIG. 4B illustrates a cross-sectional view showing locations
where a fin isolation structure may be formed in place of a gate
electrode, in accordance with an embodiment of the present
disclosure.
[0009] FIGS. 5A-5C illustrate various depth possibilities for a fin
cut fabricated using fin trim isolation approach, in accordance
with an embodiment of the preset disclosure.
[0010] FIG. 6 illustrates a plan view and corresponding
cross-sectional view taken along the a-a' axis showing possible
options for the depth of local versus broader locations of fin cuts
within a fin, in accordance with an embodiment of the present
disclosure.
[0011] FIGS. 7A and 7B illustrate cross-sectional views of various
operations in a method of selecting fin end stressor locations at
ends of a fin that has a broad cut, in accordance with an
embodiment of the present disclosure.
[0012] FIGS. 8A and 8B illustrate cross-sectional views of various
operations in a method of selecting fin end stressor locations at
ends of a fin that has a local cut, in accordance with an
embodiment of the present disclosure.
[0013] FIGS. 9A-9H illustrate cross-sectional views of various
operation in a method of fabricating an integrated circuit
structure having fin trim dielectric plugs, in accordance with an
embodiment of the present disclosure.
[0014] FIG. 10 illustrates a cross-sectional view of a structure
having fin trim plug structures at all possible locations for
demonstrative purposes, in accordance with an embodiment of the
present disclosure.
[0015] FIG. 11 illustrates an angled view of a fin having
compressive uniaxial stress, in accordance with an embodiment of
the present disclosure.
[0016] FIGS. 12A and 12B illustrate plan views representing various
operations in a method of patterning of fins with single gate
spacing for forming a local isolation structure in select gate line
cut locations, in accordance with an embodiment of the present
disclosure.
[0017] FIGS. 13A-13C illustrate cross-sectional views of various
possibilities for dielectric plugs for poly cut and fin trim
isolation (FTI) local fin cut locations and poly cut only locations
for various regions of the structure of FIG. 12B, in accordance
with an embodiment of the present disclosure.
[0018] FIG. 14 illustrates a computing device in accordance with
one implementation of the disclosure.
[0019] FIG. 15 illustrates an interposer that includes one or more
embodiments of the disclosure.
[0020] FIG. 16 is an isometric view of a mobile computing platform
employing an IC fabricated according to one or more processes
described herein or including one or more features described
herein, in accordance with an embodiment of the present
disclosure.
[0021] FIG. 17 illustrates a cross-sectional view of a flip-chip
mounted die, in accordance with an embodiment of the present
disclosure.
DESCRIPTION OF THE EMBODIMENTS
[0022] Advanced integrated circuit structure fabrication is
described. In the following description, numerous specific details
are set forth, such as specific integration and material regimes,
in order to provide a thorough understanding of embodiments of the
present disclosure. It will be apparent to one skilled in the art
that embodiments of the present disclosure may be practiced without
these specific details. In other instances, well-known features,
such as integrated circuit design layouts, are not described in
detail in order to not unnecessarily obscure embodiments of the
present disclosure. Furthermore, it is to be appreciated that the
various embodiments shown in the Figures are illustrative
representations and are not necessarily drawn to scale.
[0023] The following detailed description is merely illustrative in
nature and is not intended to limit the embodiments of the subject
matter or the application and uses of such embodiments. As used
herein, the word "exemplary" means "serving as an example,
instance, or illustration." Any implementation described herein as
exemplary is not necessarily to be construed as preferred or
advantageous over other implementations. Furthermore, there is no
intention to be bound by any expressed or implied theory presented
in the preceding technical field, background, brief summary or the
following detailed description.
[0024] This specification includes references to "one embodiment"
or "an embodiment." The appearances of the phrases "in one
embodiment" or "in an embodiment" do not necessarily refer to the
same embodiment. Particular features, structures, or
characteristics may be combined in any suitable manner consistent
with this disclosure.
[0025] Terminology. The following paragraphs provide definitions or
context for terms found in this disclosure (including the appended
claims):
[0026] "Comprising." This term is open-ended. As used in the
appended claims, this term does not foreclose additional structure
or operations.
[0027] "Configured To." Various units or components may be
described or claimed as "configured to" perform a task or tasks. In
such contexts, "configured to" is used to connote structure by
indicating that the units or components include structure that
performs those task or tasks during operation. As such, the unit or
component can be said to be configured to perform the task even
when the specified unit or component is not currently operational
(e.g., is not on or active). Reciting that a unit or circuit or
component is "configured to" perform one or more tasks is expressly
intended not to invoke 35 U.S.C. .sctn. 112, sixth paragraph, for
that unit or component.
[0028] "First," "Second," etc. As used herein, these terms are used
as labels for nouns that they precede, and do not imply any type of
ordering (e.g., spatial, temporal, logical, etc.).
[0029] "Coupled"--The following description refers to elements or
nodes or features being "coupled" together. As used herein, unless
expressly stated otherwise, "coupled" means that one element or
node or feature is directly or indirectly joined to (or directly or
indirectly communicates with) another element or node or feature,
and not necessarily mechanically.
[0030] In addition, certain terminology may also be used in the
following description for the purpose of reference only, and thus
are not intended to be limiting. For example, terms such as
"upper", "lower", "above", and "below" refer to directions in the
drawings to which reference is made. Terms such as "front", "back",
"rear", "side", "outboard", and "inboard" describe the orientation
or location or both of portions of the component within a
consistent but arbitrary frame of reference which is made clear by
reference to the text and the associated drawings describing the
component under discussion. Such terminology may include the words
specifically mentioned above, derivatives thereof, and words of
similar import.
[0031] "Inhibit"--As used herein, inhibit is used to describe a
reducing or minimizing effect. When a component or feature is
described as inhibiting an action, motion, or condition it may
completely prevent the result or outcome or future state
completely. Additionally, "inhibit" can also refer to a reduction
or lessening of the outcome, performance, or effect which might
otherwise occur. Accordingly, when a component, element, or feature
is referred to as inhibiting a result or state, it need not
completely prevent or eliminate the result or state.
[0032] Embodiments described herein may be directed to
front-end-of-line (FEOL) semiconductor processing and structures.
FEOL is the first portion of integrated circuit (IC) fabrication
where the individual devices (e.g., transistors, capacitors,
resistors, etc.) are patterned in the semiconductor substrate or
layer. FEOL generally covers everything up to (but not including)
the deposition of metal interconnect layers. Following the last
FEOL operation, the result is typically a wafer with isolated
transistors (e.g., without any wires).
[0033] Embodiments described herein may be directed to back end of
line (BEOL) semiconductor processing and structures. BEOL is the
second portion of IC fabrication where the individual devices
(e.g., transistors, capacitors, resistors, etc.) get interconnected
with wiring on the wafer, e.g., the metallization layer or layers.
BEOL includes contacts, insulating layers (dielectrics), metal
levels, and bonding sites for chip-to-package connections. In the
BEOL part of the fabrication stage contacts (pads), interconnect
wires, vias and dielectric structures are formed. For modern IC
processes, more than 10 metal layers may be added in the BEOL.
[0034] Embodiments described below may be applicable to FEOL
processing and structures, BEOL processing and structures, or both
FEOL and BEOL processing and structures. In particular, although an
exemplary processing scheme may be illustrated using a FEOL
processing scenario, such approaches may also be applicable to BEOL
processing. Likewise, although an exemplary processing scheme may
be illustrated using a BEOL processing scenario, such approaches
may also be applicable to FEOL processing.
[0035] In accordance with one or more embodiments described herein,
fin-trim isolation (FTI) and single gate spacing for isolated fins
is described. Non-planar transistors which utilize a fin of
semiconductor material protruding from a substrate surface employ a
gate electrode that wraps around two, three, or even all sides of
the fin (i.e., dual-gate, tri-gate, nanowire transistors). Source
and drain regions are typically then formed in the fin, or as
re-grown portions of the fin, on either side of the gate electrode.
To isolate a source or drain region of a first non-planar
transistor from a source or drain region of an adjacent second
non-planar transistor, a gap or space may be formed between two
adjacent fins. Such an isolation gap generally requires a masked
etch of some sort. Once isolated, a gate stack is then patterned
over the individual fins, again typically with a masked etch of
some sort (e.g., a line etch or an opening etch depending on the
specific implementation).
[0036] One potential issue with the fin isolation techniques
described above is that the gates are not self-aligned with the
ends of the fins, and alignment of the gate stack pattern with the
semiconductor fin pattern relies on overlay of these two patterns.
As such, lithographic overlay tolerances are added into the
dimensioning of the semiconductor fin and the isolation gap with
fins needing to be of greater length and isolation gaps larger than
they would be otherwise for a given level of transistor
functionality. Device architectures and fabrication techniques that
reduce such over-dimensioning therefore offer highly advantageous
improvements in transistor density.
[0037] Another potential issue with the fin isolation techniques
described in the above is that stress in the semiconductor fin
desirable for improving carrier mobility may be lost from the
channel region of the transistor where too many fin surfaces are
left free during fabrication, allowing fin strain to relax. Device
architectures and fabrication techniques that maintain higher
levels of desirable fin stress therefore offer advantageous
improvements in non-planar transistor performance.
[0038] In accordance with an embodiment of the present disclosure,
through-gate fin isolation architectures and techniques are
described herein. In the exemplary embodiments illustrated,
non-planar transistors in a microelectronic device, such as an
integrated circuit (IC) are isolated from one another in a manner
that is self-aligned to gate electrodes of the transistors.
Although embodiments of the present disclosure are applicable to
virtually any IC employing non-planar transistors, exemplary ICs
include, but are not limited to, microprocessor cores including
logic and memory (SRAM) portions, RFICs (e.g., wireless ICs
including digital baseband and analog front end modules), and power
ICs.
[0039] In embodiments, two ends of adjacent semiconductor fins are
electrically isolated from each other with an isolation region that
is positioned relative to gate electrodes with the use of only one
patterning mask level. In an embodiment, a single mask is employed
to form a plurality of sacrificial placeholder stripes of a fixed
pitch, a first subset of the placeholder stripes define a location
or dimension of isolation regions while a second subset of the
placeholder stripes defines a location or dimension of a gate
electrode. In certain embodiments, the first subset of placeholder
stripes is removed and isolation cuts made into the semiconductor
fins in the openings resulting from the first subset removal while
the second subset of the placeholder stripes is ultimately replaced
with non-sacrificial gate electrode stacks. Since a subset of
placeholders utilized for gate electrode replacement are employed
to form the isolation regions, the method and resulting
architecture is referred to herein as "through-gate" isolation. One
or more through-gate isolation embodiments described herein may,
for example, enable higher transistor densities and higher levels
of advantageous transistor channel stress.
[0040] With isolation defined after placement or definition of the
gate electrode, a greater transistor density can be achieved
because fin isolation dimensioning and placement can be made
perfectly on-pitch with the gate electrodes so that both gate
electrodes and isolation regions are integer multiples of a minimum
feature pitch of a single masking level. In further embodiments
where the semiconductor fin has a lattice mismatch with a substrate
on which the fin is disposed, greater degrees of strain are
maintained by defining the isolation after placement or definition
of the gate electrode. For such embodiments, other features of the
transistor (such as the gate electrode and added source or drain
materials) that are formed before ends of the fin are defined help
to mechanically maintain fin strain after an isolation cut is made
into the fin.
[0041] To provide further context, transistor scaling can benefit
from a denser packing of cells within the chip. Currently, most
cells are separated from their neighbors by two or more dummy
gates, which have buried fins. The cells are isolated by etching
the fins beneath these two or more dummy gates, which connect one
cell to the other. Scaling can benefit significantly if the number
of dummy gates that separate neighboring cells can be reduced from
two or more down to one. As explained above, one solution requires
two or more dummy gates. The fins under the two or more dummy gates
are etched during fin patterning. A potential issue with such an
approach is that dummy gates consume space on the chip which can be
used for cells. In an embodiment, approaches described herein
enable the use of only a single dummy gate to separate neighboring
cells.
[0042] In an embodiment, a fin trim isolation approach is
implemented as a self-aligned patterning scheme. Here, the fins
beneath a single gate are etched out. Thus, neighboring cells can
be separated by a single dummy gate. Advantages to such an approach
may include saving space on the chip and allowing for more
computational power for a given area. The approach may also allow
for fin trim to be performed at a sub-fin pitch distance.
[0043] FIGS. 1A and 1B illustrate plan views representing various
operations in a method of patterning of fins with multi-gate
spacing for forming a local isolation structure, in accordance with
an embodiment of the present disclosure.
[0044] Referring to FIG. 1A, a plurality of fins 102 is shown
having a length along a first direction 104. A grid 106, having
spacings 107 there between, defining locations for ultimately
forming a plurality of gate lines is shown along a second direction
108 orthogonal to the first direction 104.
[0045] Referring to FIG. 1B, a portion of the plurality of fins 102
is cut (e.g., removed by an etch process) to leave fins 110 having
a cut 112 therein. An isolation structure ultimately formed in the
cut 112 therefore has a dimension of more than a single gate line,
e.g., a dimension of three gate lines 106. Accordingly, gate
structures ultimately formed along the locations of the gate lines
106 will be formed at least partially over an isolation structure
formed in cut 112. Thus, cut 112 is a relatively wide fin cut.
[0046] FIGS. 2A-2D illustrate plan views representing various
operations in a method of patterning of fins with single gate
spacing for forming a local isolation structure, in accordance with
another embodiment of the present disclosure.
[0047] Referring to FIG. 2A, a method of fabricating an integrated
circuit structure includes forming a plurality of fins 202,
individual ones of the plurality of fins 202 having a longest
dimension along a first direction 204. A plurality of gate
structures 206 is over the plurality of fins 202, individual ones
of the gate structures 206 having a longest dimension along a
second direction 208 orthogonal to the first direction 204. In an
embodiment, the gate structures 206 are sacrificial or dummy gate
lines, e.g., fabricated from polycrystalline silicon. In one
embodiment, the plurality of fins 202 are silicon fins and are
continuous with a portion of an underlying silicon substrate.
[0048] Referring to FIG. 2B, a dielectric material structure 210 is
formed between adjacent ones of the plurality of gate structures
206.
[0049] Referring to FIG. 2C, a portion 212 of one of the plurality
of gate structures 206 is removed to expose a portion 214 of each
of the plurality of fins 202. In an embodiment, removing the
portion 212 of the one of the plurality of gate structures 206
involves using a lithographic window 216 wider than a width 218 of
the portion 212 of the one of the plurality of gate structures
206.
[0050] Referring to FIG. 2D, the exposed portion 214 of each of the
plurality of fins 202 is removed to form a cut region 220. In an
embodiment, the exposed portion 214 of each of the plurality of
fins 202 is removed using a dry or plasma etch process. In an
embodiment, removing the exposed portion 214 of each of the
plurality of fins 202 involves etching to a depth less than a
height of the plurality of fins 202. In one such embodiment, the
depth is greater than a depth of source or drain regions in the
plurality of fins 202. In an embodiment, the depth is deeper than a
depth of an active portion of the plurality of fins 202 to provide
isolation margin. In an embodiment, the exposed portion 214 of each
of the plurality of fins 202 is removed without etching or without
substantially etching source or drain regions (such as epitaxial
source or drain regions) of the plurality of fins 202. In one such
embodiment, the exposed portion 214 of each of the plurality of
fins 202 is removed without laterally etching or without
substantially laterally etching source or drain regions (such as
epitaxial source or drain regions) of the plurality of fins
202.
[0051] In an embodiment, the cut region 220 is ultimately filled
with an insulating layer, e.g., in locations of the removed portion
214 of each of the plurality of fins 202. Exemplary insulating
layers or "poly cut" or "plug" structure are described below. In
other embodiments, however, the cut region 220 is only partially
filled with an insulating layer in which a conductive structure is
then formed. The conductive structure may be used as a local
interconnect. In an embodiment, prior to filling the cut region 220
with an insulating layer or with an insulating layer housing a
local interconnect structure, dopants may be implanted or delivered
by a solid source dopant layer into the locally cut portion of the
fin or fins through the cut region 220.
[0052] FIG. 3 illustrates a cross-sectional view of an integrated
circuit structure having a fin with multi-gate spacing for local
isolation, in accordance with an embodiment of the present
disclosure.
[0053] Referring to FIG. 3, a silicon fin 302 has a first fin
portion 304 laterally adjacent a second fin portion 306. The first
fin portion 304 is separated from the second fin portion 306 by a
relatively wide cut 308, such as described in association with
FIGS. 1A and 1B, the relatively wide cut 308 having a width X. A
dielectric fill material 310 is formed in the relatively wide cut
308 and electrically isolates the first fin portion 304 from the
second fin portion 306. A plurality of gate lines 312 is over the
silicon fin 302, where each of the gate lines may include a gate
dielectric and gate electrode stack 314, a dielectric cap layer
316, and sidewall spacers 318. Two gate lines (left two gate lines
312) occupy the relatively wide cut 308 and, as such, the first fin
portion 304 is separated from the second fin portion 306 by
effectively two dummy or inactive gates.
[0054] By contrast, fin portions may be separated by a single gate
distance. As an example, FIG. 4A illustrates a cross-sectional view
of an integrated circuit structure having a fin with single gate
spacing for local isolation, in accordance with another embodiment
of the present disclosure.
[0055] Referring to FIG. 4A, a silicon fin 402 has a first fin
portion 404 laterally adjacent a second fin portion 406. The first
fin portion 404 is separated from the second fin portion 406 by a
relatively narrow cut 408, such as described in association with
FIGS. 2A-2D, the relatively narrow cut 408 having a width Y, where
Y is less than X of FIG. 3. A dielectric fill material 410 is
formed in the relatively narrow cut 408 and electrically isolates
the first fin portion 404 from the second fin portion 406. A
plurality of gate lines 412 is over the silicon fin 402, where each
of the gate lines may include a gate dielectric and gate electrode
stack 414, a dielectric cap layer 416, and sidewall spacers 418.
The dielectric fill material 410 occupies the location where a
single gate line was previously and, as such, the first fin portion
404 is separated from the second fin portion 406 by single
"plugged" gate line. In one embodiment, residual spacer material
420 remains on the sidewalls of the location of the removed gate
line portion, as depicted. It is to be appreciated that other
regions of the fin 402 may be isolated from one another by two or
even more inactive gate lines (region 422 having three inactive
gate lines) fabricated by an earlier, broader fin cut process, as
described below.
[0056] Referring again to FIG. 4A, an integrated circuit structure
400 a fin 402, such as a silicon fin. The fin 402 has a longest
dimension along a first direction 450. An isolation structure 410
separates a first upper portion 404 of the fin 402 from a second
upper portion 406 of the fin 402 along the first direction 450. The
isolation structure 410 has a center 411 along the first direction
450.
[0057] A first gate structure 412A is over the first upper portion
404 of the fin 402, the first gate structure 412A has a longest
dimension along a second direction 452 (e.g., into the page)
orthogonal to the first direction 450. A center 413A of the first
gate structure 412A is spaced apart from the center 411 of the
isolation structure 410 by a pitch along the first direction 450. A
second gate structure 412B is over the first upper portion 404 of
the fin, the second gate structure 412B having a longest dimension
along the second direction 452. A center 413B of the second gate
structure 412B is spaced apart from the center 413A of the first
gate structure 412A by the pitch along the first direction 450. A
third gate structure 412C is over the second upper portion 406 of
the fin 402, the third gate structure 412C having a longest
dimension along the second direction 452. A center 413C of the
third gate structure 412C is spaced apart from the center 411 of
the isolation structure 410 by the pitch along the first direction
450. In an embodiment, the isolation structure 410 has a top
substantially co-planar with a top of the first gate structure
412A, with a top of the second gate structure 412B, and with a top
of the third gate structure 412C, as is depicted.
[0058] In an embodiment, each of the first gate structure 412A, the
second gate structure 412B and the third gate structure 412C
includes a gate electrode 460 on and between sidewalls of a high-k
gate dielectric layer 462, as is illustrated for exemplary third
gate structure 412C. In one such embodiment, each of the first gate
structure 412A, the second gate structure 412B and the third gate
structure 412C further includes an insulating cap 416 on the gate
electrode 460 and on and the sidewalls of the high-k gate
dielectric layer 462.
[0059] In an embodiment, the integrated circuit structure 400
further includes a first epitaxial semiconductor region 464A on the
first upper portion 404 of the fin 402 between the first gate
structure 412A and the isolation structure 410. A second epitaxial
semiconductor region 464B is on the first upper portion 404 of the
fin 402 between the first gate structure 412A and the second gate
structure 412B. A third epitaxial semiconductor region 464C is on
the second upper portion 406 of the fin 402 between the third gate
structure 412C and the isolation structure 410. In one embodiment,
the first 464A, second 464B and third 464C epitaxial semiconductor
regions include silicon and germanium. In another embodiment, the
first 464A, second 464B and third 464C epitaxial semiconductor
regions include silicon.
[0060] In an embodiment, the isolation structure 410 induces a
stress on the first upper portion 404 of the fin 402 and on the
second upper portion 406 of the fin 402. In one embodiment, the
stress is a compressive stress. In another embodiment, the stress
is a tensile stress. In other embodiments, the isolation structure
410 is a partially filling insulating layer in which a conductive
structure is then formed. The conductive structure may be used as a
local interconnect. In an embodiment, prior to forming the
isolation structure 410 with an insulating layer or with an
insulating layer housing a local interconnect structure, dopants
are implanted or delivered by a solid source dopant layer into a
locally cut portion of the fin or fins.
[0061] In another aspect, it is to be appreciated that isolation
structures such as isolation structure 410 described above may be
formed in place of active gate electrode at local locations of a
fin cut or at broader locations of a fin cut. Additionally, the
depth of such local or broader locations of fin cut may be formed
to varying depths within the fin relative to one another. In a
first example, FIG. 4B illustrates a cross-sectional view showing
locations where a fin isolation structure may be formed in place of
a gate electrode, in accordance with an embodiment of the present
disclosure.
[0062] Referring to FIG. 4B, a fin 480, such as a silicon fin, is
formed above and may be continuous with a substrate 482. The fin
480 has fin ends or broad fin cuts 484, e.g., which may be formed
at the time of fin patterning such as in a fin trim last approach
described above. The fin 480 also has a local cut 486, where a
portion of the fin 480 is removed, e.g., using a fin trim isolation
approach where dummy gates are replaced with dielectric plugs, as
described above. Active gate electrodes 488 are formed over the fin
and, for the sake of illustration purposes, are shown slightly in
front of the fin 480, with the fin 480 in the background, where the
dashed lines represent areas covered from the front view.
Dielectric plugs 490 may be formed at the fin ends or broad fin
cuts 484 in place of using active gates at such locations. In
addition, or in the alternative, a dielectric plug 492 may be
formed at the local cut 486 in place of using an active gate at
such a location. It is to be appreciated that epitaxial source or
drain regions 494 are also shown at locations of the fins 480
between the active gate electrodes 488 and the plugs 490 or 492.
Additionally, in an embodiment, the surface roughness of the ends
of the fin at the local cut 486 are rougher than the ends of the
fin at a location of a broader cut, as is depicted in FIG. 4B.
[0063] FIGS. 5A-5C illustrate various depth possibilities for a fin
cut fabricated using fin trim isolation approach, in accordance
with an embodiment of the preset disclosure.
[0064] Referring to FIG. 5A, a semiconductor fin 500, such as a
silicon fin, is formed above and may be continuous with an
underlying substrate 502. The fin 500 has a lower fin portion 500A
and an upper fin portion 500B, as defined by the height of an
insulating structure 504 relative to the fin 500. A local fin
isolation cut 506A separates the fin 500 into a first fin portion
510 from a second fin portion 512. In the example of FIG. 5A, as
shown along the a-a' axis, the depth of the local fin isolation cut
506A is the entire depth of the fin 500 to the substrate 502.
[0065] Referring to FIG. 5B, in a second example, as shown along
the a-a' axis, the depth of a local fin isolation cut 506B is
deeper than the entire depth of the fin 500 to the substrate 502.
That is, the cut 506B extends into the underlying substrate
502.
[0066] Referring to FIG. 5C, in a third example, as shown along the
a-a' axis, the depth of a local fin isolation cut 506C is less than
the entire depth of the fin 500, but is deeper than an upper
surface of the isolation structure 504. Referring again to FIG. 5C,
in a fourth example, as shown along the a-a' axis, the depth of a
local fin isolation cut 506D is less than the entire depth of the
fin 500, and is at a level approximately co-planar with an upper
surface of the isolation structure 504.
[0067] FIG. 6 illustrates a plan view and corresponding
cross-sectional view taken along the a-a' axis showing possible
options for the depth of local versus broader locations of fin cuts
within a fin, in accordance with an embodiment of the present
disclosure.
[0068] Referring to FIG. 6, first and second semiconductor fins 600
and 602, such as silicon fins, have upper fin portions 600B and
602B extending above an insulating structure 604. Both of the fins
600 and 602 have fin ends or broad fin cuts 606, e.g., which may be
formed at the time of fin patterning such as in a fin trim last
approach described above. Both of the fins 600 and 602 also have a
local cut 608, where a portion of the fin 600 or 602 is removed,
e.g., using a fin trim isolation approach where dummy gates are
replaced with dielectric plugs, as described above. In an
embodiment, the surface roughness of the ends of the fins 600 and
602 at the local cut 608 are rougher than the ends of the fins at a
location of 606, as is depicted in FIG. 6.
[0069] Referring to the cross-sectional view of FIG. 6, lower fin
portions 600A and 602A can be viewed below the height of the
insulating structure 604. Also, seen in the cross-sectional view is
a remnant portion 610 of a fin that was removed at a fin trim last
process prior to formation of the insulating structure 604, as
described above. Although shown as protruding above a substrate,
remnant portion 610 could also be at the level of the substrate or
into the substrate, as is depicted by the additional exemplary
broad cut depths 620. It is to be appreciated that the broad cuts
606 for fins 600 and 602 may also be at the levels described for
cut depth 620, examples of which are depicted. The local cut 608
can have exemplary depths corresponding to the depths described for
FIGS. 5A-5C, as is depicted.
[0070] In another aspect, dielectric plugs formed in locations of
local or broad fin cuts can be tailored to provide a particular
stress to the fin or fin portion. The dielectric plugs may be
referred to as fin end stressors in such implementations. In the
case that dielectric plugs are formed in locations of a local fin
cut, the dielectric plugs may be referred to as fin trim plug
structures. Such fin trim plug structures may impart channel
stress.
[0071] One or more embodiments are directed to the fabrication of
fin-based semiconductor devices. Performance improvement for such
devices may be made via channel stress induced from a poly plug
fill process. Embodiments may include the exploitation of material
properties in a poly plug fill process to induce mechanical stress
in a metal oxide semiconductor field effect transistor (MOSFET)
channel. As a result, an induced stress can boost the mobility and
drive current of the transistor. In addition, a method of plug fill
described herein may allow for the elimination of any seam or void
formation during deposition.
[0072] To provide context, manipulating unique material properties
of a plug fill that abuts fins can induce stress within the
channel. In accordance with one or more embodiments, by tuning the
composition, deposition, and post-treatment conditions of the plug
fill material, stress in the channel is modulated to benefit both
NMOS and PMOS transistors. In addition, such plugs can reside
deeper in the fin substrate compared to other common stressor
techniques, such as epitaxial source or drains. The nature of the
plug fill to achieve such effect also eliminates seams or voids
during deposition and mitigates certain defect modes during the
process.
[0073] To provide further context, presently there is no
intentional stress engineering for gate (poly) plugs. The stress
enhancement from traditional stressors such as epitaxial source or
drains, dummy poly gate removal, stress liners, etc. unfortunately
tends to diminish as device pitches shrink. Addressing one or more
of the above issues, in accordance with one or more embodiments of
the present disclosure, an additional source of stress is
incorporated into the transistor structure. Another possible
benefit with such a process may be the elimination of seams or
voids within the plug that may be common with other chemical vapor
deposition methods.
[0074] FIGS. 7A and 7B illustrate cross-sectional views of various
operations in a method of selecting fin end stressor locations at
ends of a fin that has a broad cut, e.g., as part of a fin trim
last process as described above, in accordance with an embodiment
of the present disclosure.
[0075] Referring to FIG. 7A, a fin 700, such as a silicon fin, is
formed above and may be continuous with a substrate 702. The fin
700 has fin ends or broad fin cuts 704, e.g., which may be formed
at the time of fin patterning such as in a fin trim last approach
described above. An active gate electrode location 706 and dummy
gate electrode locations 708 are formed over the fin 700 and, for
the sake of illustration purposes, are shown slightly in front of
the fin 700, with the fin 700 in the background, where the dashed
lines represent areas covered from the front view. It is to be
appreciated that epitaxial source or drain regions 710 are also
shown at locations of the fin 700 between the gate locations 706
and 708. Additionally, an inter-layer dielectric material 712 is
included at locations of the fin 700 between the gate locations 706
and 708.
[0076] Referring to FIG. 7B, the gate placeholder structures or
dummy gates locations 708 are removed, exposing the fin ends or
broad fin cuts 704. The removal creates openings 720 where
dielectric plugs, e.g., fin end stressor dielectric plugs, may
ultimately be formed.
[0077] FIGS. 8A and 8B illustrate cross-sectional views of various
operations in a method of selecting fin end or fin trim stressor
locations at ends of a fin that has a local cut, e.g., as part of a
fin trim isolation process as described above, in accordance with
an embodiment of the present disclosure.
[0078] Referring to FIG. 8A, a fin 800, such as a silicon fin, is
formed above and may be continuous with a substrate 802. The fin
800 has a local cut 804, where a portion of the fin 800 is removed,
e.g., using a fin trim isolation approach where a dummy gate is
removed and the fin is etched in a local location, as described
above. Active gate electrode locations 806 and a dummy gate
electrode location 808 are formed over the fin 800 and, for the
sake of illustration purposes, are shown slightly in front of the
fin 800, with the fin 800 in the background, where the dashed lines
represent areas covered from the front view. It is to be
appreciated that epitaxial source or drain regions 810 are also
shown at locations of the fin 800 between the gate locations 806
and 808. Additionally, an inter-layer dielectric material 812 is
included at locations of the fin 800 between the gate locations 806
and 808.
[0079] Referring to FIG. 8B, the gate placeholder structure or
dummy gate electrode location 808 is removed, exposing the fin ends
with local cut 804. The removal creates opening 820 where a
dielectric plug, e.g., a fin end stressor dielectric plug, may
ultimately be formed.
[0080] In another aspect, an FTI opening is filled or partially
filled with a silicon (Si) film, and a catalytic oxidation (Cat-OX)
process is used to convert the Si to silicon oxide or silicon
dioxide. This conversion may be accompanied with an SiO.sub.2
increase in volume creating stress on an adjacent device. As an
example, FIGS. 9A-9H illustrate cross-sectional views of various
operation in a method of fabricating an integrated circuit
structure having fin trim dielectric plugs, in accordance with an
embodiment of the present disclosure. For each operation depicted,
a fin cut cross-sectional view is shown with a corresponding gate
cut cross-sectional view.
[0081] Referring to FIG. 9A, a starting structure 900 includes a
fin 904, such as a silicon fin. The fin 904 includes an upper fin
portion 904A above a lower or sub-fin portion 904B. The lower fin
portion 904B is within an isolation layer 902, such as a trench
isolation structure. Although not depicted, a substrate may be
beneath the lower fin portion 904B and the isolation layer 902.
[0082] Structures are formed over portions of the upper fin portion
904A and exposed a portion of the upper fin portion 904A. For
example, in one embodiment, the structures are dummy or permanent
gate structures including a gate electrode 908, an insulating gate
cap or hardmask 910, and gate spacers 906. In another embodiment,
the structures are dummy or permanent trench contact structures
including a trench contact or trench contact placeholder 908, an
insulating trench cap or hardmask 910, and dielectric spacers 906.
In the former case, an opening is formed between two immediately
adjacent gate structures. In the latter case, an opening is formed,
e.g., by removing a replacement gate structure between the two
trench contact structures to expose a portion of the upper fin
portion 904A. Permanent gate electrode locations (not depicted in
FIG. 9A) are further on outer sides of the trench contact or trench
contact placeholder 908.
[0083] Referring to FIG. 9B, the exposed portion of the upper fin
portion 904A is etched to form a trench 912 separating a first fin
portion and a second fin portion (covered by the left and right
structures depicted in the gate cut of FIG. 9B). In an embodiment,
an anisotropic dry or plasma etch process is used to form trench
912.
[0084] Referring to FIG. 9C, a liner dielectric layer 914 is formed
over the structure of FIG. 9B. In one embodiment, the liner
dielectric layer 914 is or includes silicon nitride.
[0085] Referring to FIG. 9D, a layer including silicon 916 is
formed over the structure of FIG. 9C. In one embodiment, the layer
including silicon 916 is or includes amorphous silicon.
[0086] Referring to FIG. 9E, the layer including silicon 916 is
recessed within trench 912 to form a recessed layer including
silicon 916A. In an embodiment, the layer including silicon 916 is
recessed by forming a hardmask layer, such as a carbon-based
hardmask layer, in trench 912 on the layer including silicon 916.
The hardmask layer is then recessed to a level within the trench
912. The portions of the layer including silicon 916 not covered by
the recessed hardmask layer are then removed to form the recessed
layer including silicon 916A.
[0087] Referring again to FIG. 9E, an oxidation catalyst layer 918
is then formed in the trench 912 and on the recessed layer
including silicon 916A. In one embodiment, the oxidation catalyst
layer 918 is or includes aluminum oxide. In another embodiment, the
oxidation catalyst layer 918 is or includes lanthanum oxide.
[0088] Referring to FIG. 9F, recessed layer including silicon 916A
is oxidized in the presence of the oxidation catalyst layer 918. In
an embodiment, the oxidation process is a process that can oxidize
silicon but at a rate that is substantially enhanced by the
presence of oxidation catalyst layer 918. In one such embodiment,
the oxidation process is enhanced to rapidly oxidize the recessed
layer including silicon 916A to form a silicon oxide or silicon
dioxide trench liner layer 916B. In one embodiment, the silicon
oxide or silicon dioxide trench liner layer 916B is formed without
oxidizing (or only very minimally oxidizing) any other exposed
silicon features such as exposed fin portions that do not include
the oxidation catalyst layer 918. In an embodiment, the oxidation
process involves a wet oxidation anneal, e.g., heating the
structure in the presence of water or water vapor.
[0089] In an embodiment, the volume of the silicon oxide or silicon
dioxide trench liner layer 916B is greater than the volume of the
recessed layer including silicon 916A due to expansion of the film
upon incorporation of oxygen. In one embodiment, the effectively
expanded silicon oxide or silicon dioxide trench liner layer 916B
pushes against ends of the upper silicon fin portions that remain
after trench 912 formation. In one such embodiment, the effect
provides a compressive stress to the upper silicon fin portions
that remain after trench 912 formation. In an embodiment, the
volume of the silicon oxide or silicon dioxide trench liner layer
916B is approximately 30% greater than the volume of the recessed
layer including silicon 916A due to expansion of the film upon
incorporation of oxygen. In an embodiment, the expanded silicon
oxide or silicon dioxide trench liner layer 916B traps a portion
918A within the expanded silicon oxide or silicon dioxide trench
liner layer 916B, as is depicted.
[0090] Referring to FIG. 9G, the method involves removing portions
of the oxidation catalyst layer 918 not including portion 918A
trapped within the expanded silicon oxide or silicon dioxide trench
liner layer 916B. In an embodiment, removing the portions of the
oxidation catalyst layer 918 is performed such that a portion of
the oxidation catalyst layer 918 is left to remain over the silicon
oxide or silicon dioxide trench liner layer 916B, as is depicted.
In other embodiments, however, only the portion 918A trapped within
the vertical seam of the expanded silicon oxide or silicon dioxide
trench liner layer 916B is retained, exposing upper surfaces of the
silicon oxide or silicon dioxide trench liner layer 916B.
[0091] Referring to FIG. 9H, the remainder of trench 912 is filled
with a fill dielectric material 920. In one embodiment, fill
dielectric material 920 is formed on the portion of the oxidation
catalyst layer 918 left to remain over the silicon oxide or silicon
dioxide trench liner layer 916B, as is depicted. In another
embodiment, fill dielectric material 920 is formed on the portion
918A of the oxidation catalyst layer trapped within the vertical
seam of the expanded silicon oxide or silicon dioxide trench liner
layer 916B and on exposed upper surfaces of the silicon oxide or
silicon dioxide trench liner layer 916B. In an embodiment, fill
dielectric material 920 is formed using a blanket deposition and
planarization approach. In one embodiment, the planarization stops
on overburden portions of the liner dielectric layer 914, as is
depicted. In other embodiments, the planarization removes
overburden portions of the liner dielectric layer 914. In an
embodiment, the fill dielectric material 920 is composed of or
includes a material such as, but not limited to, silicon oxide,
silicon dioxide, silicon oxynitride or silicon nitride.
[0092] With reference again to FIGS. 9A-9H, in accordance with an
embodiment of the present disclosure, an integrated circuit
structure includes a fin 904 including silicon, the fin 904 having
a top and sidewalls. The fin has a trench 912 separating a first
fin portion (left 904A) and a second fin portion (right 904A). A
first structure 906/908/910 such as a first gate structure
including a gate electrode (or, alternatively, a first trench
contact structure or placeholder structure) is over the top of and
laterally adjacent to the sidewalls of the first fin portion (left
904A). A second structure 906/908/910 such as a second gate
structure including a gate electrode (or, alternatively, a second
trench contact structure or placeholder structure) is over the top
of and laterally adjacent to the sidewalls of the second fin
portion (right 904A).
[0093] With reference to FIG. 9H, an isolation structure is in the
trench 912 of the fin 904. The isolation structure between the
first gate structure and the second gate structure. The isolation
structure includes a first dielectric material 914 laterally
surrounding a recessed second dielectric material 916B distinct
from the first dielectric material 914. The recessed second
dielectric material 916B is laterally surrounding an oxidation
catalyst layer 918A.
[0094] In an embodiment, the oxidation catalyst layer 918A includes
aluminum oxide. In another embodiment, the oxidation catalyst layer
918A includes lanthanum oxide.
[0095] In an embodiment, the isolation structure further includes a
third dielectric material 920 laterally surrounded by an upper
portion of the first dielectric material 914. The third dielectric
material 920 is on an upper surface of the oxidation catalyst layer
918 or 918A. In one such embodiment, the third dielectric material
920 is on only an upper surface of the oxidation catalyst layer
918, as is depicted. In another embodiment, the third dielectric
material 920 is further on an upper surface of the second
dielectric material 916B and on the portion 918A of the oxidation
catalyst layer trapped by the second dielectric material 916B.
[0096] In an embodiment, the oxidation catalyst layer 918/918A has
an upper surface above an upper surface of the second dielectric
material 916B, as is depicted. In another embodiment (not
depicted), the oxidation catalyst layer 918A has an upper surface
co-planar with an upper surface of the second dielectric material
916B. In another embodiment (not depicted), the oxidation catalyst
layer 918A has an upper surface below an upper surface of the
second dielectric material 916B.
[0097] As an exemplary structure, FIG. 10 illustrates a
cross-sectional view of a structure having fin trim plug structures
at all possible (maximum) locations for demonstrative purposes, in
accordance with an embodiment of the present disclosure.
[0098] Referring to FIG. 10, an integrated circuit structure 1000
includes upper fin portion 904A having structures (such as gate
structures) 1002 thereon which may include hardmask layers 1004.
Isolation structures formed in trenches between upper fin portions
904A include the second dielectric material 916B and the oxidation
catalyst layer having a portion 918A trapped in a seam of the
second dielectric material 916B.
[0099] As described above, it is to be appreciated that poly plug
stress effects can benefit PMOS transistors (e.g., compressive
channel stress). In accordance with an embodiment of the present
disclosure, a semiconductor fin is a uniaxially stressed
semiconductor fin. The uniaxially stressed semiconductor fin may be
uniaxially stressed with compressive stress. For example, FIG. 11
illustrates an angled view of a fin having compressive uniaxial
stress, in accordance with one or more embodiments of the present
disclosure.
[0100] Referring to FIG. 11, a semiconductor fin 1100 has a
discrete channel region (C) disposed therein. A source region (S)
and a drain region (D) are disposed in the semiconductor fin 1100,
on either side of the channel region (C). The discrete channel
region of the semiconductor fin 1100 has a current flow direction
along the direction of a uniaxial compressive stress (arrows
pointed toward one another and from ends 1102 and 1104), from the
source region (S) to the drain region (D). Accordingly, embodiments
described herein may be implemented to improve transistor mobility
and drive current, allowing for faster performing circuits and
chips.
[0101] In another aspect, there may be a relationship between
locations where gate line cuts (poly cuts) are made and fin-trim
isolation (FTI) local fin cuts are made. In an embodiment, FTI
local fin cuts are made only in locations where poly cuts are made.
In one such embodiment, however, an FTI cut is not necessarily made
at every location where a poly cut is made.
[0102] FIGS. 12A and 12B illustrate plan views representing various
operations in a method of patterning of fins with single gate
spacing for forming a local isolation structure in select gate line
cut locations, in accordance with an embodiment of the present
disclosure.
[0103] Referring to FIG. 12A, a method of fabricating an integrated
circuit structure includes forming a plurality of fins 1202,
individual ones of the plurality of fins 1202 having a longest
dimension along a first direction 1204. A plurality of gate
structures 1206 is over the plurality of fins 1202, individual ones
of the gate structures 1206 having a longest dimension along a
second direction 1208 orthogonal to the first direction 1204. In an
embodiment, the gate structures 1206 are sacrificial or dummy gate
lines, e.g., fabricated from polycrystalline silicon. In one
embodiment, the plurality of fins 1202 are silicon fins and are
continuous with a portion of an underlying silicon substrate.
[0104] Referring again to FIG. 12A, a dielectric material structure
1210 is formed between adjacent ones of the plurality of gate
structures 1206. Portions 1212 and 1213 of two of the plurality of
gate structures 1206 are removed to expose portions of each of the
plurality of fins 1202. In an embodiment, removing the portions
1212 and 1213 of the two of the gate structures 1206 involves using
a lithographic window wider than a width of each of the portions
1212 and 1213 of the gate structures 1206. The exposed portion of
each of the plurality of fins 1202 at location 1212 is removed to
form a cut region 1220. In an embodiment, the exposed portion of
each of the plurality of fins 1202 is removed using a dry or plasma
etch process. However, the exposed portion of each of the plurality
of fins 1202 at location 1213 is masked from removal. In an
embodiment, the region 1212/1220 represents both a poly cut and an
FTI local fin cut. However, the location 1213 represents a poly cut
only.
[0105] Referring to FIG. 12B, the location 1212/1220 of the poly
cut and FTI local fin cut and the location 1213 of the poly cut are
filled with insulating structures 1230 such as a dielectric plugs.
Exemplary insulating structures or "poly cut" or "plug" structure
are described below.
[0106] FIGS. 13A-13C illustrate cross-sectional views of various
possibilities for dielectric plugs for poly cut and FTI local fin
cut locations and poly cut only locations for various regions of
the structure of FIG. 12B, in accordance with an embodiment of the
present disclosure.
[0107] Referring to FIG. 13A, a cross-sectional view of a portion
1300A of the dielectric plug 1230 at location 1213 is shown along
the a-a' axis of the structure of FIG. 12B. The portion 1300A of
the dielectric plug 1230 is shown on an uncut fin 1202 and between
dielectric material structures 1210.
[0108] Referring to FIG. 13B, a cross-sectional view of a portion
1300B of the dielectric plug 1230 at location 1212 is shown along
the b-b' axis of the structure of FIG. 12B. The portion 1300B of
the dielectric plug 1230 is shown on an cut fin location 1220 and
between dielectric material structures 1210.
[0109] Referring to FIG. 13C, a cross-sectional view of a portion
1300C of the dielectric plug 1230 at location 1212 is shown along
the c-c' axis of the structure of FIG. 12B. The portion 1300C of
the dielectric plug 1230 is shown on a trench isolation structure
1302 between fins 1202 and between dielectric material structures
1210. In an embodiment, examples of which are described above, the
trench isolation structure 1302 includes a first insulating layer
1302A, a second insulating layer 1302B, and an insulating fill
material 1302C on the second insulating layer 1302B.
[0110] As described throughout the present application, a substrate
may be composed of a semiconductor material that can withstand a
manufacturing process and in which charge can migrate. In an
embodiment, a substrate is described herein is a bulk substrate
composed of a crystalline silicon, silicon/germanium or germanium
layer doped with a charge carrier, such as but not limited to
phosphorus, arsenic, boron or a combination thereof, to form an
active region. In one embodiment, the concentration of silicon
atoms in such a bulk substrate is greater than 97%. In another
embodiment, a bulk substrate is composed of an epitaxial layer
grown atop a distinct crystalline substrate, e.g. a silicon
epitaxial layer grown atop a boron-doped bulk silicon
mono-crystalline substrate. A bulk substrate may alternatively be
composed of a group III-V material. In an embodiment, a bulk
substrate is composed of a III-V material such as, but not limited
to, gallium nitride, gallium phosphide, gallium arsenide, indium
phosphide, indium antimonide, indium gallium arsenide, aluminum
gallium arsenide, indium gallium phosphide, or a combination
thereof. In one embodiment, a bulk substrate is composed of a III-V
material and the charge-carrier dopant impurity atoms are ones such
as, but not limited to, carbon, silicon, germanium, oxygen, sulfur,
selenium or tellurium.
[0111] As described throughout the present application, isolation
regions such as shallow trench isolation regions or sub-fin
isolation regions may be composed of a material suitable to
ultimately electrically isolate, or contribute to the isolation of,
portions of a permanent gate structure from an underlying bulk
substrate or to isolate active regions formed within an underlying
bulk substrate, such as isolating fin active regions. For example,
in one embodiment, an isolation region is composed of one or more
layers of a dielectric material such as, but not limited to,
silicon dioxide, silicon oxy-nitride, silicon nitride, carbon-doped
silicon nitride, or a combination thereof.
[0112] As described throughout the present application, gate lines
or gate structures may be composed of a gate electrode stack which
includes a gate dielectric layer and a gate electrode layer. In an
embodiment, the gate electrode of the gate electrode stack is
composed of a metal gate and the gate dielectric layer is composed
of a high-K material. For example, in one embodiment, the gate
dielectric layer is composed of a material such as, but not limited
to, hafnium oxide, hafnium oxy-nitride, hafnium silicate, lanthanum
oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium
strontium titanate, barium titanate, strontium titanate, yttrium
oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc
niobate, or a combination thereof. Furthermore, a portion of gate
dielectric layer may include a layer of native oxide formed from
the top few layers of a semiconductor substrate. In an embodiment,
the gate dielectric layer is composed of a top high-k portion and a
lower portion composed of an oxide of a semiconductor material. In
one embodiment, the gate dielectric layer is composed of a top
portion of hafnium oxide and a bottom portion of silicon dioxide or
silicon oxy-nitride. In some implementations, a portion of the gate
dielectric is a "U"-shaped structure that includes a bottom portion
substantially parallel to the surface of the substrate and two
sidewall portions that are substantially perpendicular to the top
surface of the substrate.
[0113] In one embodiment, a gate electrode is composed of a metal
layer such as, but not limited to, metal nitrides, metal carbides,
metal silicides, metal aluminides, hafnium, zirconium, titanium,
tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel
or conductive metal oxides. In a specific embodiment, the gate
electrode is composed of a non-workfunction-setting fill material
formed above a metal workfunction-setting layer. The gate electrode
layer may consist of a P-type workfunction metal or an N-type
workfunction metal, depending on whether the transistor is to be a
PMOS or an NMOS transistor. In some implementations, the gate
electrode layer may consist of a stack of two or more metal layers,
where one or more metal layers are workfunction metal layers and at
least one metal layer is a conductive fill layer. For a PMOS
transistor, metals that may be used for the gate electrode include,
but are not limited to, ruthenium, palladium, platinum, cobalt,
nickel, and conductive metal oxides, e.g., ruthenium oxide. A
P-type metal layer will enable the formation of a PMOS gate
electrode with a workfunction that is between about 4.9 eV and
about 5.2 eV. For an NMOS transistor, metals that may be used for
the gate electrode include, but are not limited to, hafnium,
zirconium, titanium, tantalum, aluminum, alloys of these metals,
and carbides of these metals such as hafnium carbide, zirconium
carbide, titanium carbide, tantalum carbide, and aluminum carbide.
An N-type metal layer will enable the formation of an NMOS gate
electrode with a workfunction that is between about 3.9 eV and
about 4.2 eV. In some implementations, the gate electrode may
consist of a "U"-shaped structure that includes a bottom portion
substantially parallel to the surface of the substrate and two
sidewall portions that are substantially perpendicular to the top
surface of the substrate. In another implementation, at least one
of the metal layers that form the gate electrode may simply be a
planar layer that is substantially parallel to the top surface of
the substrate and does not include sidewall portions substantially
perpendicular to the top surface of the substrate. In further
implementations of the disclosure, the gate electrode may consist
of a combination of U-shaped structures and planar, non-U-shaped
structures. For example, the gate electrode may consist of one or
more U-shaped metal layers formed atop one or more planar,
non-U-shaped layers.
[0114] As described throughout the present application, spacers
associated with gate lines or electrode stacks may be composed of a
material suitable to ultimately electrically isolate, or contribute
to the isolation of, a permanent gate structure from adjacent
conductive contacts, such as self-aligned contacts. For example, in
one embodiment, the spacers are composed of a dielectric material
such as, but not limited to, silicon dioxide, silicon oxy-nitride,
silicon nitride, or carbon-doped silicon nitride.
[0115] In an embodiment, approaches described herein may involve
formation of a contact pattern which is very well aligned to an
existing gate pattern while eliminating the use of a lithographic
operation with exceedingly tight registration budget. In one such
embodiment, this approach enables the use of intrinsically highly
selective wet etching (e.g., versus dry or plasma etching) to
generate contact openings. In an embodiment, a contact pattern is
formed by utilizing an existing gate pattern in combination with a
contact plug lithography operation. In one such embodiment, the
approach enables elimination of the need for an otherwise critical
lithography operation to generate a contact pattern, as used in
other approaches. In an embodiment, a trench contact grid is not
separately patterned, but is rather formed between poly (gate)
lines. For example, in one such embodiment, a trench contact grid
is formed subsequent to gate grating patterning but prior to gate
grating cuts.
[0116] Furthermore, a gate stack structure may be fabricated by a
replacement gate process. In such a scheme, dummy gate material
such as polysilicon or silicon nitride pillar material, may be
removed and replaced with permanent gate electrode material. In one
such embodiment, a permanent gate dielectric layer is also formed
in this process, as opposed to being carried through from earlier
processing. In an embodiment, dummy gates are removed by a dry etch
or wet etch process. In one embodiment, dummy gates are composed of
polycrystalline silicon or amorphous silicon and are removed with a
dry etch process including use of SF.sub.6. In another embodiment,
dummy gates are composed of polycrystalline silicon or amorphous
silicon and are removed with a wet etch process including use of
aqueous NH.sub.4OH or tetramethylammonium hydroxide. In one
embodiment, dummy gates are composed of silicon nitride and are
removed with a wet etch including aqueous phosphoric acid.
[0117] In an embodiment, one or more approaches described herein
contemplate essentially a dummy and replacement gate process in
combination with a dummy and replacement contact process to arrive
at structure. In one such embodiment, the replacement contact
process is performed after the replacement gate process to allow
high temperature anneal of at least a portion of the permanent gate
stack. For example, in a specific such embodiment, an anneal of at
least a portion of the permanent gate structures, e.g., after a
gate dielectric layer is formed, is performed at a temperature
greater than approximately 600 degrees Celsius. The anneal is
performed prior to formation of the permanent contacts.
[0118] In some embodiments, the arrangement of a semiconductor
structure or device places a gate contact over portions of a gate
line or gate stack over isolation regions. However, such an
arrangement may be viewed as inefficient use of layout space. In
another embodiment, a semiconductor device has contact structures
that contact portions of a gate electrode formed over an active
region. In general, prior to (e.g., in addition to) forming a gate
contact structure (such as a via) over an active portion of a gate
and in a same layer as a trench contact via, one or more
embodiments of the present disclosure include first using a gate
aligned trench contact process. Such a process may be implemented
to form trench contact structures for semiconductor structure
fabrication, e.g., for integrated circuit fabrication. In an
embodiment, a trench contact pattern is formed as aligned to an
existing gate pattern. By contrast, other approaches typically
involve an additional lithography process with tight registration
of a lithographic contact pattern to an existing gate pattern in
combination with selective contact etches. For example, another
process may include patterning of a poly (gate) grid with separate
patterning of contact features.
[0119] Pitch division processing and patterning schemes may be
implemented to enable embodiments described herein or may be
included as part of embodiments described herein. Pitch division
patterning typically refers to pitch halving, pitch quartering etc.
Pitch division schemes may be applicable to FEOL processing, BEOL
processing, or both FEOL (device) and BEOL (metallization)
processing. In accordance with one or more embodiments described
herein, optical lithography is first implemented to print
unidirectional lines (e.g., either strictly unidirectional or
predominantly unidirectional) in a pre-defined pitch. Pitch
division processing is then implemented as a technique to increase
line density.
[0120] In an embodiment, the term "grating structure" for fins,
gate lines, metal lines, ILD lines or hardmask lines is used herein
to refer to a tight pitch grating structure. In one such
embodiment, the tight pitch is not achievable directly through a
selected lithography. For example, a pattern based on a selected
lithography may first be formed, but the pitch may be halved by the
use of spacer mask patterning, as is known in the art. Even
further, the original pitch may be quartered by a second round of
spacer mask patterning. Accordingly, the grating-like patterns
described herein may have metal lines, ILD lines or hardmask lines
spaced at a substantially consistent pitch and having a
substantially consistent width. For example, in some embodiments
the pitch variation would be within ten percent and the width
variation would be within ten percent, and in some embodiments, the
pitch variation would be within five percent and the width
variation would be within five percent. The pattern may be
fabricated by a pitch halving or pitch quartering, or other pitch
division, approach. In an embodiment, the grating is not
necessarily single pitch.
[0121] It is to be appreciated that not all aspects of the
processes described above need be practiced to fall within the
spirit and scope of embodiments of the present disclosure. For
example, in one embodiment, dummy gates need not ever be formed
prior to fabricating gate contacts over active portions of the gate
stacks. The gate stacks described above may actually be permanent
gate stacks as initially formed. Also, the processes described
herein may be used to fabricate one or a plurality of semiconductor
devices. The semiconductor devices may be transistors or like
devices. For example, in an embodiment, the semiconductor devices
are a metal-oxide semiconductor (MOS) transistors for logic or
memory, or are bipolar transistors. Also, in an embodiment, the
semiconductor devices have a three-dimensional architecture, such
as a trigate device, an independently accessed double gate device,
or a FIN-FET. One or more embodiments may be particularly useful
for fabricating semiconductor devices at a 10 nanometer (10 nm)
technology node sub-10 nanometer (10 nm) technology node.
[0122] Additional or intermediate operations for FEOL layer or
structure fabrication may include standard microelectronic
fabrication processes such as lithography, etch, thin films
deposition, planarization (such as chemical mechanical polishing
(CMP)), diffusion, metrology, the use of sacrificial layers, the
use of etch stop layers, the use of planarization stop layers, or
any other associated action with microelectronic component
fabrication. Also, it is to be appreciated that the process
operations described for the preceding process flows may be
practiced in alternative sequences, not every operation need be
performed or additional process operations may be performed, or
both.
[0123] Embodiments disclosed herein may be used to manufacture a
wide variety of different types of integrated circuits or
microelectronic devices. Examples of such integrated circuits
include, but are not limited to, processors, chipset components,
graphics processors, digital signal processors, micro-controllers,
and the like. In other embodiments, semiconductor memory may be
manufactured. Moreover, the integrated circuits or other
microelectronic devices may be used in a wide variety of electronic
devices known in the arts. For example, in computer systems (e.g.,
desktop, laptop, server), cellular phones, personal electronics,
etc. The integrated circuits may be coupled with a bus and other
components in the systems. For example, a processor may be coupled
by one or more buses to a memory, a chipset, etc. Each of the
processor, the memory, and the chipset, may potentially be
manufactured using the approaches disclosed herein.
[0124] FIG. 14 illustrates a computing device 1400 in accordance
with one implementation of the disclosure. The computing device
1400 houses a board 1402. The board 1402 may include a number of
components, including but not limited to a processor 1404 and at
least one communication chip 1406. The processor 1404 is physically
and electrically coupled to the board 1402. In some implementations
the at least one communication chip 1406 is also physically and
electrically coupled to the board 1402. In further implementations,
the communication chip 1406 is part of the processor 1404.
[0125] Depending on its applications, computing device 1400 may
include other components that may or may not be physically and
electrically coupled to the board 1402. These other components
include, but are not limited to, volatile memory (e.g., DRAM),
non-volatile memory (e.g., ROM), flash memory, a graphics
processor, a digital signal processor, a crypto processor, a
chipset, an antenna, a display, a touchscreen display, a
touchscreen controller, a battery, an audio codec, a video codec, a
power amplifier, a global positioning system (GPS) device, a
compass, an accelerometer, a gyroscope, a speaker, a camera, and a
mass storage device (such as hard disk drive, compact disk (CD),
digital versatile disk (DVD), and so forth).
[0126] The communication chip 1406 enables wireless communications
for the transfer of data to and from the computing device 1400. The
term "wireless" and its derivatives may be used to describe
circuits, devices, systems, methods, techniques, communications
channels, etc., that may communicate data through the use of
modulated electromagnetic radiation through a non-solid medium. The
term does not imply that the associated devices do not contain any
wires, although in some embodiments they might not. The
communication chip 1406 may implement any of a number of wireless
standards or protocols, including but not limited to Wi-Fi (IEEE
802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term
evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS,
CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any
other wireless protocols that are designated as 3G, 4G, 5G, and
beyond. The computing device 1400 may include a plurality of
communication chips 1406. For instance, a first communication chip
1406 may be dedicated to shorter range wireless communications such
as Wi-Fi and Bluetooth and a second communication chip 1406 may be
dedicated to longer range wireless communications such as GPS,
EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
[0127] The processor 1404 of the computing device 1400 includes an
integrated circuit die packaged within the processor 1404. In some
implementations of embodiments of the disclosure, the integrated
circuit die of the processor includes one or more structures, such
as integrated circuit structures built in accordance with
implementations of the disclosure. The term "processor" may refer
to any device or portion of a device that processes electronic data
from registers or memory to transform that electronic data, or
both, into other electronic data that may be stored in registers or
memory, or both.
[0128] The communication chip 1406 also includes an integrated
circuit die packaged within the communication chip 1406. In
accordance with another implementation of the disclosure, the
integrated circuit die of the communication chip is built in
accordance with implementations of the disclosure.
[0129] In further implementations, another component housed within
the computing device 1400 may contain an integrated circuit die
built in accordance with implementations of embodiments of the
disclosure.
[0130] In various embodiments, the computing device 1400 may be a
laptop, a netbook, a notebook, an ultrabook, a smartphone, a
tablet, a personal digital assistant (PDA), an ultramobile PC, a
mobile phone, a desktop computer, a server, a printer, a scanner, a
monitor, a set-top box, an entertainment control unit, a digital
camera, a portable music player, or a digital video recorder. In
further implementations, the computing device 1400 may be any other
electronic device that processes data.
[0131] FIG. 15 illustrates an interposer 1500 that includes one or
more embodiments of the disclosure. The interposer 1500 is an
intervening substrate used to bridge a first substrate 1502 to a
second substrate 1504. The first substrate 1502 may be, for
instance, an integrated circuit die. The second substrate 1504 may
be, for instance, a memory module, a computer motherboard, or
another integrated circuit die. Generally, the purpose of an
interposer 1500 is to spread a connection to a wider pitch or to
reroute a connection to a different connection. For example, an
interposer 1500 may couple an integrated circuit die to a ball grid
array (BGA) 1506 that can subsequently be coupled to the second
substrate 1504. In some embodiments, the first and second
substrates 1502/1504 are attached to opposing sides of the
interposer 1500. In other embodiments, the first and second
substrates 1502/1504 are attached to the same side of the
interposer 1500. And in further embodiments, three or more
substrates are interconnected by way of the interposer 1500.
[0132] The interposer 1500 may be formed of an epoxy resin, a
fiberglass-reinforced epoxy resin, a ceramic material, or a polymer
material such as polyimide. In further implementations, the
interposer may be formed of alternate rigid or flexible materials
that may include the same materials described above for use in a
semiconductor substrate, such as silicon, germanium, and other
group III-V and group IV materials.
[0133] The interposer may include metal interconnects 1508 and vias
1510, including but not limited to through-silicon vias (TSVs)
1512. The interposer 1500 may further include embedded devices
1514, including both passive and active devices. Such devices
include, but are not limited to, capacitors, decoupling capacitors,
resistors, inductors, fuses, diodes, transformers, sensors, and
electrostatic discharge (ESD) devices. More complex devices such as
radio-frequency (RF) devices, power amplifiers, power management
devices, antennas, arrays, sensors, and MEMS devices may also be
formed on the interposer 1500. In accordance with embodiments of
the disclosure, apparatuses or processes disclosed herein may be
used in the fabrication of interposer 1500 or in the fabrication of
components included in the interposer 1500.
[0134] FIG. 16 is an isometric view of a mobile computing platform
1600 employing an integrated circuit (IC) fabricated according to
one or more processes described herein or including one or more
features described herein, in accordance with an embodiment of the
present disclosure.
[0135] The mobile computing platform 1600 may be any portable
device configured for each of electronic data display, electronic
data processing, and wireless electronic data transmission. For
example, mobile computing platform 1600 may be any of a tablet, a
smart phone, laptop computer, etc. and includes a display screen
1605 which in the exemplary embodiment is a touchscreen
(capacitive, inductive, resistive, etc.), a chip-level (SoC) or
package-level integrated system 1610, and a battery 1613. As
illustrated, the greater the level of integration in the system
1610 enabled by higher transistor packing density, the greater the
portion of the mobile computing platform 1600 that may be occupied
by the battery 1613 or non-volatile storage, such as a solid state
drive, or the greater the transistor gate count for improved
platform functionality. Similarly, the greater the carrier mobility
of each transistor in the system 1610, the greater the
functionality. As such, techniques described herein may enable
performance and form factor improvements in the mobile computing
platform 1600.
[0136] The integrated system 1610 is further illustrated in the
expanded view 1620. In the exemplary embodiment, packaged device
1677 includes at least one memory chip (e.g., RAM), or at least one
processor chip (e.g., a multi-core microprocessor and/or graphics
processor) fabricated according to one or more processes described
herein or including one or more features described herein. The
packaged device 1677 is further coupled to the board 1660 along
with one or more of a power management integrated circuit (PMIC)
1615, RF (wireless) integrated circuit (RFIC) 1625 including a
wideband RF (wireless) transmitter and/or receiver (e.g., including
a digital baseband and an analog front end module further include a
power amplifier on a transmit path and a low noise amplifier on a
receive path), and a controller thereof 1611. Functionally, the
PMIC 1615 performs battery power regulation, DC-to-DC conversion,
etc., and so has an input coupled to the battery 1613 and with an
output providing a current supply to all the other functional
modules. As further illustrated, in the exemplary embodiment, the
RFIC 1625 has an output coupled to an antenna to provide to
implement any of a number of wireless standards or protocols,
including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX
(IEEE 802.16 family), IEEE 802.20, long term evolution (LTE),
Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT,
Bluetooth, derivatives thereof, as well as any other wireless
protocols that are designated as 3G, 4G, 5G, and beyond. In
alternative implementations, each of these board-level modules may
be integrated onto separate ICs coupled to the package substrate of
the packaged device 1677 or within a single IC (SoC) coupled to the
package substrate of the packaged device 1677.
[0137] In another aspect, semiconductor packages are used for
protecting an integrated circuit (IC) chip or die, and also to
provide the die with an electrical interface to external circuitry.
With the increasing demand for smaller electronic devices,
semiconductor packages are designed to be even more compact and
must support larger circuit density. Furthermore, the demand for
higher performance devices results in a need for an improved
semiconductor package that enables a thin packaging profile and low
overall warpage compatible with subsequent assembly processing.
[0138] In an embodiment, wire bonding to a ceramic or organic
package substrate is used. In another embodiment, a C4 process is
used to mount a die to a ceramic or organic package substrate. In
particular, C4 solder ball connections can be implemented to
provide flip chip interconnections between semiconductor devices
and substrates. A flip chip or Controlled Collapse Chip Connection
(C4) is a type of mounting used for semiconductor devices, such as
integrated circuit (IC) chips, MEMS or components, which utilizes
solder bumps instead of wire bonds. The solder bumps are deposited
on the C4 pads, located on the top side of the substrate package.
In order to mount the semiconductor device to the substrate, it is
flipped over with the active side facing down on the mounting area.
The solder bumps are used to connect the semiconductor device
directly to the substrate.
[0139] FIG. 17 illustrates a cross-sectional view of a flip-chip
mounted die, in accordance with an embodiment of the present
disclosure.
[0140] Referring to FIG. 17, an apparatus 1700 includes a die 1702
such as an integrated circuit (IC) fabricated according to one or
more processes described herein or including one or more features
described herein, in accordance with an embodiment of the present
disclosure. The die 1702 includes metallized pads 1704 thereon. A
package substrate 1706, such as a ceramic or organic substrate,
includes connections 1708 thereon. The die 1702 and package
substrate 1706 are electrically connected by solder balls 1710
coupled to the metallized pads 1704 and the connections 1708. An
underfill material 1712 surrounds the solder balls 1710.
[0141] Processing a flip chip may be similar to conventional IC
fabrication, with a few additional operations. Near the end of the
manufacturing process, the attachment pads are metalized to make
them more receptive to solder. This typically consists of several
treatments. A small dot of solder is then deposited on each
metalized pad. The chips are then cut out of the wafer as normal.
To attach the flip chip into a circuit, the chip is inverted to
bring the solder dots down onto connectors on the underlying
electronics or circuit board. The solder is then re-melted to
produce an electrical connection, typically using an ultrasonic or
alternatively reflow solder process. This also leaves a small space
between the chip's circuitry and the underlying mounting. In most
cases an electrically-insulating adhesive is then "underfilled" to
provide a stronger mechanical connection, provide a heat bridge,
and to ensure the solder joints are not stressed due to
differential heating of the chip and the rest of the system.
[0142] In other embodiments, newer packaging and die-to-die
interconnect approaches, such as through silicon via (TSV) and
silicon interposer, are implemented to fabricate high performance
Multi-Chip Module (MCM) and System in Package (SiP) incorporating
an integrated circuit (IC) fabricated according to one or more
processes described herein or including one or more features
described herein, in accordance with an embodiment of the present
disclosure.
[0143] Thus, embodiments of the present disclosure include fin trim
plug structures for imparting channel stress, and methods of
fabricating fin trim plug structures for imparting channel
stress.
[0144] Although specific embodiments have been described above,
these embodiments are not intended to limit the scope of the
present disclosure, even where only a single embodiment is
described with respect to a particular feature. Examples of
features provided in the disclosure are intended to be illustrative
rather than restrictive unless stated otherwise. The above
description is intended to cover such alternatives, modifications,
and equivalents as would be apparent to a person skilled in the art
having the benefit of the present disclosure.
[0145] The scope of the present disclosure includes any feature or
combination of features disclosed herein (either explicitly or
implicitly), or any generalization thereof, whether or not it
mitigates any or all of the problems addressed herein. Accordingly,
new claims may be formulated during prosecution of the present
application (or an application claiming priority thereto) to any
such combination of features. In particular, with reference to the
appended claims, features from dependent claims may be combined
with those of the independent claims and features from respective
independent claims may be combined in any appropriate manner and
not merely in the specific combinations enumerated in the appended
claims.
[0146] The following examples pertain to further embodiments. The
various features of the different embodiments may be variously
combined with some features included and others excluded to suit a
variety of different applications.
Example Embodiment 1
[0147] An integrated circuit structure includes a fin including
silicon, the fin having a top and sidewalls. The fin has a trench
separating a first fin portion and a second fin portion. A first
gate structure including a gate electrode is over the top of and
laterally adjacent to the sidewalls of the first fin portion. A
second gate structure including a gate electrode is over the top of
and laterally adjacent to the sidewalls of the second fin portion.
An isolation structure is in the trench of the fin, the isolation
structure between the first gate structure and the second gate
structure. The isolation structure includes a first dielectric
material laterally surrounding a recessed second dielectric
material distinct from the first dielectric material, the recessed
second dielectric material laterally surrounding an oxidation
catalyst layer.
Example Embodiment 2
[0148] The integrated circuit structure of example embodiment 1,
wherein the oxidation catalyst layer includes aluminum oxide.
Example Embodiment 3
[0149] The integrated circuit structure of example embodiment 1,
wherein the oxidation catalyst layer includes lanthanum oxide.
Example Embodiment 4
[0150] The integrated circuit structure of example embodiment 1, 2
or 3, wherein the isolation structure further includes a third
dielectric material laterally surrounded by an upper portion of the
first dielectric material, the third dielectric material on an
upper surface of the oxidation catalyst layer.
Example Embodiment 5
[0151] The integrated circuit structure of example embodiment 4,
wherein the third dielectric material is further on an upper
surface of the second dielectric material.
Example Embodiment 6
[0152] The integrated circuit structure of example embodiment 1, 2,
3, 4 or 5, wherein the oxidation catalyst layer has an upper
surface co-planar with an upper surface of the second dielectric
material.
Example Embodiment 7
[0153] The integrated circuit structure of example embodiment 1, 2,
3, 4 or 5, wherein the oxidation catalyst layer has an upper
surface above an upper surface of the second dielectric
material.
Example Embodiment 8
[0154] An integrated circuit structure includes a fin including
silicon, the fin having a top and sidewalls, wherein the top has a
longest dimension along a direction. A first isolation structure is
over a first end of the fin. A gate structure includes a gate
electrode over the top of and laterally adjacent to the sidewalls
of a region of the fin, wherein the gate structure is spaced apart
from the first isolation structure along the direction. A second
isolation structure is over a second end of the fin, the second end
opposite the first end. The second isolation structure is spaced
apart from the gate structure along the direction, wherein the
first isolation structure and the second isolation structure both
include a first dielectric material laterally surrounding a
recessed second dielectric material distinct from the first
dielectric material. The recessed second dielectric material
laterally surrounds an oxidation catalyst layer.
Example Embodiment 9
[0155] The integrated circuit structure of example embodiment 8,
wherein the isolation structure further includes a third dielectric
material laterally surrounded by an upper portion of the first
dielectric material, the third dielectric material on an upper
surface of the oxidation catalyst layer.
Example Embodiment 10
[0156] The integrated circuit structure of example embodiment 9,
wherein the third dielectric material is further on an upper
surface of the second dielectric material.
Example Embodiment 11
[0157] The integrated circuit structure of example embodiment 8, 9
or 10, wherein the oxidation catalyst layer has an upper surface
co-planar with an upper surface of the second dielectric
material.
Example Embodiment 12
[0158] The integrated circuit structure of example embodiment 8, 9
or 10, wherein the oxidation catalyst layer has an upper surface
above an upper surface of the second dielectric material.
Example Embodiment 13
[0159] The integrated circuit structure of example embodiment 8, 9,
10, 11 or 12, wherein the first and second isolation structures
induce a compressive stress on the fin.
Example Embodiment 14
[0160] The integrated circuit structure of example embodiment 8, 9,
10, 11, 12 or 13, wherein the gate electrode is a P-type gate
electrode.
Example Embodiment 15
[0161] The integrated circuit structure of example embodiment 8, 9,
10, 11, 12, 13 or 14, wherein the first isolation structure has a
width along the direction, the gate structure has the width along
the direction, and the second isolation structure has the width
along the direction.
Example Embodiment 16
[0162] The integrated circuit structure of example embodiment 15,
wherein a center of the gate structure is spaced apart from a
center of the first isolation structure by a pitch along the
direction, and a center of the second isolation structure is spaced
apart from the center of the gate structure by the pitch along the
direction.
Example Embodiment 17
[0163] The integrated circuit structure of example embodiment 8, 9,
10, 11, 12, 13, 14, 15 or 16, wherein the first and second
isolation structures are both in a corresponding trench in an
inter-layer dielectric layer.
Example Embodiment 18
[0164] The integrated circuit structure of example embodiment 8, 9,
10, 11, 12, 13, 14, 15, 16 or 17, further including a first source
or drain region between the gate structure and the first isolation
structure; and a second source or drain region between the gate
structure and the second isolation structure.
Example Embodiment 19
[0165] The integrated circuit structure of example embodiment 18,
wherein the first and second source or drain regions are embedded
source or drain regions including silicon and germanium.
Example Embodiment 20
[0166] The integrated circuit structure of example embodiment 8, 9,
10, 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the gate
structure further includes a high-k dielectric layer between the
gate electrode and the fin and along sidewalls of the gate
electrode.
Example Embodiment 21
[0167] The integrated circuit structure of example embodiment 8, 9,
10, 11, 12, 13, 14, 15, 16, 17, 18, 19 or 20, wherein the oxidation
catalyst layer includes aluminum oxide or lanthanum oxide.
Example Embodiment 22
[0168] A method of fabricating an integrated circuit structure
includes forming a fin including silicon, exposing a portion of the
fin, etching the portion of the fin to form a trench separating a
first fin portion and a second fin portion, forming a layer
including silicon in the trench, forming an oxidation catalyst
layer on the layer including silicon, and oxidizing the layer
including silicon in the presence of the oxidation catalyst
layer.
Example Embodiment 23
[0169] The method of example embodiment 22, further including
recessing the layer including silicon in the trench prior to
forming the oxidation catalyst layer.
Example Embodiment 24
[0170] The method of example embodiment 22 or 23, wherein oxidizing
the layer including silicon in the presence of the oxidation
catalyst layer includes using a wet oxidation process.
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