| Patent | Date |
|---|
Advanced Lithography And Self-assembled Devices
App 20220262722 - SCHENKER; Richard E. ; et al. | 2022-08-18 |
Self-aligned Gate Endcap (sage) Architectures With Gate-all-around Devices Having Epitaxial Source Or Drain Structures
App 20220254893 - GULER; Leonard P. ; et al. | 2022-08-11 |
Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions
Grant 11,398,474 - Guler , et al. July 26, 2 | 2022-07-26 |
Advanced lithography and self-assembled devices
Grant 11,373,950 - Schenker , et al. June 28, 2 | 2022-06-28 |
Fin Shaping Using Templates And Integrated Circuit Structures Resulting Therefrom
App 20220199792 - GULER; Leonard P. ; et al. | 2022-06-23 |
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures
Grant 11,355,608 - Guler , et al. June 7, 2 | 2022-06-07 |
Fin shaping using templates and integrated circuit structures resulting therefrom
Grant 11,302,790 - Guler , et al. April 12, 2 | 2022-04-12 |
Pattern Decomposition Lithography Techniques
App 20210375807 - WALLACE; Charles H. ; et al. | 2021-12-02 |
Three-dimensional Memory Arrays With Layer Selector Transistors
App 20210335791 - Gomes; Wilfred ; et al. | 2021-10-28 |
Three-dimensional memory arrays with layer selector transistors
Grant 11,139,300 - Gomes , et al. October 5, 2 | 2021-10-05 |
Pattern decomposition lithography techniques
Grant 11,107,786 - Wallace , et al. August 31, 2 | 2021-08-31 |
Dense memory arrays utilizing access transistors with back-side contacts
Grant 11,056,492 - Gomes , et al. July 6, 2 | 2021-07-06 |
Dense Memory Arrays Utilizing Access Transistors With Back-side Contacts
App 20210193666 - Gomes; Wilfred ; et al. | 2021-06-24 |
Three-dimensional Memory Arrays With Layer Selector Transistors
App 20210151438 - Gomes; Wilfred ; et al. | 2021-05-20 |
Gate Aligned Contact And Method To Fabricate Same
App 20210125866 - GOLONZKA; Oleg ; et al. | 2021-04-29 |
Advanced Lithography And Self-assembled Devices
App 20210082800 - SCHENKER; Richard E. ; et al. | 2021-03-18 |
Gate aligned contact and method to fabricate same
Grant 10,910,265 - Golonzka , et al. February 2, 2 | 2021-02-02 |
Advanced lithography and self-assembled devices
Grant 10,892,223 - Schenker , et al. January 12, 2 | 2021-01-12 |
1d Vertical Edge Blocking (veb) Via And Plug
App 20200388534 - GULER; Leonard P. ; et al. | 2020-12-10 |
Fin Shaping Using Templates And Integrated Circuit Structures Resulting Therefrom
App 20200388689 - GULER; Leonard P. ; et al. | 2020-12-10 |
Gate-all-around Integrated Circuit Structures Having Oxide Sub-fins
App 20200219978 - GULER; Leonard P. ; et al. | 2020-07-09 |
Fin Trim Plug Structures For Imparting Channel Stress
App 20200220016 - GULER; Leonard ; et al. | 2020-07-09 |
Die Interconnection Scheme For Providing A High Yielding Process For High Performance Microprocessors
App 20200211970 - GOMES; Wilfred ; et al. | 2020-07-02 |
Gate Aligned Contact And Method To Fabricate Same
App 20200194309 - GOLONZKA; Oleg ; et al. | 2020-06-18 |
Gate aligned contact and method to fabricate same
Grant 10,607,884 - Golonzka , et al. | 2020-03-31 |
Self-aligned Gate Endcap (sage) Architectures With Gate-all-around Devices Having Epitaxial Source Or Drain Structures
App 20200098878 - GULER; Leonard P. ; et al. | 2020-03-26 |
Self-aligned isotropic etch of pre-formed vias and plugs for back end of line (BEOL) interconnects
Grant 10,600,678 - Wallace , et al. | 2020-03-24 |
Pattern Decomposition Lithography Techniques
App 20200091101 - WALLACE; CHARLES H. ; et al. | 2020-03-19 |
Neighboring Gate-all-around Integrated Circuit Structures Having Disjoined Epitaxial Source Or Drain Regions
App 20200091144 - GULER; Leonard P. ; et al. | 2020-03-19 |
Advanced Lithography And Self-assembled Devices
App 20200066629 - SCHENKER; Richard E. ; et al. | 2020-02-27 |
Pattern decomposition lithography techniques
Grant 10,490,519 - Wallace , et al. Nov | 2019-11-26 |
Exposure activated chemically amplified directed self-assembly (DSA) for back end of line (BEOL) pattern cutting and plugging
Grant 10,459,338 - Nyhus , et al. Oc | 2019-10-29 |
Pattern decomposition lithography techniques
Grant 10,409,152 - Wallace , et al. Sept | 2019-09-10 |
Gate Aligned Contact And Method To Fabricate Same
App 20190267286 - GOLONZKA; Oleg ; et al. | 2019-08-29 |
Gate aligned contact and method to fabricate same
Grant 10,340,185 - Golonzka , et al. | 2019-07-02 |
Patterning of vertical nanowire transistor channel and gate with directed self assembly
Grant 10,325,814 - Nyhus , et al. | 2019-06-18 |
Self-aligned Isotropic Etch Of Pre-formed Vias And Plugs For Back End Of Line (beol) Interconnects
App 20190148220 - WALLACE; Charles H. ; et al. | 2019-05-16 |
Self-aligned isotropic etch of pre-formed vias and plugs for back end of line (BEOL) interconnects
Grant 10,211,088 - Wallace , et al. Feb | 2019-02-19 |
Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects
Grant 10,204,830 - Wallace , et al. Feb | 2019-02-12 |
Self-aligned Isotropic Etch Of Pre-formed Vias And Plugs For Back End Of Line (beol) Interconnects
App 20180204763 - WALLACE; Charles H. ; et al. | 2018-07-19 |
Previous Layer Self-aligned Via And Plug Patterning For Back End Of Line (beol) Interconnects
App 20180033692 - WALLACE; Charles H. ; et al. | 2018-02-01 |
Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects
Grant 9,793,159 - Wallace , et al. October 17, 2 | 2017-10-17 |
Gate Aligned Contact And Method To Fabricate Same
App 20170294350 - GOLONZKA; Oleg ; et al. | 2017-10-12 |
Patterning Of Vertical Nanowire Transistor Channel And Gate With Directed Self Assembly
App 20170236757 - Nyhus; Paul A. ; et al. | 2017-08-17 |
Gate aligned contact and method to fabricate same
Grant 9,716,037 - Golonzka , et al. July 25, 2 | 2017-07-25 |
Exposure Activated Chemically Amplified Directed Self-assembly (dsa) For Back End Of Line (beol) Pattern Cutting And Plugging
App 20170207116 - Nyhus; Paul A. ; et al. | 2017-07-20 |
Pattern Decomposition Lithography Techniques
App 20170207185 - WALLACE; CHARLES H. ; et al. | 2017-07-20 |
Pattern Decomposition Lithography Techniques
App 20170139318 - WALLACE; CHARLES H. ; et al. | 2017-05-18 |
Patterning of vertical nanowire transistor channel and gate with directed self assembly
Grant 9,653,576 - Nyhus , et al. May 16, 2 | 2017-05-16 |
Exposure activated chemically amplified directed self-assembly (DSA) for back end of line (BEOL) pattern cutting and plugging
Grant 9,625,815 - Nyhus , et al. April 18, 2 | 2017-04-18 |
Pattern decomposition lithography techniques
Grant 9,558,947 - Wallace , et al. January 31, 2 | 2017-01-31 |
Directed self assembly of block copolymers to form vias aligned with interconnects
Grant 9,530,688 - Nyhus , et al. December 27, 2 | 2016-12-27 |
Patterning Of Vertical Nanowire Transisor Channel And Gate With Directed Self Assembly
App 20160365429 - NYHUS; Paul A. ; et al. | 2016-12-15 |
Patterning of vertical nanowire transistor channel and gate with directed self assembly
Grant 9,431,518 - Nyhus , et al. August 30, 2 | 2016-08-30 |
Previous Layer Self-Aligned Via and Plug Patterning for Back End of Line (BEOL)Interconnects
App 20160190009 - WALLACE; CHARLES H. ; et al. | 2016-06-30 |
Patterning Of Vertical Nanowire Transistor Channel And Gate With Directed Self Assembly
App 20160133724 - NYHUS; Paul A. ; et al. | 2016-05-12 |
Patterning of vertical nanowire transistor channel and gate with directed self assembly
Grant 9,269,630 - Nyhus , et al. February 23, 2 | 2016-02-23 |
Embedded memory device having MIM capacitor formed in excavated structure
Grant 9,224,794 - Keating , et al. December 29, 2 | 2015-12-29 |
Directed Self Assembly Of Block Copolymers To Form Vias Aligned With Interconnects
App 20150348839 - Nyhus; Paul A. ; et al. | 2015-12-03 |
Patterning Of Vertical Nanowire Transistor Channel And Gate With Directed Self Assembly
App 20150270374 - NYHUS; Paul A. ; et al. | 2015-09-24 |
Double patterning lithography techniques
Grant 9,142,421 - Wallace , et al. September 22, 2 | 2015-09-22 |
Patterning of vertical nanowire transistor channel and gate with directed self assembly
Grant 9,054,215 - Nyhus , et al. June 9, 2 | 2015-06-09 |
Lithography mask having sub-resolution phased assist features
Grant 9,046,761 - Ogadhoh , et al. June 2, 2 | 2015-06-02 |
Exposure Activated Chemically Amplified Directed Self-assembly (dsa) For Back End Of Line (beol) Pattern Cutting And Plugging
App 20150093702 - Nyhus; Paul A. ; et al. | 2015-04-02 |
Techniques for phase tuning for process optimization
Grant 8,959,465 - Nyhus , et al. February 17, 2 | 2015-02-17 |
Spacer assisted pitch division lithography
Grant 8,860,184 - Sivakumar , et al. October 14, 2 | 2014-10-14 |
Spacer Assisted Pitch Division Lithography
App 20140191372 - Sivakumar; Swaminathan ; et al. | 2014-07-10 |
Patterning Of Vertical Nanowire Transistor Channel And Gate With Directed Self Assembly
App 20140170821 - NYHUS; Paul A. ; et al. | 2014-06-19 |
Pattern Decomposition Lithography Techniques
App 20140117488 - Wallace; Charles H. ; et al. | 2014-05-01 |
Techniques For Phase Tuning For Process Optimization
App 20140053117 - Nyhus; Paul A. ; et al. | 2014-02-20 |
Double Patterning Lithography Techniques
App 20140017899 - Wallace; Charles H. ; et al. | 2014-01-16 |
Gate Aligned Contact And Method To Fabricate Same
App 20130320456 - Golonzka; Oleg ; et al. | 2013-12-05 |
Method Of Patterning A Metal On A Vertical Sidewall Of An Excavated Feature, Method Of Forming An Embedded Mim Capacitor Using Same, And Embedded Memory Device Produced Thereby
App 20130234290 - Keating; Steven ; et al. | 2013-09-12 |
6F2 DRAM cell
Grant 8,519,462 - Wang , et al. August 27, 2 | 2013-08-27 |
Lithography Mask Having Sub-resolution Phased Assist Features
App 20130216941 - Ogadhoh; Shem O. ; et al. | 2013-08-22 |
Embedded memory device having MIM capacitor formed in excavated structure
Grant 8,441,057 - Keating , et al. May 14, 2 | 2013-05-14 |
6F2 DRAM Cell
App 20120326218 - Wang; Yih ; et al. | 2012-12-27 |
Illumination aperture for optical lithography
Grant 8,233,210 - Wallace , et al. July 31, 2 | 2012-07-31 |
Transistor having raised source/drain self-aligned contacts and method of forming same
Grant 8,013,426 - Sivakumar September 6, 2 | 2011-09-06 |
Common plate capacitor array connections, and processes of making same
Grant 7,981,756 - Lindert , et al. July 19, 2 | 2011-07-19 |
Method Of Patterning A Metal On A Vertical Sidewall Of An Excavated Feature, Method Of Forming An Embedded Mim Capacitor Using Same, And Embedded Memory Device Produced Thereby
App 20110134583 - Keating; Steve J. ; et al. | 2011-06-09 |
Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby
Grant 7,927,959 - Keating , et al. April 19, 2 | 2011-04-19 |
Double patterning techniques and structures
Grant 7,915,171 - Wallace , et al. March 29, 2 | 2011-03-29 |
Negative tone double patterning method
Grant 7,820,550 - Nyhus , et al. October 26, 2 | 2010-10-26 |
Lithography masks for improved line-end patterning
Grant 7,816,061 - Schenker , et al. October 19, 2 | 2010-10-19 |
Forming self-aligned nano-electrodes
Grant 7,755,082 - Dubin , et al. July 13, 2 | 2010-07-13 |
Method for Forming Semiconductor Contacts
App 20100171156 - Rahhal-Orabi; Nadia ; et al. | 2010-07-08 |
Illumination aperture for optical lithography
App 20100165317 - Wallace; Charles ; et al. | 2010-07-01 |
Common plate capacitor array connections, and processes of making same
App 20100155887 - Lindert; Nick ; et al. | 2010-06-24 |
Method for forming semiconductor contacts
Grant 7,709,866 - Rahhal-Orabi , et al. May 4, 2 | 2010-05-04 |
Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby
App 20100079924 - Keating; Steven J. ; et al. | 2010-04-01 |
Negative Tone Double Patterning Method
App 20100062228 - Nyhus; Paul ; et al. | 2010-03-11 |
Double Patterning Techniques And Structures
App 20090267175 - Wallace; Charles H. ; et al. | 2009-10-29 |
Methods for double patterning photoresist
App 20090263751 - Sivakumar; Swaminathan ; et al. | 2009-10-22 |
Non-collinear end-to-end structures with sub-resolution assist features
Grant 7,572,557 - Wallace , et al. August 11, 2 | 2009-08-11 |
Transistor Having Raised Source/Drain Self-Aligned Contacts And Method Of Forming Same
App 20090166759 - Sivakumar; Swaminathan | 2009-07-02 |
Cross-shaped sub-resolution assist feature
Grant 7,521,157 - Wallace , et al. April 21, 2 | 2009-04-21 |
Method for forming semiconductor contacts
App 20090001431 - Rahhal-Orabi; Nadia ; et al. | 2009-01-01 |
Lithography masks for improved line-end patterning
App 20080318137 - Schenker; Richard ; et al. | 2008-12-25 |
Forming self-aligned nano-electrodes
App 20080116439 - Dubin; Valery M. ; et al. | 2008-05-22 |
Imageable bottom anti-reflective coating for high resolution lithography
Grant 7,358,111 - Sivakumar April 15, 2 | 2008-04-15 |
Forming self-aligned nano-electrodes
Grant 7,312,155 - Dubin , et al. December 25, 2 | 2007-12-25 |
Patterning trenches in a photoresist layer with tight end-to-end separation
App 20070231748 - Sivakumar; Swaminathan ; et al. | 2007-10-04 |
Method of forming trench contacts for MOS transistors
App 20070218685 - Sivakumar; Swaminathan ; et al. | 2007-09-20 |
Imageable bottom anti-reflective coating for high resolution lithography
Grant 7,265,431 - Sivakumar September 4, 2 | 2007-09-04 |
Pre-exposure of patterned photoresist films to achieve critical dimension reduction during temperature reflow
Grant 7,258,965 - Frost , et al. August 21, 2 | 2007-08-21 |
Cross-shaped sub-resolution assist feature
App 20070184355 - Wallace; Charles H. ; et al. | 2007-08-09 |
Non-collinear end-to-end structures with sub-resolution assist features
App 20070128526 - Wallace; Charles H. ; et al. | 2007-06-07 |
Imageable bottom anti-reflective coating for high resolution lithography
App 20060051956 - Sivakumar; Swaminathan | 2006-03-09 |
Solvent vapor-assisted plasticization of photoresist films to achieve critical dimension reduction during temperature reflow
Grant 6,977,219 - Frost , et al. December 20, 2 | 2005-12-20 |
Photoresist process to enable sloped passivation bondpad openings for ease of metal step coverings
App 20050263899 - Sivakumar, Swaminathan ; et al. | 2005-12-01 |
Multiple exposure and shrink to achieve reduced dimensions
App 20050255411 - Frost, Rex ; et al. | 2005-11-17 |
Forming self-aligned nano-electrodes
App 20050224778 - Dubin, Valery M. ; et al. | 2005-10-13 |
Method of evaluating the quality of a contact plug fill
Grant 6,927,082 - Sivakumar , et al. August 9, 2 | 2005-08-09 |
Pre-exposure of patterned photoresist films to achieve critical dimension reduction during temperature reflow
App 20050147928 - Frost, Rex K. ; et al. | 2005-07-07 |
Photoresist process to enable sloped passivation bondpad openings for ease of metal step coverings
App 20050148180 - Sivakumar, Swaminathan ; et al. | 2005-07-07 |
Solvent vapor-assisted plasticization of photoresist films to achieve critical dimension reduction during temperature reflow
App 20050148169 - Frost, Rex K. ; et al. | 2005-07-07 |
Using water soluble bottom anti-reflective coating
App 20040077173 - Sivakumar, Swaminathan | 2004-04-22 |
Imageable bottom anti-reflective coating for high resolution ligthography
App 20030213968 - Sivakumar, Swaminathan | 2003-11-20 |
Patterning tighter and looser pitch geometries
App 20030207584 - Sivakumar, Swaminathan ; et al. | 2003-11-06 |
Method of controlling etch bias with a fixed lithography pattern for sub-micron critical dimension shallow trench applications
Grant 5,933,759 - Nguyen , et al. August 3, 1 | 1999-08-03 |
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