U.S. patent application number 16/160224 was filed with the patent office on 2020-04-16 for step pyramid shaped structure to reduce dicing defects.
The applicant listed for this patent is INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to Shidong Li, Kirk D. Peterson, Nicolas Pizzuti, Thomas M. Shaw, Thomas A. Wassick.
Application Number | 20200118942 16/160224 |
Document ID | / |
Family ID | 70159657 |
Filed Date | 2020-04-16 |
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United States Patent
Application |
20200118942 |
Kind Code |
A1 |
Li; Shidong ; et
al. |
April 16, 2020 |
STEP PYRAMID SHAPED STRUCTURE TO REDUCE DICING DEFECTS
Abstract
A semiconductor device which includes a substrate having
integrated circuits; and metallization layers on the substrate, the
metallization layers having a peripheral region adjacent to a kerf
region of the semiconductor device and containing a crack stop
structure. The crack stop structure includes a bottom portion
containing a plurality of the metallization layers connected by
vias with each metallization layer decreasing in width in a step
pyramid structure from a bottom of the bottom portion to a top of
the bottom portion; and a top portion containing a top
metallization layer of the metallization layers connected to the
bottom portion, the top metallization layer being wider than a
top-most metallization layer of the bottom portion and having a
segment that extends toward the kerf region so as to create an
overhang with respect to the bottom portion.
Inventors: |
Li; Shidong; (Poughkeepsie,
NY) ; Peterson; Kirk D.; (Jericho, VT) ;
Pizzuti; Nicolas; (Waterbury, VT) ; Shaw; Thomas
M.; (Peekskill, NY) ; Wassick; Thomas A.;
(LaGrangeville, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
Armonk |
NY |
US |
|
|
Family ID: |
70159657 |
Appl. No.: |
16/160224 |
Filed: |
October 15, 2018 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 23/585 20130101;
H01L 2223/5446 20130101; H01L 23/562 20130101; H01L 21/78 20130101;
H01L 23/544 20130101 |
International
Class: |
H01L 23/00 20060101
H01L023/00; H01L 23/544 20060101 H01L023/544; H01L 21/78 20060101
H01L021/78 |
Claims
1. A semiconductor device comprising: a substrate having integrated
circuits; metallization layers on the substrate, the metallization
layers having a peripheral region adjacent to a kerf region of the
semiconductor device and containing a crack stop structure
comprising: a bottom portion containing a plurality of the
metallization layers connected by vias with each metallization
layer decreasing in width in a step pyramid structure from a bottom
of the bottom portion to a top of the bottom portion; and a top
portion containing a top metallization layer of the metallization
layers connected to the bottom portion, the top metallization layer
being wider than a top-most metallization layer of the bottom
portion and having a segment that extends toward the kerf region so
as to create an overhang with respect to the bottom portion;
wherein the vias that connect each metallization layer to an
adjacent metallization layer are spaced entirely across each
metallization layer immediately above the vias.
2. The semiconductor device of claim 1 wherein the outermost via on
each metallization layer of the bottom portion is aligned with an
edge of the metallization layer immediately above the outermost
via.
3. (canceled)
4. The semiconductor device of claim 1 wherein all metallization
layers are symmetrically aligned such that each metallization layer
is situated above a middle of the metallization layer immediately
below.
5. A semiconductor device comprising: a substrate having integrated
circuits; metallization layers on the substrate, the metallization
layers having a peripheral region adjacent to a kerf region of the
semiconductor device and containing a crack stop structure
comprising: a bottom portion containing a plurality of the
metallization layers connected by vias with each metallization
layer decreasing in width in a step pyramid structure from a bottom
of the bottom portion to a top of the bottom portion; and a top
portion containing a top metallization layer of the metallization
layers connected to the bottom portion, the top metallization layer
being wider than a top-most metallization layer of the bottom
portion and having a segment that extends toward the kerf region so
as to create an overhang with respect to the bottom portion;
wherein all metallization layers in the bottom portion have the
step pyramid structure only on a side facing the kerf and are
vertically aligned with the top metallization layer on a side
facing away from the kerf.
6. The semiconductor structure of claim 5 wherein at least one
metallization layer in the bottom portion is discontinuous.
7. The semiconductor structure of claim 1 wherein the crack stop
structure is continuous around the entire periphery of the
semiconductor device.
8. The semiconductor structure of claim 1 wherein the crack stop
structure is electrically inoperable.
9. A semiconductor device comprising: a substrate having integrated
circuits; metallization layers on the substrate, the metallization
layers having a peripheral region adjacent to a kerf region of the
semiconductor device and containing a crack stop structure
comprising: a plurality of metallization layers connected by vias
with each metallization layer decreasing in width in a step pyramid
structure and a top metallization layer connected to the plurality
of metallization layers in the step pyramid structure, the top
metallization layer being wider than the top-most metallization
layer in the step pyramid structure and having a segment that
extends toward the kerf region so as to create an overhang with
respect to the step pyramid structure; wherein the vias that
connect each metallization layer to an adjacent metallization layer
are spaced entirely across each metallization layer immediately
above the vias.
10. The semiconductor device of claim 9 wherein the outermost via
on each metallization layer in the step pyramid structure is
aligned with an edge of the metallization layer immediately above
the outermost via.
11. (canceled)
12. The semiconductor device of claim 9 wherein all metallization
layers are symmetrically aligned such that each metallization layer
is situated above a middle of the metallization layer immediately
below.
13. A semiconductor device comprising: a substrate having
integrated circuits; metallization layers on the substrate, the
metallization layers having a peripheral region adjacent to a kerf
region of the semiconductor device and containing a crack stop
structure comprising: a plurality of metallization layers connected
by vias with each metallization layer decreasing in width in a step
pyramid structure and a top metallization layer connected to the
plurality of metallization layers in the step pyramid structure,
the top metallization layer being wider than the top-most
metallization layer in the step pyramid structure and having a
segment that extends toward the kerf region so as to create an
overhang with respect to the step pyramid structure; wherein all
metallization layers in the step pyramid structure have the step
pyramid structure only on a side facing the kerf and are vertically
aligned with the top metallization layer on a side facing away from
the kerf.
14. The semiconductor structure of claim 13 wherein metallization
layers in the step pyramid structure have the step pyramid
structure on a at least one metallization layer in a bottom portion
of the step pyramid structure is discontinuous.
15. The semiconductor structure of claim 9 wherein the crack stop
structure is continuous around the entire periphery of the
semiconductor device.
16. The semiconductor structure of claim 9 wherein the crack stop
structure is electrically inoperable.
17. A method of stopping cracks in a semiconductor device
comprising a substrate having integrated circuits and metallization
layers on the substrate, the method comprising: forming a
peripheral region in the metallization layers adjacent to a kerf
region of the semiconductor device; forming a crack stop structure
comprising: a plurality of metallization layers connected by vias
with each metallization layer decreasing in width in a step pyramid
structure and a top metallization layer connected to the plurality
of metallization layers in the step pyramid structure, the top
metallization layer being wider than the top-most metallization
layer in the step pyramid structure and having a segment that
extends toward the kerf region so as to create an overhang with
respect to the step pyramid structure, wherein the vias that
connect each metallization layer to an adjacent metallization layer
are spaced entirely across each metallization layer immediately
above the vias; dicing the semiconductor device in the kerf region;
and stopping any cracks extending from the kerf region by directing
the cracks upward to an area encompassed by the step pyramid
structure and the top metallization layer.
18. The method of claim 17 wherein the crack stop structure is
continuous around the entire periphery of the semiconductor
device.
19. The method of claim 17 wherein the crack stop structure is
electrically inoperable.
20. The method of claim 17 wherein the outermost via on each
metallization layer in the step pyramid structure is aligned with
an edge of the metallization layer immediately above the outermost
via.
Description
BACKGROUND
[0001] The present exemplary embodiments pertain to the manufacture
of semiconductor devices and, more particularly, to a crack stop
structure for mitigating crack formation in the semiconductor
devices during singulation.
[0002] Semiconductor devices are used in a variety of electronic
applications, such as personal computers, cell phones, digital
cameras, and other electronic equipment, as examples. Semiconductor
devices are typically fabricated by sequentially depositing
insulating or dielectric layers, conductive layers, and
semiconductive layers of material over a semiconductor substrate,
and patterning the various layers using lithography to form circuit
components and elements thereon.
[0003] Dozens or hundreds of semiconductor devices are typically
manufactured on a single semiconductor wafer. The individual die
are singulated by sawing the semiconductor devices along a scribe
line in a kerf region. The individual die are then packaged, either
separately or in a multi-chip module or other type of packaging,
for example.
[0004] A problem that may occur in semiconductor devices is that
when the die are singulated, the material layers can crack
proximate the scribe line in the kerf region, damaging the
integrated circuits within the semiconductor devices and leading to
device failures. The cracks can disrupt conductive lines, for
example, rendering the circuits inoperable. The cracks can also
allow moisture and other contaminants to enter into the integrated
circuit, causing corrosion, for example.
BRIEF SUMMARY
[0005] The various advantages and purposes of the exemplary
embodiments as described above and hereafter are achieved by
providing, according to an aspect of the exemplary embodiments, a
semiconductor device comprising: a substrate having integrated
circuits; and metallization layers on the substrate, the
metallization layers having a peripheral region adjacent to a kerf
region of the semiconductor device and containing a crack stop
structure. The crack stop structure comprising: a bottom portion
containing a plurality of the metallization layers connected by
vias with each metallization layer decreasing in width in a step
pyramid structure from a bottom of the bottom portion to a top of
the bottom portion; and a top portion containing a top
metallization layer of the metallization layers connected to the
bottom portion, the top metallization layer being wider than a
top-most metallization layer of the bottom portion and having a
segment that extends toward the kerf region so as to create an
overhang with respect to the bottom portion.
[0006] According to another aspect of the exemplary embodiments,
there is provided a semiconductor device comprising: a substrate
having integrated circuits; and metallization layers on the
substrate, the metallization layers having a peripheral region
adjacent to a kerf region of the semiconductor device and
containing a crack stop structure. The crack stop structure
comprising: a plurality of metallization layers connected by vias
with each metallization layer decreasing in width in a step pyramid
structure and a top metallization layer connected to the plurality
of metallization layers in the step pyramid structure, the top
metallization layer being wider than the top-most metallization
layer in the step pyramid structure and having a segment that
extends toward the kerf region so as to create an overhang with
respect to the step pyramid structure.
[0007] According to a further aspect of the exemplary embodiments,
there is provided a method of stopping cracks in a semiconductor
device comprising a substrate having integrated circuits and
metallization layers on the substrate, the method comprising:
forming a peripheral region in the metallization layers adjacent to
a kerf region of the semiconductor device; forming a crack stop
structure comprising: a plurality of metallization layers connected
by vias with each metallization layer decreasing in width in a step
pyramid structure and a top metallization layer connected to the
plurality of metallization layers in the step pyramid structure,
the top metallization layer being wider than the top-most
metallization layer in the step pyramid structure and having a
segment that extends toward the kerf region so as to create an
overhang with respect to the step pyramid structure; dicing the
semiconductor device in the kerf region; and stopping any cracks
extending from the kerf region by directing the cracks upward to an
area encompassed by the step pyramid structure and the top
metallization layer.
BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS
[0008] The features of the exemplary embodiments believed to be
novel and the elements characteristic of the exemplary embodiments
are set forth with particularity in the appended claims. The
Figures are for illustration purposes only and are not drawn to
scale. The exemplary embodiments, both as to organization and
method of operation, may best be understood by reference to the
detailed description which follows taken in conjunction with the
accompanying drawings in which:
[0009] FIG. 1 is a plan view of a semiconductor device having a
crack stop structure before singulation.
[0010] FIG. 2 is a cross sectional view of an exemplary embodiment
of the crack stop structure in FIG. 1 in the direction of arrows
A-A in FIG. 1.
[0011] FIG. 3 is a cross sectional view of the exemplary embodiment
of the crack stop structure in FIG. 1 in the direction of arrows
B-B in FIG. 1.
[0012] FIG. 4 is a cross sectional view of an undesirable
arrangement of vias and adjacent metallization layers.
[0013] FIG. 5 is a cross sectional view of a preferred arrangement
of vias and adjacent metallization layers.
[0014] FIG. 6 is a cross sectional view of another exemplary
embodiment of the crack stop structure in FIG. 1 in the direction
of arrows A-A in FIG. 1.
[0015] FIG. 7 is a cross sectional view of a further exemplary
embodiment of the crack stop structure in FIG. 1 in the direction
of arrows A-A in FIG. 1.
[0016] FIG. 8 is an illustration of a method of the exemplary
embodiments.
DETAILED DESCRIPTION
[0017] Semiconductor devices include a semiconductor substrate in
which the front end of the line components may be formed. On top of
the semiconductor substrate may be formed metallization layers
comprising alternating layers of metallization and insulation
material. There is evidence to show that dicing-induced cracks
propagate through a crack stop at the metallization layers which
leads to electrical fails.
[0018] Dicing optimization to reduce initial crack formation is
only a mitigation but not a solution.
[0019] The exemplary embodiments enhance the fracture toughness of
the crack stop structure to stop a crack from propagating passed
the crack stop structure.
[0020] Referring to the Figures in more detail, and particularly
referring to FIG. 1, there is shown a plan view of a partial
semiconductor wafer 10 having a plurality of semiconductor devices
12. Located between the semiconductor devices 12 is a kerf region
14 through which the semiconductor devices 12 may be separated in a
singulation process.
[0021] One particular semiconductor device 16 is shown with greater
detail to illustrate a crack stop structure 18. The other
semiconductor devices 12 may also have the crack stop structure 18
but the crack stop structure is not shown for clarity. The crack
stop structure 18 preferably extends around the entire periphery of
the semiconductor device 16 and preferably is continuous around the
entire periphery of the semiconductor device 16. The purpose of the
crack stop structure 18 is to stop the propagation of cracks and
thus performs no electrical function.
[0022] There may be a space 20 between the crack stop structure 18
and the edges 22 of the semiconductor device 16. Located in the
central portion 24 of the semiconductor device 16 are the
integrated circuits which perform the electrical function of the
semiconductor device 16 but are not shown here for clarity.
[0023] Referring now to FIG. 2, there is illustrated a cross
sectional view of an exemplary embodiment of the crack stop 18
structure in FIG. 1 in the direction of arrows A-A in FIG. 1.
[0024] Semiconductor substrate 26 contains the front end of the
line components and has a plurality of metallization layers 28. The
crack stop structure 18 is located within the periphery of the
semiconductor device 16 and is comprised of a peripheral portion of
the metallization layers 28. Some metallization layers 29 of the
metallization layers 28 form a step pyramid structure in which the
edges 36 of the metallization layers 29 facing the edge 22 of the
semiconductor device 16 are set back a predetermined distance 32
from the metallization layer 29 below as the step pyramid structure
is progressed towards the top of the metallization layers 29. In
the exemplary embodiment illustrated in FIG. 2, the step pyramid
structure may be formed with the edges 36 of the metallization
layers 29 facing the edge 22 of the semiconductor device 16 as well
as the edges 38 of the metallization layers 29 facing the central
portion 24 of the semiconductor device 16.
[0025] The predetermined distance 32 may change as the step pyramid
is progressed upwardly. The predetermined distance 32 may be
empirically determined. The toughening mechanism of the exemplary
embodiments will be most effective if the grade of the step pyramid
is perpendicular to the phase angle of the potential crack, which
is typically between 40 degrees and 50 degrees, more preferably 40
degrees to 42 degrees. That being said, it will be desirable to
keep the slope of the steps to the horizontal within 40 degrees to
50 degrees.
[0026] Each metallization layer 29 has a plurality of vias 34
spaced continuously from edge 36 to edge 38 of each metallization
layer to provide fracture toughness to each metallization layer
29.
[0027] The crack stop structure 18 further includes a top
metallization layer 30 which may connect to the metallization
layers 29 of the step pyramid structure by additional vias 34. It
is noted that top metallization layer 30, contrary to the other
metallization layers 29, does not follow the step pyramid structure
but rather extends toward the edge 22 of the semiconductor device
16 beyond the metallization layer 40 below so as to create an
"overhang". Top metallization layer 30 may similarly have an
"overhang" toward the central portion 24 of the semiconductor
device 16. The vias 34 that connect top metallization layer 30 to
metallization layer 40 may also be spaced continuously from edge 36
to edge 38 of metallization layer 40.
[0028] The purpose of the "overhang" of the top metallization layer
30 will now be discussed.
[0029] The lowest metallization layers, such as metallization
layers 42, are the weakest metallization layers 28. In the
exemplary embodiments, all of the metallization layers 28 have been
reinforced by adding vias 34 all across the crack stop structure
18. Further, the crack stop structure 18 has been made in a step
pyramid, except for top metallization layer 30, so that any crack
approaching the crack stop structure 18 is directed upward as
indicated by arrow 44 to the upper metallization layers 28, such as
metallization layer 40, which are more robust than the lower
metallization layers 28, such as metallization layers 42. In
general, when a crack hits the crack stop structure 18 at a
particular metallization layer, the region above this layer, the
dielectric, is not reinforced while the region below this
metallization layer is reinforced by the vias 34 arrayed across the
crack stop structure 18. Accordingly, the crack will follow the
weakest path which is upward as indicated by arrow 44.
[0030] While not wishing to be held to any particular theory, if
the crack stop structure 18 is robust enough, it forms a
compressive zone in the region adjacent to it, which may "shield"
the crack front from actually reaching the crack stop structure 18.
The upward path of the crack may eventually run into the top
metallization layer 30, the corner bounded by the top metallization
layer 30 and the adjacent metallization layer 40 which are joined
by vias 34 or the metallization layer 40 by itself. However, it is
likely that the crack may be prohibited from actually propagating
into the top metallization layer 30, the corner or the
metallization layer 40 by the compressive zone. The crack stop
structure 18 has been engineered so as to be very robust at the top
metallization layer 30, in this corner and at metallization layer
40 so that it is desirable to direct the potential crack towards
them. Any crack that runs into the top metallization layer 30, this
corner or metallization layer 40 would be effectively stopped.
[0031] FIG. 3 is a cross sectional view of the exemplary embodiment
of the crack stop structure in FIG. 1 in the direction of arrows
B-B in FIG. 1. It can be seen that the various metallization layers
28 are continuous. Further, the vias 34 are also continuous. The
continuous vias 34 may also be referred to as via bars.
[0032] One way of connecting the vias to the adjacent metallization
layers is to recess the vias from the edges of the two
metallization layers. As shown in FIG. 4, such an arrangement is
undesirable as a crack, indicated by arrow 46, could be trapped
between the metallization layers, possibly leading to delamination
of the metallization layers. Certainly, such an arrangement would
be undesirable in the lower metallization layers, such as
metallization layers 42 (FIG. 2), where the metallization layers
are the weakest.
[0033] Contrarily, a feature of the exemplary embodiments is that
with respect to the metallization layers 29 the outermost via is
aligned with the edge of the metallization layer immediately above
the via. Referring to FIG. 5, the via 34 is aligned with the edge
of metallization layer 29B although the via also connects to the
lower metallization layer 29A in the step pyramid construction of
the exemplary embodiments. In this arrangement, a crack 47 is
blocked by the robust structure of the metallization layers 29A,
29B and via 34 so the crack 47 is directed upwards.
[0034] FIG. 6 is a cross sectional view of another exemplary
embodiment of the crack stop structure in FIG. 1. It is noted that
the crack stop structure 18 illustrated in FIG. 2 is symmetrical in
that the step pyramid structure is formed on both sides of the
crack stop structure 18. In the FIG. 6 exemplary embodiment of
crack stop structure 48, the step pyramid structure is formed only
on one side of the crack stop structure 48, the side facing the
edge 22 of the semiconductor device 16 while all of the
metallization layers 28 are vertically aligned on the side facing
the central portion 24 of the semiconductor device 16.
[0035] FIG. 7 is a cross sectional view of a further exemplary
embodiment of the crack stop structure in FIG. 1. In the FIG. 7
exemplary embodiment of crack stop structure 50, the step pyramid
structure is formed only on one side of the crack stop structure
50, the side facing the edge 22 of the semiconductor device 16
while all of the metallization layers 28 are vertically aligned on
the side facing the central portion 24 of the semiconductor device
16. In addition, there is a gap 52 in at least one of the bottom
metallization layers 42.
[0036] Referring now to FIG. 8, there is illustrated a method of
stopping cracks in a semiconductor device comprising a substrate
having integrated circuits and metallization layers on the
substrate.
[0037] The method includes a peripheral region formed in the
metallization layers adjacent to a kerf region of the semiconductor
device, box 54.
[0038] A crack stop structure is formed on the semiconductor
device, box 56. The crack stop structure includes: a plurality of
metallization layers connected by vias with each metallization
layer decreasing in width in a step pyramid structure and a top
metallization layer connected to the plurality of metallization
layers in the step pyramid structure, the top metallization layer
being wider than the top most metallization layer in the step
pyramid structure and having a segment that extends toward the kerf
region so as to create an overhang with respect to the step pyramid
structure;
[0039] The semiconductor device is diced in the kerf region, box
58.
[0040] Any cracks extending from the kerf region are stopped by
directing the cracks upward to an area encompassed by the step
pyramid structure and the top metallization layer, box 60.
[0041] It will be apparent to those skilled in the art having
regard to this disclosure that other modifications of the exemplary
embodiments beyond those embodiments specifically described here
may be made without departing from the spirit of the invention.
Accordingly, such modifications are considered within the scope of
the invention as limited solely by the appended claims.
* * * * *