U.S. patent application number 16/016828 was filed with the patent office on 2019-12-26 for method for forming replacement air gap.
The applicant listed for this patent is GLOBALFOUNDRIES Inc.. Invention is credited to Laertis Economikos, Jinping Liu, Shesh Mani Pandey, Haiting Wang, Hui Zang.
Application Number | 20190393335 16/016828 |
Document ID | / |
Family ID | 68982203 |
Filed Date | 2019-12-26 |
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United States Patent
Application |
20190393335 |
Kind Code |
A1 |
Economikos; Laertis ; et
al. |
December 26, 2019 |
METHOD FOR FORMING REPLACEMENT AIR GAP
Abstract
A method of forming transistor devices with an air gap in the
replacement gate structure is disclosed including forming a
placeholder gate structure above a semiconductor material region,
forming a sidewall spacer adjacent the placeholder gate structure,
removing the placeholder gate structure to define a gate cavity
bounded by the sidewall spacer, forming a gate insulation layer in
the gate cavity, the gate insulation layer including a first
portion having a first thickness and a second portion having a
second thickness greater than the first thickness, forming a gate
electrode in the gate cavity above the gate insulation layer,
removing at least a portion of the second portion of the gate
insulation layer to define an air gap cavity adjacent the gate
electrode, and forming a first gate cap layer above the gate
electrode, wherein the first gate cap layer seals an upper end of
the air gap cavity.
Inventors: |
Economikos; Laertis;
(Wappingers Falls, NY) ; Pandey; Shesh Mani;
(Saratoga Springs, NY) ; Zang; Hui; (Guilderland,
NY) ; Wang; Haiting; (Clifton Park, NY) ; Liu;
Jinping; (Ballston Lake, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
GLOBALFOUNDRIES Inc. |
Grand Cayman |
|
KY |
|
|
Family ID: |
68982203 |
Appl. No.: |
16/016828 |
Filed: |
June 25, 2018 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/6681 20130101;
H01L 29/42376 20130101; H01L 29/66795 20130101; H01L 29/785
20130101; H01L 29/66545 20130101; H01L 29/4991 20130101; H01L
29/4232 20130101; H01L 29/7851 20130101; H01L 21/02362
20130101 |
International
Class: |
H01L 29/78 20060101
H01L029/78; H01L 29/423 20060101 H01L029/423; H01L 29/66 20060101
H01L029/66; H01L 21/02 20060101 H01L021/02 |
Claims
1. A method, comprising: forming a placeholder gate structure above
a semiconductor material region; forming a sidewall spacer adjacent
the placeholder gate structure; removing the placeholder gate
structure to define a gate cavity bounded by the sidewall spacer;
forming a gate insulation layer in the gate cavity, wherein the
gate insulation layer comprises a first vertical portion positioned
in a lower portion of the gate cavity having a first thickness in a
horizontal direction and a second vertical portion positioned in an
upper portion of the gate cavity having a second thickness in the
horizontal direction greater than the first thickness; forming a
gate electrode in the gate cavity above the gate insulation layer;
removing at least a portion of the second vertical portion of the
gate insulation layer to define an air gap cavity adjacent the gate
electrode; and forming a first gate cap layer above the gate
electrode, wherein the first gate cap layer seals an upper end of
the air gap cavity.
2. The method of claim 1, wherein forming the gate insulation layer
comprises: forming an inner spacer on the upper portion of the gate
cavity; and forming a first insulating layer above the inner spacer
and in the lower portion of the gate cavity, wherein the inner
spacer and the first insulating layer define the gate insulation
layer.
3. The method of claim 2, wherein forming the inner spacer
comprises: forming a mask layer in the lower portion of the gate
cavity; forming a second insulating layer above the mask layer;
etching the second insulating layer to define the inner spacer; and
removing the mask layer.
4. The method of claim 2, wherein the inner spacer and the first
layer of insulating material comprise a same material.
5. The method of claim 4, wherein the inner spacer and the first
layer of insulating material comprise a high-k dielectric
material.
6. The method of claim 2, wherein removing at least a portion of
the second vertical portion of the gate insulation layer comprises
removing the inner spacer and portions of the first insulating
layer adjacent the inner spacer.
7. The method of claim 1, wherein removing at least a portion of
the second vertical portion of the gate insulation layer comprises
removing an entirety of the second vertical portion.
8. The method of claim 1, further comprising recessing the sidewall
spacer prior to removing at least a portion of the second vertical
portion of the gate insulation layer.
9. The method of claim 1, wherein forming the gate electrode in the
gate cavity comprises: forming the gate electrode to fill the gate
cavity; and recessing the gate electrode prior to removing at least
a portion of the second vertical portion of the gate insulation
layer.
10. The method of claim 1, wherein a second gate cap layer is
positioned above the placeholder gate structure, and the method
further comprises: forming a dielectric layer above the placeholder
gate structure; and planarizing the dielectric layer, the sidewall
spacer and the second gate cap layer to expose the placeholder gate
structure.
11. A method, comprising: forming a placeholder gate structure
above a semiconductor material region; forming a sidewall spacer
adjacent the placeholder gate structure; removing the placeholder
gate structure to define a gate cavity bounded by the sidewall
spacer; forming a mask layer in a lower portion of the gate cavity;
forming a first gate insulation layer in the gate cavity and above
the mask layer; etching the first gate insulation layer to define
an inner spacer; removing the mask layer; forming a second gate
insulation layer in the gate cavity and above the inner spacer;
forming a gate electrode in the gate cavity above the second gate
insulation layer; removing at least portions of the inner spacer
and the second gate insulation layer in an upper portion of the
gate cavity to define an air gap cavity adjacent the gate
electrode; and forming a first gate cap layer above the gate
electrode, wherein the first gate cap layer seals an upper end of
the air gap cavity.
12. The method of claim 11, wherein the first and second gate
insulation layers comprise a same material.
13. The method of claim 12, wherein the first and second gate
insulation layers comprise a high-k dielectric material.
14. The method of claim 11, wherein removing at least portions of
the inner spacer and the second gate insulation layer comprises
removing overlapping portions of the inner spacer and the second
gate insulation layer.
15. The method of claim 11, further comprising recessing the
sidewall spacer prior to removing portions of the inner spacer and
the second gate insulation layer.
16. The method of claim 11, wherein forming the gate electrode in
the gate cavity comprises: forming the gate electrode to fill the
gate cavity; and recessing the gate electrode prior to removing
portions of the inner spacer and the second gate insulation
layer.
17. The method of claim 11, wherein a second gate cap layer is
positioned above the placeholder gate structure, and the method
further comprises: forming a dielectric layer above the placeholder
gate structure; and planarizing the dielectric layer, the sidewall
spacer and the second gate cap layer to expose the placeholder gate
structure.
18.-20. (canceled)
21. A method, comprising: forming a placeholder gate structure
above a semiconductor material region; forming a sidewall spacer
adjacent the placeholder gate structure; removing the placeholder
gate structure to define a gate cavity bounded by the sidewall
spacer; forming a gate insulation layer in the gate cavity, wherein
the gate insulation layer comprises a first portion positioned in a
lower portion of the gate cavity having a first thickness and a
second portion positioned in an upper portion of the gate cavity
having a second thickness greater than the first thickness; forming
a gate electrode in the gate cavity above the gate insulation
layer; recessing the sidewall spacer; removing a portion of the
second portion of the gate insulation layer after recessing the
sidewall spacer to define an air gap cavity adjacent the gate
electrode; and forming a first gate cap layer above the gate
electrode, wherein the first gate cap layer seals an upper end of
the air gap cavity.
22. The method of claim 21, wherein forming the gate electrode in
the gate cavity comprises: forming the gate electrode to fill the
gate cavity; and recessing the gate electrode prior to removing at
least a portion of the second portion of the gate insulation
layer.
23. The method of claim 21, wherein a second gate cap layer is
positioned above the placeholder gate structure, and the method
further comprises: forming a dielectric layer above the placeholder
gate structure; and planarizing the dielectric layer, the sidewall
spacer and the second gate cap layer to expose the placeholder gate
structure.
Description
BACKGROUND
1. FIELD OF THE INVENTION
[0001] The present disclosure generally relates to the fabrication
of semiconductor devices, and, more particularly, to methods for
forming an air gap in a replacement gate.
2. DESCRIPTION OF THE RELATED ART
[0002] In modern integrated circuits, such as microprocessors,
storage devices and the like, a very large number of circuit
elements, especially transistors, are provided on a restricted chip
area. Transistors come in a variety of shapes and forms, e.g.,
planar transistors, FinFET transistors, nanowire devices, etc. The
transistors are typically either NMOS (NFET) or PMOS (PFET) type
devices wherein the "N" and "P" designation is based upon the type
of dopants used to create the source/drain regions of the devices.
So-called CMOS (Complementary Metal Oxide Semiconductor) technology
or products refers to integrated circuit products that are
manufactured using both NMOS and PMOS transistor devices.
Irrespective of the physical configuration of the transistor
device, each device comprises drain and source regions and a gate
electrode structure positioned above and between the source/drain
regions. Upon application of an appropriate control voltage to the
gate electrode, a conductive channel region forms between the drain
region and the source region.
[0003] In some applications, fins for FinFET devices are formed
such that the fin is vertically spaced apart from and above the
substrate with an isolation material positioned between the fin and
the substrate. FIG. 1 is a perspective view of an illustrative
prior art FinFET semiconductor device 100 that is formed above a
semiconductor substrate 105 at an intermediate point during
fabrication. In this example, the FinFET device 100 includes three
illustrative fins 110, an isolation material 130, a gate structure
115, sidewall spacers 120 and a gate cap layer 125. The fins 110
have a three-dimensional configuration: a height, a width, and an
axial length. The portions of the fins 110 covered by the gate
structure 115 are the channel regions of the FinFET device 100,
while the portions of the fins 110 positioned laterally outside of
the spacers 120 are part of the source/drain regions of the device
100. Although not depicted, the portions of the fins 110 in the
source/drain regions may have additional epi semiconductor material
formed thereon in either a merged or unmerged condition.
[0004] In an integrated circuit device, there are different
performance requirements for different functional blocks or regions
of the device. One technique for improving performance in a
transistor device involves reducing the capacitance of the gate
structure. Low dielectric constant materials have been employed for
gate spacers to reduce the capacitance. To further reduce
capacitance, air gaps have been employed in conjunction with the
gate spacers. However, such techniques often require multiple
process operations, which increases process complexity and can
reduce yield.
[0005] The present disclosure is directed to various methods and
resulting devices that may avoid, or at least reduce, the effects
of one or more of the problems identified above.
SUMMARY
[0006] The following presents a simplified summary of the invention
in order to provide a basic understanding of some aspects of the
invention. This summary is not an exhaustive overview of the
invention. It is not intended to identify key or critical elements
of the invention or to delineate the scope of the invention. Its
sole purpose is to present some concepts in a simplified form as a
prelude to the more detailed description that is discussed
later.
[0007] Generally, the present disclosure is directed to various
methods of forming transistor devices with an air gap in the
replacement gate structure. One illustrative method includes, among
other things, forming a placeholder gate structure above a
semiconductor material region, forming a sidewall spacer adjacent
the placeholder gate structure, removing the placeholder gate
structure to define a gate cavity bounded by the sidewall spacer,
forming a gate insulation layer in the gate cavity, wherein the
gate insulation layer includes a first portion positioned in a
lower portion of the gate cavity having a first thickness and a
second portion positioned in an upper portion of the gate cavity
having a second thickness greater than the first thickness, forming
a gate electrode in the gate cavity above the gate insulation
layer, removing at least a portion of the second portion of the
gate insulation layer to define an air gap cavity adjacent the gate
electrode, and forming a first gate cap layer above the gate
electrode, wherein the first gate cap layer seals an upper end of
the air gap cavity.
[0008] Another illustrative method includes, among other things,
forming a placeholder gate structure above a semiconductor material
region, forming a sidewall spacer adjacent the placeholder gate
structure, removing the placeholder gate structure to define a gate
cavity bounded by the sidewall spacer, forming a mask layer in a
lower portion of the gate cavity, forming a first gate insulation
layer in the gate cavity and above the mask layer, etching the
first gate insulation layer to define an inner spacer, removing the
mask layer, forming a second gate insulation layer in the gate
cavity and above the inner spacer, forming a gate electrode in the
gate cavity above the second gate insulation layer, removing at
least portions of the inner spacer and the second gate insulation
layer in an upper portion of the gate cavity to define an air gap
cavity adjacent the gate electrode, and forming a first gate cap
layer above the gate electrode, wherein the first gate cap layer
seals an upper end of the air gap cavity.
[0009] One illustrative device includes, among other things, a gate
electrode formed above a semiconductor material region, a sidewall
spacer positioned adjacent the gate electrode, wherein an air gap
is defined between an upper portion of the sidewall spacer and the
gate electrode, a gate insulation layer having a first portion
positioned between the gate electrode and the semiconductor
material region and a second portion positioned between a lower
portion of the sidewall spacer and the gate electrode along a
portion of a sidewall of the gate electrode, and a gate cap layer
positioned above the gate electrode, wherein the first gate cap
layer seals an upper end of the air gap cavity.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The disclosure may be understood by reference to the
following description taken in conjunction with the accompanying
drawings, in which like reference numerals identify like elements,
and in which:
[0011] FIG. 1 schematically depicts an illustrative prior art
finFET device; and
[0012] FIGS. 2A-2I and 3A-3C depict various methods disclosed
herein of forming transistor devices with an air gap in a
replacement gate structure.
[0013] While the subject matter disclosed herein is susceptible to
various modifications and alternative forms, specific embodiments
thereof have been shown by way of example in the drawings and are
herein described in detail. It should be understood, however, that
the description herein of specific embodiments is not intended to
limit the invention to the particular forms disclosed, but on the
contrary, the intention is to cover all modifications, equivalents,
and alternatives falling within the spirit and scope of the
invention as defined by the appended claims.
DETAILED DESCRIPTION
[0014] Various illustrative embodiments of the invention are
described below. In the interest of clarity, not all features of an
actual implementation are described in this specification. It will
of course be appreciated that in the development of any such actual
embodiment, numerous implementation-specific decisions must be made
to achieve the developers' specific goals, such as compliance with
system-related and business-related constraints, which will vary
from one implementation to another. Moreover, it will be
appreciated that such a development effort might be complex and
time-consuming, but would nevertheless be a routine undertaking for
those of ordinary skill in the art having the benefit of this
disclosure.
[0015] The present subject matter will now be described with
reference to the attached figures. Various structures, systems and
devices are schematically depicted in the drawings for purposes of
explanation only and so as to not obscure the present disclosure
with details that are well known to those skilled in the art.
Nevertheless, the attached drawings are included to describe and
explain illustrative examples of the present disclosure. The words
and phrases used herein should be understood and interpreted to
have a meaning consistent with the understanding of those words and
phrases by those skilled in the relevant art. No special definition
of a term or phrase, i.e., a definition that is different from the
ordinary and customary meaning as understood by those skilled in
the art, is intended to be implied by consistent usage of the term
or phrase herein. To the extent that a term or phrase is intended
to have a special meaning, i.e., a meaning other than that
understood by skilled artisans, such a special definition will be
expressly set forth in the specification in a definitional manner
that directly and unequivocally provides the special definition for
the term or phrase.
[0016] The present disclosure generally relates to various methods
of forming transistor devices with an air gap in the replacement
gate structure. As will be readily apparent to those skilled in the
art upon a complete reading of the present application, the present
method is applicable to a variety of devices, including, but not
limited to, logic devices, memory devices, etc. With reference to
the attached figures, various illustrative embodiments of the
methods and devices disclosed herein will now be described in more
detail.
[0017] FIGS. 2A-2I and 3A-3C illustrate various illustrative
methods disclosed herein for forming an integrated circuit product
200 with a replacement gate air gap. In the illustrated embodiment,
the product includes finFET transistor devices, but the techniques
described herein are not so limited, and they may be applied to
other types of devices, such as planar devices. FIGS. 2A-2I and
3A-3C show a cross-sectional view of the product 200 taken through
the long axis of one of a fin 205 formed in a substrate 210. The
cross-sectional view is taken in a direction corresponding to the
gate length direction of the product 200.
[0018] In the illustrated embodiment, a replacement gate technique
is used to form devices in the product 200. A placeholder gate
structure 220 was formed above the fin 205. The placeholder gate
structure 220 includes a sacrificial placeholder material 225, such
as amorphous polysilicon, and a gate insulation layer (not
separately shown), such as silicon dioxide. Also depicted are an
illustrative gate cap layer 230 and a sidewall spacer 235, both of
which may be made of a dielectric material such as silicon nitride.
Source/drain regions 240 were formed adjacent the placeholder gate
structure 220 by recessing the fin 205 and performing an epitaxial
growth process. A dielectric layer 245 (e.g., silicon dioxide, a
low-k dielectric material having a dielectric constant of
approximately 3.0 or lower, or an ultra-low-k (ULK) material having
a dielectric constant of approximately 2.5 or lower) was formed
above the placeholder gate structure 220 and the source/drain
regions 240.
[0019] The transistor devices formed in the product 200 depicted
herein may be either NMOS or PMOS transistors, or a combination of
both. Additionally, various doped regions, e.g., halo implant
regions, well regions and the like, may be formed, but are not
depicted in the attached drawings. The substrate 210 may have a
variety of configurations, such as the depicted bulk silicon
configuration. The substrate 210 may also have a
silicon-on-insulator (SOI) configuration that includes a bulk
silicon layer, a buried insulation layer and an active layer,
wherein semiconductor devices are formed in and above the active
layer. The substrate 210 may be formed of silicon or silicon
germanium or it may be made of materials other than silicon, such
as germanium. Thus, the terms "substrate" or "semiconductor
substrate" should be understood to cover all semiconducting
materials and all forms of such materials. The substrate 210 may
have different layers. For example, the fin 205 may be formed in a
process layer formed above the base layer of the substrate 210.
[0020] FIG. 2B illustrates the product 200 after the dielectric
layer 245 was planarized to remove the gate cap layer 230, reduce
the height of the sidewall spacer 235, and expose a top surface of
the sacrificial placeholder material 225.
[0021] FIG. 2C illustrates the product 200 after a plurality of
etch processes were performed to remove the sacrificial placeholder
material 225 and any underlying gate dielectric layer (not
visible), thereby defining a gate cavity 250.
[0022] FIG. 2D illustrates the product 200 after several deposition
processes were performed to form a mask layer 255 (e.g., organic
patterning layer (OPL)) in the lower portion of the gate cavity 250
and to form a first gate insulation layer 260 (e.g., high-k
material, such as hafnium dioxide).
[0023] FIG. 2E illustrates the product 200 after an anisotropic
etch process was performed to define an inner spacer 260S from the
first gate insulation layer 260. An ashing process was performed to
strip the mask layer 255.
[0024] FIG. 2F illustrates the product 200 after several processes
were performed. A deposition process was performed to form a second
gate insulation layer 265 in the gate cavity 250. One or more
deposition processes were performed to form a gate electrode 270 in
the gate cavity. The gate electrode 270 may have multiple layers,
such as a barrier layer, one or more work function material layers,
and a metal fill layer (e.g., tungsten, aluminum, etc.). A
planarization process was performed to remove excess portions of
the gate electrode 270 and the second gate insulation layer 265
positioned above the upper surface of the dielectric layer 245. The
first and second gate insulation layers 260, 265 may be the same
material, so the combination of the inner spacer 260S and the
second gate insulation layer 265 may be seen as a gate insulation
layer 275 with an increased thickness in an upper portion the gate
cavity 250.
[0025] FIG. 2G illustrates the product 200 after an etch process
was performed to recess the gate electrode 270.
[0026] FIG. 2H illustrates the product 200 after an etch process
was performed to recess the inner spacer 260S and the second gate
insulation layer 265 to define an air gap cavity 280 adjacent the
gate electrode 270. The recessing may extend to the entire depth of
the inner spacer 260S (i.e., the portion of the gate insulation
layer 275 having the increased thickness).
[0027] FIG. 2I illustrates the product 200 after a deposition
process was performed to form a gate cap layer 285 in the gate
cavity 250 above the gate electrode 270. A planarization process
was performed to remove excess portions of the gate cap layer 285
extending above the dielectric layer 245. During the deposition
process, the gate cap layer 285 pinches off the upper portion of
the air gap cavity 280. The provision of the air gap cavity 280
adjacent the gate electrode 270 reduces the effective capacitance
of the product 200, thereby improving performance.
[0028] FIGS. 3A-3C illustrate an alternative process flow for
forming the product 200'. FIG. 3A illustrates the product 200'
starting with the device 200 shown in FIG. 2G after an etch process
was performed to recess the sidewall spacer 235, the inner spacer
260S, and the gate insulation layer 265.
[0029] FIG. 3B illustrates the product 200' after an etch process
was performed to recess the inner spacer 260S and the second gate
insulation layer 265 to define the air gap cavity 280 adjacent the
gate electrode 270. The recessing may extend to the entire depth of
the inner spacer 260S (i.e., the portion of the gate insulation
layer 275 having the increased thickness).
[0030] FIG. 3C illustrates the product 200' after a deposition
process was performed to form the gate cap layer 285 in the gate
cavity 250 above the gate electrode 270. A planarization process
was performed to remove excess portions of the gate cap layer 285
extending above the dielectric layer 245. During the deposition
process, the gate cap layer 285 pinches off the upper portion of
the air gap cavity 280.
[0031] The particular embodiments disclosed above are illustrative
only, as the invention may be modified and practiced in different
but equivalent manners apparent to those skilled in the art having
the benefit of the teachings herein. For example, the process steps
set forth above may be performed in a different order. Furthermore,
no limitations are intended to the details of construction or
design herein shown, other than as described in the claims below.
It is therefore evident that the particular embodiments disclosed
above may be altered or modified and all such variations are
considered within the scope and spirit of the invention. Note that
the use of terms, such as "first," "second," "third" or "fourth" to
describe various processes or structures in this specification and
in the attached claims is only used as a shorthand reference to
such steps/structures and does not necessarily imply that such
steps/structures are performed/formed in that ordered sequence. Of
course, depending upon the exact claim language, an ordered
sequence of such processes may or may not be required. Accordingly,
the protection sought herein is as set forth in the claims
below.
* * * * *