U.S. patent application number 16/390953 was filed with the patent office on 2019-08-15 for trace design for bump-on-trace (bot) assembly.
The applicant listed for this patent is Taiwan Semiconductor Manufacturing Company, Ltd.. Invention is credited to Chen-Shien Chen, Tin-Hao Kuo, Yen-Liang Lin.
Application Number | 20190252347 16/390953 |
Document ID | / |
Family ID | 53372197 |
Filed Date | 2019-08-15 |
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United States Patent
Application |
20190252347 |
Kind Code |
A1 |
Lin; Yen-Liang ; et
al. |
August 15, 2019 |
Trace Design for Bump-on-Trace (BOT) Assembly
Abstract
A bump-on-trace (BOT) interconnection in a package and methods
of making the BOT interconnection are provided. An embodiment BOT
interconnection comprises a landing trace including a distal end, a
conductive pillar extending at least to the distal end of the
landing trace; and a solder feature electrically coupling the
landing trace and the conductive pillar. In an embodiment, the
conductive pillar overhangs the end surface of the landing trace.
In another embodiment, the landing trace includes one or more
recesses for trapping the solder feature after reflow. Therefore, a
wetting area available to the solder feature is increased while
permitting the bump pitch of the package to remain small.
Inventors: |
Lin; Yen-Liang; (Taichung,
TW) ; Chen; Chen-Shien; (Zhubei, TW) ; Kuo;
Tin-Hao; (Hsinchu, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Taiwan Semiconductor Manufacturing Company, Ltd. |
Hsinchu |
|
TW |
|
|
Family ID: |
53372197 |
Appl. No.: |
16/390953 |
Filed: |
April 22, 2019 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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15456134 |
Mar 10, 2017 |
10269759 |
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16390953 |
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14143648 |
Dec 30, 2013 |
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15456134 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 2224/10175
20130101; H01L 2224/13023 20130101; H01L 2224/05552 20130101; H05K
2203/1173 20130101; H01L 2224/81385 20130101; H01L 2224/16113
20130101; H01L 24/13 20130101; H01L 2224/133 20130101; H01L
23/49811 20130101; H01L 2924/381 20130101; H01L 2224/0807 20130101;
H01L 2224/08053 20130101; H01L 2924/12042 20130101; H01L 2224/131
20130101; Y02P 70/613 20151101; H05K 3/3436 20130101; H01L
2224/16238 20130101; H01L 2224/13147 20130101; H01L 2224/13294
20130101; H01L 2224/16105 20130101; H01L 2224/13013 20130101; H01L
2224/13014 20130101; H01L 2224/81815 20130101; H01L 2224/16013
20130101; H01L 2224/81447 20130101; H01L 2924/3841 20130101; H01L
24/81 20130101; H01L 2224/05551 20130101; H01L 2224/8112 20130101;
Y02P 70/50 20151101; H01L 24/05 20130101; H01L 2224/16012 20130101;
H01L 2924/14 20130101; H05K 2201/10674 20130101; H01L 2224/05011
20130101; H01L 24/11 20130101; H01L 2224/16227 20130101; H01L
2224/05012 20130101; H01L 24/16 20130101; H01L 2224/0401 20130101;
H01L 2924/12042 20130101; H01L 2924/00 20130101; H01L 2224/81447
20130101; H01L 2924/00014 20130101; H01L 2224/13147 20130101; H01L
2924/00014 20130101; H01L 2224/131 20130101; H01L 2924/014
20130101; H01L 2224/81815 20130101; H01L 2924/00014 20130101; H01L
2224/13294 20130101; H01L 2924/00014 20130101; H01L 2224/133
20130101; H01L 2924/014 20130101; H01L 2224/8112 20130101; H01L
2924/00014 20130101 |
International
Class: |
H01L 23/00 20060101
H01L023/00; H01L 23/498 20060101 H01L023/498; H05K 3/34 20060101
H05K003/34 |
Claims
1. A structure comprising: a substrate; and a landing trace on the
substrate, the landing trace having a first side and a second side
opposite to the first side, the landing trace having a plurality of
indents extending into the first side in a plan view, the second
side being free of indents in the plan view.
2. The structure of claim 1, further comprising a solder feature
over the landing trace, the solder feature extending into the
plurality of indents.
3. The structure of claim 2, wherein solder feature is in physical
contact with the plurality of indents.
4. The structure of claim 2, further comprising a conductive pillar
over the solder feature, the conductive pillar overlapping with the
plurality of indents in the plan view.
5. The structure of claim 4, wherein a width of the solder feature
is greater than a width of the conductive pillar.
6. The structure of claim 4, wherein a width of the landing trace
is less than a width of the conductive pillar.
7. The structure of claim 1, wherein the plurality of indents have
a comb pattern in the plan view.
8. A structure comprising: a substrate; and a landing trace on the
substrate, the landing trace having a first sidewall and a second
sidewall opposite to the first sidewall, the first sidewall having
a plurality of indents in a plan view, an entirety of the second
sidewall being a planar sidewall.
9. The structure of claim 8, further comprising a solder feature
over the landing trace, the solder feature filling the plurality of
indents.
10. The structure of claim 9, wherein a width of the solder feature
is greater than a width of the landing trace.
11. The structure of claim 9, wherein the solder feature is in
physical contact with the second sidewall of the landing trace.
12. The structure of claim 9, further comprising a conductive
pillar over the solder feature, the conductive pillar overlapping
with the plurality of indents in the plan view.
13. The structure of claim 12, wherein a width of the solder
feature is greater than a width of the conductive pillar.
14. The structure of claim 8, wherein the plurality of indents have
a comb pattern in the plan view.
15. A structure comprising: a substrate; and a landing trace on the
substrate, the landing trace comprising: a first portion; a second
portion; and a third portion connecting the first portion to the
second portion in a plan view, a first sidewall of the first
portion being collinear with a first sidewall of the second portion
in the plan view, a second sidewall of the first portion being
collinear with a second sidewall of the second portion and a second
sidewall of the third portion in the plan view, the first sidewall
of the third portion having a plurality of indents in the plan
view, an entirety of the second sidewall of the third portion being
a planar sidewall.
16. The structure of claim 15, wherein the plurality of indents
have a comb pattern in the plan view.
17. The structure of claim 15, further comprising a solder feature
over the third portion of the landing trace, the solder feature
overlapping with the plurality of indents in the plan view.
18. The structure of claim 17, wherein the solder feature is in
physical contact with the plurality of indents.
19. The structure of claim 17, further comprising a conductive
pillar over the solder feature, the conductive pillar overlapping
with the plurality of indents in the plan view.
20. The structure of claim 19, wherein the conductive pillar is in
physical contact with the solder feature.
Description
[0001] This application is a continuation U.S. patent application
Ser. No. 15/456,134, filed on Mar. 10, 2017, entitled "Trace Design
for Bump-on-Trace (BOT) Assembly," which is a continuation of U.S.
patent application Ser. No. 14/143,648, filed Dec. 30, 2013,
entitled "Trace Design for Bump-on-Trace (BOT) Assembly," which
application is incorporated herein by reference in its
entirety.
BACKGROUND
[0002] In a package such as a flip chip Chip Scale Package (fcCSP),
an integrated circuit (IC) or die is mounted to a substrate (e.g.,
a printed circuit board (PCB) or other integrated circuit carrier)
through a bump on trace (BOT) interconnection. The BOT
interconnection employs solder to electrically couple the bump of
the IC to the trace of the substrate.
[0003] In light of the demand for ever smaller packages, attempts
are often made to reduce the distance between adjacent bumps, which
is known as the bump pitch. One way to reduce the bump pitch is by
reducing the distance between neighboring metal traces.
[0004] Unfortunately, reducing the distance between neighboring
metal traces may lead to undesirable or detrimental consequences.
For example, if the neighboring metal traces are too close to each
other, a solder bridge may form during reflow when the BOT
interconnection is established.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] For a more complete understanding of the present disclosure,
and the advantages thereof, reference is now made to the following
descriptions taken in conjunction with the accompanying drawings,
in which:
[0006] FIG. 1 illustrates a top view of an embodiment bump-on-trace
(BOT) assembly in a package (with the die removed) for ease of
illustration;
[0007] FIG. 2 illustrates a cross section of the embodiment BOT
assembly of FIG. 1 taken generally along line 2-2;
[0008] FIG. 3 illustrates a cross section of the embodiment BOT
assembly of FIG. 1 taken generally along line 3-3;
[0009] FIGS. 4-6 collectively illustrate an embodiment process flow
used to fabricate the embodiment BOT assembly of FIGS. 1-3;
[0010] FIGS. 7-8 illustrate recesses that may be formed in the
landing trace of the embodiment BOT assembly of FIG. 1;
[0011] FIG. 9 illustrates dimensions of the conductive pillar
relative to the portion of the landing trace beneath the conductive
pillar;
[0012] FIGS. 10-11 provide a set of images depicting the increased
distance between the solder feature and the neighboring trace in a
BOT interconnection and the embodiment BOT assembly of FIG. 1;
and
[0013] FIGS. 12-13 illustrate embodiment methods of forming the BOT
assembly of FIG. 1.
[0014] Corresponding numerals and symbols in the different figures
generally refer to corresponding parts unless otherwise indicated.
The figures are drawn to clearly illustrate the relevant aspects of
the embodiments and are not necessarily drawn to scale.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
[0015] The making and using of the present embodiments are
discussed in detail below. It should be appreciated, however, that
the disclosure provides many applicable inventive concepts that can
be embodied in a wide variety of specific contexts. The specific
embodiments discussed are merely illustrative and do not limit the
scope of the disclosure.
[0016] The present disclosure will be described with respect to
embodiments in a specific context, namely a package incorporating a
bump-on-trace (BOT) interconnection. The concepts in the disclosure
may also apply, however, to other packages, interconnection
assemblies, or semiconductor structures.
[0017] Referring collectively to FIGS. 1-3, a bump-on-trace (BOT)
assembly 10 for a package 12 is illustrated. As will be more fully
explained below, the BOT assembly 10 offers numerous benefits and
advantages over BOT assemblies formed using other approaches. For
example, the BOT assembly 10 allows solder to more uniformly
disperse over the landing trace. By doing so, undesirable solder
bridging between adjacent traces in a fine pitch bump design is
inhibited or prevented. In addition, the BOT assembly 10 provides a
more robust and reliable electrical interconnection for the package
12.
[0018] As shown, the BOT assembly 10 is employed to electrically
(and, in some embodiments, structurally) couple a die 14 (in FIGS.
2 and 3) to a substrate 16. In an embodiment, the die 14 includes
one or more of a variety of different integrated circuits
singulated from a wafer. In an embodiment, the substrate 16 may be,
for example, a printed circuit board. In some embodiments, the die
14 and the substrate 16 may each include additional components,
layers, structures, or features that have been omitted for ease of
illustration.
[0019] As shown in FIG. 1, the BOT assembly 10 includes a landing
trace 18, a conductive pillar 20, and a solder feature 22. The
landing trace 18 is adjacent to at least one neighboring trace 30
on the substrate 16. As will be explained below, the landing trace
18 has a reduced length or may be truncated relative to the
adjacent neighboring trace 30. In other words, the landing trace 18
may be shorter than the neighboring trace 30.
[0020] As shown in FIGS. 2-3, the landing trace 18 is supported by
the substrate 16. In an embodiment, the landing trace 18 is
entirely disposed above a top surface of the substrate 16. In an
embodiment, the landing trace 18 is at least partially embedded
into the substrate 16. The landing trace 18 is formed from a
conductive metal such as, for example, copper (Cu), but may be
suitably formed from other conductive metals.
[0021] Referring back to FIG. 1, the landing trace 18 of the BOT
assembly 10 includes an end 24 of the landing trace 18. The end 24
may also be referred to a distal end. The end 24 provides an end
surface 26 situated between opposing sidewalls 28. In embodiments
where the landing trace 18 is shorter than the neighboring trace
30, the distal end 24 of the landing trace 18 is offset from a
distal end 24 of the neighboring trace 30. In other words, the
landing trace 18 and the neighboring trace 30 are misaligned
relative to one another as positioned on the substrate 16.
[0022] As shown in FIGS. 2-3, the conductive pillar 20 is coupled
to the die 14. The conductive pillar 20 is formed from a conductive
metal such as, for example, copper (Cu), but may be suitably formed
from other conductive metals. The conductive pillar 20 may be
referred to as a bump or an under bump metallization (UBM).
[0023] As shown in FIGS. 1-2, the conductive pillar 20 extends to
at least the distal end 24 of the landing trace 18 and may extend
beyond the distal end 24 in some embodiments. In other words, a
periphery 32 of the conductive pillar 20 at least reaches to the
end surface 26 of the underlying landing trace 18 as shown in FIG.
1. In an embodiment, the conductive pillar 20 overhangs the
underlying landing trace 18 such that the periphery 32 of the
conductive pillar 20 projects beyond the end surface 26 of the
underlying landing trace 18. In an embodiment, the conductive
pillar 20 has a width 34 that is greater than a width 36 of the
underlying landing trace 18.
[0024] In an embodiment, the landing trace 18 and the conductive
pillar 20 may take a variety of suitable shapes. In other words,
the landing trace 18 and the conductive pillar 20 are not limited
to the shape illustrated in FIGS. 1-3. For example, instead of
being rectangular, the landing trace 18 may be square, round, oval,
and so on. In addition, instead of being oval, the conductive
pillar 20 may be may be rectangular, square, round, and so on.
[0025] As shown in FIGS. 1-3, the solder feature 22 (e.g., solder
joint) is disposed between and around the conductive pillar 20 and
the landing trace 18. As such, the solder feature 22 is able to
electrically couple the conductive pillar 20 extending from the die
14 with the landing trace 18 disposed on the substrate 16.
[0026] In an embodiment, the solder feature 22 engages and abuts
both of the sidewalls 28 of the landing trace 18. In an embodiment,
the solder feature 22 also engages and abuts the end surface 26 of
the landing trace 18. The solder feature 22 may be a solder paste,
a solder ball, or another suitable fusible metal alloy used to join
components and having a melting point below that of the
components.
[0027] Because the conductive pillar 20 extends at least to, and
may overhang, the distal end 24 of the landing trace 18 as shown in
FIGS. 1-2, the solder feature 22 is allowed to uniformly disperse
on both sidewalls 28 of the landing trace 18. With the solder
feature 22 disposed along both of the sidewalls 28, the volume of
solder on either side of the landing trace 18 is reduced compared
to when the solder only wets on one of the two sidewalls 28. In
other words, the volume of solder is divided between the two
sidewalls 28 instead of accumulating along just one of the
sidewalls 28.
[0028] Because the volume of solder is shared between the two
sidewalls 28 of the landing trace 18, the distance between the
solder feature 22 and the neighboring trace 30 is decreased
relative to when most or all of the solder feature 22 collects
along only the sidewall 28 of the landing trace 18 facing the
neighboring trace 30. Therefore, the pitch between the landing
trace 18 and the neighboring trace 30 can be reduced to, for
example, provide for a smaller overall package 10.
[0029] In an embodiment, the volume of solder is shared between the
two sidewalls 28 and the end surface 26 of the landing trace 18. In
such an embodiment, the distance between the solder feature 22 and
the neighboring trace 30 may be even further decreased relative to
when the solder feature 22 collects along only the sidewall 28 of
the landing trace 18 facing the neighboring trace 30.
[0030] In an embodiment, the landing trace 18 may be made smaller
than the neighboring trace 30 from the outset. In such
circumstances, the portion 38 of the landing trace 18 depicted by
dashed lines in FIG. 4 will not have been created. In another
embodiment, the landing trace 18 and the neighboring landing trace
18 may have about the same length if there is sufficient room at
the distal end 24 of the landing trace 18 to permit the conductive
pillar to extend to, or overhang, the distal end 24. In other
words, if the distal end 24 of the landing trace 18 is spaced apart
from a periphery of the substrate 16 to allow for a solder
connection then the landing trace 18 and the neighboring landing
trace 18 may have about the same length.
[0031] Referring now to FIGS. 4-6, an embodiment process flow used
to fabricate the BOT assembly 10 of FIGS. 1-3 is schematically
illustrated. As shown in FIG. 4, the landing trace 18 and the
neighboring trace 30 are formed on the substrate 16. In an
embodiment, a portion 38 (represented by dashed lines) of the
landing trace 18 is omitted during the formation process such that
the landing trace 18 is shorter in length than the neighboring
trace 30.
[0032] In an embodiment, the landing trace 18 and the neighboring
trace 30 may be initially formed with the same length and,
thereafter, the portion 38 may be removed to provide the landing
trace 18 with a shorter length. The portion 38 of the landing trace
18 may be removed by, for example, etching. The portion 38 of the
landing trace may also be suitably removed by a laser cut, laser
burn, selective etching process, a mechanical cut, etc.
[0033] Referring now to FIG. 5, when the landing trace 18 is made
shorter than the neighboring trace 30 or when the portion 38 of the
landing trace 18 has been removed, an augmented wetting area 40
(shown in dashed lines in FIG. 5) is generated or produced. In an
embodiment, the augmented wetting area 40 includes the end surface
26 of the landing trace 18. In an embodiment, the augmented wetting
area 40 includes the end surface 26 and at least a portion of both
of the sidewalls 28 of the landing trace 18. The augmented wetting
area 40 provides more area or additional surfaces for the solder
feature 22 to disperse over and around.
[0034] Referring now to FIG. 5, the conductive pillar 20 is
positioned over the landing trace 18. In an embodiment, the
conductive pillar 20 extends at least to the distal end 24 of the
landing trace 18. In an embodiment, the conductive pillar 20
overhangs the distal end 24 of the landing trace 18. In other
words, the periphery 32 of the conductive pillar 20 projects beyond
the end surface 26 of the underlying landing trace 18 as shown in
FIG. 5.
[0035] Referring now to FIG. 6, after the conductive pillar 20 has
been positioned, the solder feature 22 initially disposed between
the landing trace 18 and the conductive pillar 20 is reflowed. When
the solder feature 22 cools, the landing trace 18 is electrically
coupled to the conductive pillar 20. In FIG. 6 the solder feature
22 extends along both sidewalls 28 and the end surface 26 of the
landing trace 18. Therefore, the extrusion of the solder feature 22
in the direction of the adjacent neighboring trace 30 is reduced
relative to the other BOT interconnections.
[0036] As shown in FIGS. 7-8, in an embodiment one or more recesses
42 may be formed in the landing trace 18 to generate or contribute
to the augmented wetting area 40 (shown in dashed lines) of the
landing trace 18. In other words, the recesses 42 may be formed in
the landing trace 18 instead of, or in addition to, removal of the
portion 38 of the landing trace 18 shown in FIG. 4. The recesses 42
in the landing trace 18 provide an area for the solder feature 22
to occupy upon reflow. As such, the extrusion of the solder feature
22 in the direction of the adjacent neighboring trace 30 is reduced
relative to the other BOT interconnections.
[0037] As shown in FIG. 7, the recesses 42 may be formed in a "fish
bone" pattern. As shown in FIG. 8, the recesses 42 may be formed in
a "comb" pattern. The recesses 42 may also be formed in a variety
of other suitable patterns. For example, the recesses 42 may be
formed in symmetrical or asymmetrical patterns, patterns that have
even or uneven spacing between recesses 42, and so on. In addition,
the recesses 42 may have a variety of suitable shapes. For example,
the recesses 42 may be square, rectangular, semi-circular, oval,
and so on.
[0038] Referring now to FIG. 9, the neighboring trace 30 is
depicted laterally adjacent to the landing trace 18. As shown, the
solder feature 22 and the conductive pillar 20 are illustrated over
the landing trace 18. The conductive pillar 20 has a diameter, R.
The landing trace 18 has a length, L, which represents the portion
of the landing trace 18 within the periphery 32 of the conductive
pillar 20.
[0039] In an embodiment, the length, L, of the landing trace 18
within the periphery 32 of the conductive pillar 20 is about 20% to
about 100% of the diameter, R, of the conductive pillar 20. The 20%
lower limit was selected because the total assembly process
variation is around 20% of the diameter, R, of the conductive
pillar 20. Therefore, in order to ensure that the conductive pillar
20 has a suitable joint on the landing trace 18, the length, L, of
the landing trace 18 is suggested to be 20% or more of the
diameter, R, of the conductive pillar 20. If not, an electric open
may be encountered after the assembly process because the
conductive pillar 20 does not contact on landing trace 18. In an
embodiment, the conductive pillar 20 is positioned such that the
length, L, of the landing trace 18 within the periphery 32 of the
conductive pillar 20 is less than 100% of the diameter, R, of the
conductive pillar 20. In other words, the equation 1/5
R.ltoreq.L.ltoreq.R is satisfied.
[0040] Referring now to FIGS. 10-11, a first image 44 and a second
image 46 illustrate the increased distance between the solder
feature and the neighboring trace when the process described herein
is utilized. Indeed, as shown in FIG. 10, a distance, D1, between
the solder feature and the neighboring trace in the BOT
interconnection 52 is less than a distance, D2, between the solder
feature and the neighboring trace using the embodiment BOT assembly
10. In other words, the distance, D2, in FIG. 11 far exceeds the
distance, D1, in FIG. 10 because the solder feature 22 is
encouraged to wet along both sidewalls in the BOT assembly 10 of
FIG. 11.
[0041] In FIG. 12, a method 60 of forming the BOT assembly 10 is
illustrated. In block 62, the landing trace 18 is formed on the
substrate 16. In block 64, the conductive pillar 20 is positioned
over the landing trace 18 such that the conductive pillar 20
extends at least to the end 24 of the landing trace 18. In block
66, the solder feature 22 between the landing trace 18 and the
conductive pillar 20 is reflowed to electrically couple the landing
trace 18 to the conductive pillar 20.
[0042] In FIG. 13, a method 70 of forming the BOT assembly 10 is
illustrated. In block 72, the landing trace 18 is formed on the
substrate 16. In block 74, a portion of the landing trace 18 is
removed to generate an augmented wetting area 40. In block 76,
solder is applied over the augmented wetting area 40 of the landing
trace 18 to electrically couple the landing trace to the conductive
pillar 20.
[0043] From the foregoing, those of ordinary skill in the art will
recognize that the BOT assembly 10 controls or minimizes solder
extrusion. Moreover, the BOT assembly 10 enables solder to more
uniformly disperse over the landing trace. Therefore, the potential
for the formation of a solder bridge is reduced in fine bump pitch
packages. In other words, undesirable solder bridging between
adjacent traces in a fine pitch bump (I/O) design is inhibited or
prevented. In addition, BOT assembly 10 provides a more robust and
reliable electrical interconnection for the package 12 by changing
existing trace pattern design without substantial additional
process cost.
[0044] An embodiment method of forming a bump-on-trace (BOT)
assembly includes forming a landing trace on a substrate,
positioning a conductive pillar over the landing trace such that
the conductive pillar extends at least to an end of the landing
trace, and reflowing a solder feature between the landing trace and
the conductive pillar to electrically couple the landing trace to
the conductive pillar.
[0045] An embodiment method of forming a bump-on-trace (BOT)
assembly includes forming a landing trace on a substrate, removing
a portion of the landing trace to generate an augmented wetting
area, and applying solder over the augmented wetting area of the
landing trace to electrically couple the landing trace to a
conductive pillar.
[0046] An embodiment bump-on-trace (BOT) interconnection for a
package includes a landing trace including a distal end, a
conductive pillar extending at least to the distal end of the
landing trace, and a solder feature electrically coupling the
landing trace and the conductive pillar.
[0047] An embodiment structure includes a substrate and a landing
trace on the substrate. The landing trace has a first side and a
second side opposite to the first side. The landing trace has a
plurality of indents extending into the first side in a plan view.
The second side is free of indents in the plan view.
[0048] An embodiment structure includes a substrate and a landing
trace on the substrate. The landing trace has a first sidewall and
a second sidewall opposite to the first sidewall. The first
sidewall has a plurality of indents in a plan view. An entirety of
the second sidewall is a planar sidewall.
[0049] An embodiment structure includes a substrate and a landing
trace on the substrate. The landing trace includes a first portion,
a second portion, and a third portion connecting the first portion
to the second portion in a plan view. A first sidewall of the first
portion is collinear with a first sidewall of the second portion in
the plan view. A second sidewall of the first portion is collinear
with a second sidewall of the second portion and a second sidewall
of the third portion in the plan view. The first sidewall of the
third portion has a plurality of indents in the plan view. An
entirety of the second sidewall of the third portion is a planar
sidewall.
[0050] While the disclosure provides illustrative embodiments, this
description is not intended to be construed in a limiting sense.
Various modifications and combinations of the illustrative
embodiments, as well as other embodiments, will be apparent to
persons of ordinary skill in the art upon reference to the
description. It is therefore intended that the appended claims
encompass any such modifications or embodiments.
* * * * *