U.S. patent application number 15/832742 was filed with the patent office on 2019-05-09 for integrated fan-out package and manufacturing method thereof.
This patent application is currently assigned to Taiwan Semiconductor Manufacturing Co., Ltd.. The applicant listed for this patent is Taiwan Semiconductor Manufacturing Co., Ltd.. Invention is credited to Meng-Tse Chen, Sheng-Hsiang Chiu, Ching-Hua Hsieh, Yao-Tong Lai, Chih-Wei Lin, Chung-Shi Liu.
Application Number | 20190139787 15/832742 |
Document ID | / |
Family ID | 66327564 |
Filed Date | 2019-05-09 |
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United States Patent
Application |
20190139787 |
Kind Code |
A1 |
Chen; Meng-Tse ; et
al. |
May 9, 2019 |
INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF
Abstract
An integrated fan-out (InFO) package includes at least one die,
a plurality of conductive structures, an encapsulant, an
enhancement layer, and a redistribution structure. The die has an
active surface and includes a plurality of conductive posts on the
active surface. The conductive structures surround the die. The
encapsulant partially encapsulates the die. The enhancement layer
is over the encapsulant. A top surface of the enhancement layer is
substantially coplanar with top surfaces of the conductive posts
and the conductive structures. A material of the enhancement layer
is different from a material of the encapsulant. A roughness of an
interface between the encapsulant and the enhancement layer is
larger than a roughness of the top surface of the enhancement
layer. The redistribution structure is over the enhancement layer
and is electrically connected to the conductive structures and the
die.
Inventors: |
Chen; Meng-Tse; (Pingtung
County, TW) ; Hsieh; Ching-Hua; (Hsinchu, TW)
; Liu; Chung-Shi; (Hsinchu City, TW) ; Lin;
Chih-Wei; (Hsinchu County, TW) ; Chiu;
Sheng-Hsiang; (Tainan City, TW) ; Lai; Yao-Tong;
(Yilan County, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Taiwan Semiconductor Manufacturing Co., Ltd. |
Hsinchu |
|
TW |
|
|
Assignee: |
Taiwan Semiconductor Manufacturing
Co., Ltd.
Hsinchu
TW
|
Family ID: |
66327564 |
Appl. No.: |
15/832742 |
Filed: |
December 5, 2017 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
62582333 |
Nov 7, 2017 |
|
|
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 2224/13024
20130101; H01L 2224/1403 20130101; H01L 24/13 20130101; H01L 24/14
20130101; H01L 24/32 20130101; H01L 24/97 20130101; H01L 21/486
20130101; H01L 2224/02379 20130101; H01L 23/5389 20130101; H01L
24/92 20130101; H01L 21/563 20130101; H01L 2224/02319 20130101;
H01L 2224/14051 20130101; H01L 2924/19103 20130101; H01L 23/49827
20130101; H01L 2224/14181 20130101; H01L 2224/05548 20130101; H01L
2924/37001 20130101; H01L 24/73 20130101; H01L 23/50 20130101; H01L
2221/68359 20130101; H01L 2224/32225 20130101; H01L 23/3128
20130101; H01L 24/19 20130101; H01L 2224/02381 20130101; H01L
2224/12105 20130101; H01L 2924/35 20130101; H01L 2924/15311
20130101; H01L 21/6835 20130101; H01L 21/561 20130101; H01L
2224/08265 20130101; H01L 2224/73267 20130101; H01L 2224/02331
20130101; H01L 23/49816 20130101; H01L 2224/214 20130101; H01L
2224/92244 20130101; H01L 24/08 20130101; H01L 2224/95001 20130101;
H01L 21/568 20130101; H01L 24/05 20130101; H01L 24/20 20130101;
H01L 2221/68345 20130101; H01L 2224/97 20130101; H01L 23/3135
20130101; H01L 2224/13008 20130101; H01L 2224/0401 20130101; H01L
2224/04105 20130101; H01L 2224/97 20130101; H01L 2224/83
20130101 |
International
Class: |
H01L 21/56 20060101
H01L021/56; H01L 23/31 20060101 H01L023/31; H01L 23/00 20060101
H01L023/00 |
Claims
1-7. (canceled)
8. A method of manufacturing an integrated fan-out (InFO) package,
comprising: providing a plurality of dies and a plurality of
conductive structures on a carrier, wherein each of the plurality
of dies has an active surface and comprises a plurality of
conductive posts on the active surface, and the active surface is
exposed; encapsulating the plurality of dies and the plurality of
conductive structures with an encapsulant material; removing a
portion of the encapsulant material to form an encapsulant, wherein
the encapsulant exposes at least a portion of sidewalls of the
plurality of conductive structures and at least a portion of
sidewalls of the plurality of conductive posts; forming an
enhancement layer over the encapsulant, wherein the enhancement
layer seals the at least a portion of sidewalls of the plurality of
conductive posts exposed by the encapsulant and the at least a
portion of sidewalls of the plurality of conductive structures
exposed by the encapsulant, and a top surface of the enhancement
layer is substantially coplanar with top surfaces of the plurality
of conductive posts and the plurality of conductive structures; and
forming a redistribution structure over the enhancement layer.
9. The method according to claim 8, wherein the step of removing
the portion of the encapsulant material comprises performing a
plasma etching process to remove the portion of the encapsulant
material such that a plurality of microstructures are formed on the
encapsulant.
10. The method according to claim 9, wherein the step of removing
the portion of the encapsulant material further comprises
performing the plasma etching process to remove the portion of the
encapsulant material such that the active surface and a portion of
sidewalls of the plurality of dies are exposed.
11. The method according to claim 8, wherein the step of forming
the redistribution structure comprises: forming a first dielectric
layer over the enhancement layer, the plurality of conductive
structures, and the plurality of conductive posts, wherein the
first dielectric layer has a plurality of openings exposing the
plurality of conductive structures and the plurality of conductive
posts; forming a plurality of first redistribution conductive
patterns over the first dielectric layer and within the plurality
of openings of the first dielectric layer; forming a second
dielectric layer over the first dielectric layer and the plurality
of first redistribution conductive patterns, wherein the second
dielectric layer has a plurality of openings exposing the plurality
of first redistribution conductive patterns; and forming a
plurality of under-ball metallurgy (UBM) patterns over the second
dielectric layer, wherein the plurality of UBM patterns are
electrically connected to the plurality of conductive structures
and the plurality of conductive posts.
12. The method according to claim 8, wherein the step of forming
the redistribution structure comprises: forming a plurality of
first redistribution conductive patterns over the plurality of
conductive structures and the plurality of conductive posts;
forming a first dielectric layer over the plurality of first
redistribution conductive patterns, wherein the first dielectric
layer has a plurality of openings exposing the plurality of first
redistribution conductive patterns; forming a plurality of second
redistribution conductive patterns over the first dielectric layer
and within the plurality of openings of the first dielectric layer;
forming a second dielectric layer over the first dielectric layer
and the plurality of second redistribution conductive patterns,
wherein the second dielectric layer has a plurality of openings
exposing the plurality of second redistribution conductive
patterns; and forming a plurality of under-ball metallurgy (UBM)
patterns over the second dielectric layer, wherein the plurality of
UBM patterns are electrically connected to the plurality of
conductive structures and the plurality of conductive posts.
13. The method according to claim 12, wherein a material of the
enhancement layer is the same as a material of the first dielectric
layer.
14. The method according to claim 8, further comprising: forming a
plurality of conductive terminals over the redistribution
structure.
15. A method of manufacturing an integrated fan-out (InFO) package,
comprising: providing a plurality of dies and a plurality of
conductive structures on a carrier, wherein each of the plurality
of dies has an active surface and comprises a plurality of
conductive posts on the active surface, and the active surface is
exposed; encapsulating the plurality of dies and the plurality of
conductive structures with an encapsulant material; removing a
portion of the encapsulant material to form an encapsulant, wherein
the encapsulant covers a portion of sidewalls of the plurality of
conductive structures and a portion of sidewalls of the plurality
of conductive posts; forming an enhancement layer over the
encapsulant, wherein the enhancement layer covers another portion
of sidewalls of the plurality of conductive posts and another
portion of sidewalls of the plurality of conductive structures, and
a ratio of a coverage of the sidewalls of the plurality of
conductive posts by the encapsulant to a coverage of the sidewalls
of the plurality of conductive posts by the enhancement layer
ranges between 50%:50% and 80%:20%. forming a redistribution
structure over the enhancement layer.
16. The method according to claim 15, wherein the step of removing
the portion of the encapsulant material comprises performing a
plasma etching process to remove the portion of the encapsulant
material such that a plurality of microstructures are formed on the
encapsulant.
17. The method according to claim 15, wherein the step of forming
the redistribution structure comprises: forming a first dielectric
layer over the enhancement layer, the plurality of conductive
structures, and the plurality of conductive posts, wherein the
first dielectric layer has a plurality of openings exposing the
plurality of conductive structures and the plurality of conductive
posts; forming a plurality of first redistribution conductive
patterns over the first dielectric layer and within the plurality
of openings of the first dielectric layer; forming a second
dielectric layer over the first dielectric layer and the plurality
of first redistribution conductive patterns, wherein the second
dielectric layer has a plurality of openings exposing the plurality
of first redistribution conductive patterns; and forming a
plurality of under-ball metallurgy (UBM) patterns over the second
dielectric layer, wherein the plurality of UBM patterns are
electrically connected to the plurality of conductive structures
and the plurality of conductive posts.
18. The method according to claim 15, wherein the step of forming
the redistribution structure comprises: forming a plurality of
first redistribution conductive patterns over the plurality of
conductive structures and the plurality of conductive posts;
forming a first dielectric layer over the plurality of first
redistribution conductive patterns, wherein the first dielectric
layer has a plurality of openings exposing the plurality of first
redistribution conductive patterns; forming a plurality of second
redistribution conductive patterns over the first dielectric layer
and within the plurality of openings of the first dielectric layer;
forming a second dielectric layer over the first dielectric layer
and the plurality of second redistribution conductive patterns,
wherein the second dielectric layer has a plurality of openings
exposing the plurality of second redistribution conductive
patterns; and forming a plurality of under-ball metallurgy (UBM)
patterns over the second dielectric layer, wherein the plurality of
UBM patterns are electrically connected to the plurality of
conductive structures and the plurality of conductive posts.
19. The method according to claim 18, wherein a material of the
enhancement layer is the same as a material of the first dielectric
layer.
20. The method according to claim 15, further comprising: forming a
plurality of conductive terminals over the redistribution
structure.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the priority benefit of U.S.
provisional application Ser. No. 62/582,333, filed on Nov. 7, 2017.
The entirety of the above-mentioned patent application is hereby
incorporated by reference herein and made a part of this
specification.
BACKGROUND
[0002] The semiconductor industry has experienced rapid growth due
to continuous improvements in the integration density of various
electronic components (i.e., transistors, diodes, resistors,
capacitors, etc.). For the most part, this improvement in
integration density has come from repeated reductions in minimum
feature size, which allows more of the smaller components to be
integrated into a given area. These smaller electronic components
also require smaller packages that utilize less area than previous
packages. Currently, integrated fan-out packages are becoming
increasingly popular for their compactness. The integrated fan-out
packages typically include a redistribution circuit structure
laying over the molded integrated circuit devices such that the
integrated circuit devices may be accessed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] Aspects of the present disclosure are best understood from
the following detailed description when read with the accompanying
figures. It is noted that, in accordance with the standard practice
in the industry, various features are not drawn to scale. In fact,
the dimensions of the various features may be arbitrarily increased
or reduced for clarity of discussion.
[0004] FIG. 1A to FIG. 1L are schematic cross-sectional views
illustrating a manufacturing process of an integrated fan-out
(InFO) package in accordance with some embodiments of the
disclosure.
[0005] FIG. 2A is a schematic cross-sectional view illustrating an
intermediate step of a manufacturing process of an InFO package in
accordance with some alternative embodiments of the disclosure.
[0006] FIG. 2B is a schematic cross-sectional view illustrating an
InFO package in accordance with some alternative embodiments of the
disclosure.
[0007] FIG. 3A to FIG. 3D are schematic cross-sectional views
illustrating intermediate steps of a manufacturing process of an
InFO package in accordance with some alternative embodiments of the
disclosure.
[0008] FIG. 3E is a schematic cross-sectional view illustrating an
InFO package in accordance with some alternative embodiments of the
disclosure.
[0009] FIG. 4 is a schematic cross-sectional view illustrating an
InFO package in accordance with some alternative embodiments of the
disclosure.
[0010] FIG. 5 is a schematic cross-sectional view illustrating an
InFO package in accordance with some alternative embodiments of the
disclosure.
DETAILED DESCRIPTION
[0011] The following disclosure provides many different
embodiments, or examples, for implementing different features of
the provided subject matter. Specific examples of components and
arrangements are described below to simplify the present
disclosure. These are, of course, merely examples and are not
intended to be limiting. For example, the formation of a first
feature over or on a second feature in the description that follows
may include embodiments in which the first and second features are
formed in direct contact, and may also include embodiments in which
additional features may be formed between the first and second
features, such that the first and second features may not be in
direct contact. In addition, the present disclosure may repeat
reference numerals and/or letters in the various examples. This
repetition is for the purpose of simplicity and clarity and does
not in itself dictate a relationship between the various
embodiments and/or configurations discussed.
[0012] Further, spatially relative terms, such as "beneath,"
"below," "lower," "above," "upper" and the like, may be used herein
for ease of description to describe one element or feature's
relationship to another element(s) or feature(s) as illustrated in
the figures. The spatially relative terms are intended to encompass
different orientations of the device in use or operation in
addition to the orientation depicted in the figures. The apparatus
may be otherwise oriented (rotated 90 degrees or at other
orientations) and the spatially relative descriptors used herein
may likewise be interpreted accordingly.
[0013] Other features and processes may also be included. For
example, testing structures may be included to aid in the
verification testing of the 3D packaging or 3DIC devices. The
testing structures may include, for example, test pads formed in a
redistribution layer or on a substrate that allows the testing of
the 3D packaging or 3DIC, the use of probes and/or probe cards, and
the like. The verification testing may be performed on intermediate
structures as well as the final structure. Additionally, the
structures and methods disclosed herein may be used in conjunction
with testing methodologies that incorporate intermediate
verification of known good dies to increase the yield and decrease
costs.
[0014] FIG. 1A to FIG. 1L are schematic cross-sectional views
illustrating a manufacturing process of an integrated fan-out
(InFO) package 10 in accordance with some embodiments of the
disclosure. Referring to FIG. 1A, a carrier 100 is provided. A
de-bonding layer 102 and a dielectric layer 104 are stacked over
the carrier 100 in sequential order. In some embodiments, the
de-bonding layer 102 is formed on the upper surface of the carrier
100 and the de-bonding layer 102 is between the carrier 100 and the
dielectric layer 104. The carrier 100 is, for example, a glass
substrate. However, the disclosure is not limited thereto. The
carrier 100 may be made of any suitable material as long as such
material is able to withstand the subsequent processes. In some
embodiments, the de-bonding layer 102 is a light-to-heat-conversion
(LTHC) release layer formed on the carrier 100. In some
embodiments, the dielectric layer 104 may be formed of polymeric
materials. Examples of the polymeric material include polyimide,
benzocyclobutene (BCB), polybenzoxazole (PBO), or the like. In some
alternative embodiments, the dielectric layer 104 may include
non-organic dielectric materials such as silicon oxide, silicon
nitride, silicon carbide, silicon oxynitride, or the like. However,
the materials of the de-bonding layer 102 and the dielectric layer
104 are merely for illustration and the disclosure is not limited
thereto.
[0015] A plurality of pre-fabricated conductive structures 300 and
a plurality of pre-fabricated dies 200 are provided over the
dielectric layer 104. For example, the dies 200 are mounted onto
the dielectric layer 104 having the conductive structures 300
formed thereon. A die attach film (DAF) (not illustrated) is locate
between the dies 200 and the dielectric layer 104 for adhering the
dies 200 onto the dielectric layer 104. In some embodiments, the
dies 200 are arranged in an array and are surrounded by the
conductive structures 300.
[0016] In some embodiments, each die 200 includes a semiconductor
substrate 202, a plurality of conductive pads 204, and a plurality
of conductive posts 206. Each of the dies 200 has an active surface
200a opposite to the surface attaching to the dielectric layer 104.
For example, as illustrated in FIG. 1A, the active surface 200a of
the die 200 face upward. In some embodiments, the semiconductor
substrate 202 may be made of silicon or germanium. However, the
disclosure is not limited thereto. The semiconductor substrate 202
may also include other suitable semiconductor materials, such as
elements in Group III, Group IV, and/or Group V in the periodic
table. The conductive pads 204 are distributed on the active
surface 200a of the die 200. In some embodiments, the conductive
pads 204 are embedded in the semiconductor substrate 202 as
illustrated in FIG. 1A. Nevertheless, it should be understood that
the configuration depicted in FIG. 1A merely serves as an exemplary
illustration, and the disclosure is not limited thereto. In some
alternative embodiments, the conductive pads 204 may protrude from
the active surface 200a of the die 200. The conductive posts 206
are disposed on the active surface 200a of the die 200. For
example, the conductive posts 206 are disposed on the conductive
pads 204 such that the conductive posts 206 are electrically
connected to the conductive pads 204. The conductive posts 206 may
be copper posts or other suitable metallic posts. Referring to FIG.
1A, the active surface 200a of the die 200 is exposed to
atmospheric environment. In other words, the active surface 200a of
the die 200 is not covered by a dielectric layer. As illustrated in
FIG. 1A, top surfaces of the dies 200 (top surfaces of the
conductive posts 206) are substantially coplanar with top surfaces
of the conductive structures 300. However, the disclosure is not
limited thereto. In some alternative embodiments, the top surfaces
of the dies 200 may be lower than the top surfaces of the
conductive structures 300.
[0017] In some embodiments, the conductive structures 300 may be
conductive pillars. For example, the conductive structures 300 may
be conductive pillars made of copper, copper alloys, or other
metallic materials. In some embodiments, the conductive structures
300 may be referred to as through interlayer vias (TIVs). For
example, the conductive structures 300 are through integrated
fan-out (InFO) vias in some embodiments. It should be noted that
although FIG. 1A depicted eight conductive structures 300, the
number of conductive structures 300 is not limited thereto. In some
alternative embodiments, the number of the conductive structures
300 may be fewer or more based on circuit design.
[0018] Referring to FIG. 1B, an encapsulant material 400 is formed
on the dielectric layer 104 to encapsulate the conductive
structures 300 and the dies 200. In some embodiments, the
encapsulant material 400 is a molding compound formed by a molding
process. For example, the encapsulant material 400 may include
epoxy or other suitable materials. In some embodiments, the
encapsulant material 400 includes fillers to enhance the mechanical
strength thereof. As illustrated in FIG. 1B, the conductive
structures 300 and the conductive posts 206 of the dies 200 are not
revealed and are well protected by the encapsulant material
400.
[0019] Referring to FIG. 1C, a portion of the encapsulant material
400 is removed to form an encapsulant 400'. The portion of the
encapsulant material 400 may be removed by an anisotropic etching
process such that the conductive structures 300 and the conductive
posts 206 of the dies 200 are partially exposed. In some
embodiments, the portion of the encapsulant material 400 may be
removed through a plasma etching process such that a portion of
sidewalls of the conductive structures 300 and a portion of
sidewalls of the conductive posts 206 are exposed. For example, as
illustrated in FIG. 1C, a first portion of sidewalls 300a of the
conductive structures 300 is covered by the encapsulant 400' while
a second portion of sidewalls 300b of the conductive structures 300
is exposed by the encapsulant 400'. Similarly, a first portion of
sidewalls 206a of the conductive posts 206 is covered by the
encapsulant 400' while a second portion of sidewalls 206b of the
conductive posts 206 is exposed by the encapsulant 400'. As
illustrated in FIG. 1C, the top surface 400a' of the encapsulant
400' is lower than top surfaces 300c of the conductive structures
300 and top surfaces 206c of the conductive posts 206 and higher
than active surfaces 200a of the dies 200. In some embodiments,
during the plasma etching process, the etchant includes Argon (Ar)
gas, nitrogen (N.sub.2) gas, oxygen (O.sub.2) gas, or a combination
thereof. In some embodiments, the plasma etching process results in
a plurality of microstructures 402 on the top surface 400a' of the
encapsulant 400'. In other words, the top surface 400a' of the
encapsulant 400' is a rough surface. In some embodiments, the
microstructures 402 are randomly dispersed on the top surface 400a'
of the encapsulant 400'.
[0020] Referring to FIG. 1D, an enhancement material layer 500 is
formed over the encapsulant 400' to cover the exposed portion of
the conductive structures 300 and the exposed portion of the
conductive posts 206. A material of the enhancement material layer
500 is different from the material of the encapsulant 400'. In some
embodiments, the material of the enhancement material layer 500
includes dielectric material such as polyimide, epoxy resin,
acrylic resin, phenol resin, BCB, PBO, or any other suitable
polymer-based dielectric materials. Unlike the encapsulant 400',
the enhancement material layer 500 is free of fillers. The
enhancement material layer 500 is formed to completely seal the
conductive structures 300 and the conductive posts 206. For
example, as illustrated in FIG. 1D, top surface 500a of the
enhancement material layer 500 is higher than top surfaces 300c of
the conductive structures 300 and top surfaces 206c of the
conductive posts 206.
[0021] Referring to FIG. 1E, a portion of the enhancement material
layer 500 is removed to form an enhancement layer 500'. The
enhancement layer 500' exposes top surfaces 300c of the conductive
structures 300 and top surfaces 206c of the conductive posts 206.
In some embodiments, the portion of the enhancement material layer
500 may be removed through mechanical grinding, chemical mechanical
polishing (CMP), fly cutting, or other suitable mechanisms. For
example, the top surface 500a of the enhancement material layer 500
may be grinded until the top surfaces 300c of the conductive
structures 300 and the top surfaces 206c of the conductive posts
206 are revealed. However, the disclosure is not limited thereto.
In some alternative embodiments, after the top surfaces 300c of the
conductive structures 300 and the top surfaces 206c of the
conductive posts 206 are revealed, the enhancement material layer
500', the conductive structures 300, and the conductive posts 206
may be further grinded to reduce the overall thickness of the
package. In some embodiments, top surface 500a' of the enhancement
layer 500' is substantially coplanar with top surfaces 300c of the
conductive structures 300 and top surfaces 206c of the conductive
posts 206.
[0022] As illustrated in FIG. 1E, the enhancement layer 500' covers
the second portion of sidewalls 300b of the conductive structures
300 and the second portion of sidewalls 206b of the conductive
posts 206. In some embodiments, a ratio of a coverage of the first
portion of sidewalls 206a of the conductive posts 206 by the
encapsulant 400' to a coverage of second portion of sidewalls 206b
of the conductive posts 206 by the enhancement layer 500' ranges
between 50%:50% and 80%:20%. For example, a height of the first
portion of sidewalls 206a of the conductive posts 206 covered by
the encapsulant 400' ranges between 5 .mu.m and 20 .mu.m, and a
height of the second portion of sidewalls 206b of the conductive
posts 206 by the enhancement layer 500' ranges between 2 .mu.m and
10 .mu.m. In some embodiments, the conductive posts 206 are uniform
conductive posts with straight sidewalls. Therefore, the term
"coverage" herein refers to an area of the lateral surface of the
conductive posts 206 that is being covered. Since the enhancement
layer 500' is formed over the encapsulant 400', the top surface
400a' of the encapsulant 400' may be referred to as an interface
between the encapsulant 400' and the enhancement layer 500'.
[0023] In general, when a material having fillers is grinded, a
plurality of pits is formed on the grinded surface due to removal
of the fillers located on the grinded surface. However, as
mentioned above, the enhancement material layer 500 is free of
fillers. Therefore, upon processing the enhancement material layer
500, the resulting enhancement layer 500' has a smooth top surface
500a' with substantially no pit. In other words, a roughness of an
interface (top surface 400a') between the encapsulant 400' and the
enhancement layer 500' is larger than a roughness of the top
surface 500a' of the enhancement layer 500. For example, the
interface between the encapsulant 400' and the enhancement layer
500' has a roughness (Ra) ranges between 1 .mu.m and 5 .mu.m. On
the other hand, the top surface 500a' of the enhancement layer 500'
has a roughness ranges between 0.5 .mu.m and 2 .mu.m. The roughness
of the interface between the encapsulant 400' and the enhancement
layer 500' is able to enhance the adhesion between the encapsulant
400' and the enhancement layer 500', thereby improving the
mechanical strength of the package.
[0024] Referring to FIG. 1F to FIG. 1H, a redistribution structure
600 electrically connected to the conductive structures 300 and the
conductive posts 206 is formed over the enhancement layer 500'. The
steps for forming the redistribution structure 600 will be
discussed in detail below.
[0025] Referring to FIG. 1F, a first dielectric layer 602a is
formed over the enhancement layer 500', the conductive structures
300, and the conductive posts 206. The first dielectric layer 602a
has a plurality of openings OP exposing the conductive structures
300 and the conductive posts 206 for future electrical connection.
For example, the openings OP of the first dielectric layer 602a may
be formed corresponding to the top surfaces 300c of the conductive
structures 300 and the top surfaces 206c of the conductive posts
206. In some embodiments, the first dielectric layer 602a may be
formed of polyimide, epoxy resin, acrylic resin, phenol resin, BCB,
PBO, or any other suitable polymer-based dielectric materials.
[0026] Referring to FIG. 1G, a plurality of first redistribution
conductive patterns 604a is formed over the first dielectric layer
602a and within the openings OP of the first dielectric layer 602a.
The first redistribution conductive patterns 604a extends into the
openings OP of the first dielectric layer 602a to be in direct
contact with the conductive structures 300 and the conductive posts
206. In some embodiments, the first redistribution conductive
patterns 604a may be formed by the following steps. First, a seed
layer (not shown) is deposited onto the first dielectric layer 602a
and within the openings OP of the first dielectric layer 602a. The
seed layer may be formed by physical vapor deposition or other
applicable methods. Subsequently, a mask layer (not shown) having a
plurality of openings corresponding to the openings OP of the first
dielectric layer 602a is formed over the seed layer. In other
words, the openings of the mask layer exposes the seed layer
located in the openings OP of the first dielectric layer 602a.
Thereafter, a conductive material layer (not shown) is filled into
the openings of the mask such that the conductive material layer is
formed over the seed layer located in the openings of the mask. The
conductive material layer may be formed by a plating process. The
plating process is, for example, electro-plating,
electroless-plating, immersion plating, or the like. Next, the mask
and a portion of the seed layer not covered by the conductive
material layer are removed. The conductive material layer and the
remaining seed layer constitute the first redistribution conductive
patterns 604a. In some embodiments, a material of the first
redistribution conductive patterns 604a includes aluminum,
titanium, copper, nickel, tungsten, and/or alloys thereof.
[0027] Referring to FIG. 1H, the steps similar to the steps
illustrated in FIG. 1F to FIG. 1G may be repeated to form a second
dielectric layer 602b, a third dielectric layer 602c, a fourth
dielectric layer 602d, a plurality of second redistribution
conductive patterns 604b, a plurality of third redistribution
conductive patterns 604c, a plurality of under-ball metallurgy
(UBM) patterns 606a, and a plurality of connection pads 606b. For
example, the second dielectric layer 602b may be formed over the
first dielectric layer 602a and the first redistribution conductive
patterns 604a. Similar to the first dielectric layer 602a, the
second dielectric layer 602b also has a plurality of openings
exposing the first redistribution conductive patterns 604a.
Subsequently, the second redistribution conductive patterns 604b is
formed over the second dielectric layer 602b and extends into the
openings of the second dielectric layer 602b to be in direct
contact with the first redistribution conductive patterns 604a. The
third dielectric layer 602c, the fourth dielectric layer 602d, the
third redistribution conductive patterns 604c, the UBM patterns
606a, and the connection pads 606b may be formed by similar
manners, so the detailed descriptions thereof are omitted
herein.
[0028] As illustrated in FIG. 1H, the redistribution structure 600
includes a plurality of dielectric layers (the first dielectric
layer 602a, the second dielectric layer 602b, the third dielectric
layer 602c, and the fourth dielectric layer 602d) and a plurality
of redistribution conductive patterns (the first redistribution
conductive patterns 604a, the second redistribution conductive
patterns 604b, the third redistribution conductive patterns 604c,
the UBM patterns 606a, and the connection pads 606b) stacked
alternately. The redistribution conductive patterns (the first
redistribution conductive patterns 604a, the second redistribution
conductive patterns 604b, the third redistribution conductive
patterns 604c, the UBM patterns 606a, and the connection pads 606b)
are electrically connected to the conductive structures 300 and the
conductive posts 206 of the dies 200. In some embodiments, the top
surfaces of the conductive structures 300 and the top surfaces of
the conductive posts 206 are in contact with the bottommost
redistribution conductive patterns (the first redistribution
conductive patterns 604a). The top surfaces of the conductive
structures 300 and the top surfaces of the conductive posts 206 may
be partially of fully covered by the first redistribution
conductive patterns 604a. Furthermore, the topmost redistribution
conductive patterns may be referred to as the UBM patterns 606a and
the connection pads 606b. It should be noted that the number of the
dielectric layer and the number of the redistribution conductive
patterns of the redistribution structure 600 depicted in FIG. 1H
merely serve as exemplary illustrations, and the disclosure is not
limited thereto. In some alternative embodiments, fewer or more
dielectric layers and/or redistribution conductive patterns may be
adapted based on circuit design.
[0029] As mentioned above, the top surface 500a' of the enhancement
layer 500' is a smooth surface. In other words, the redistribution
structure 600 may be formed on a flat surface. Since the
redistribution structure 600 is formed on a flat surface, the
problem of breakage of the redistribution conductive patterns in
the redistribution structure 600 may be sufficiently alleviated. As
such, finer pitch of the metallic traces in the redistribution
structure 600 may be realized and the quality of the metallic
traces in the redistribution structure 600 may be ensured.
[0030] Referring to FIG. 11, after the redistribution structure 600
is formed, a plurality of conductive terminals 700a is placed on
the UBM patterns 606a and a plurality of passive components 700b is
mounted on the connection pads 606b. In some embodiments, the
conductive terminals 700a may be placed on the UBM patterns 606a
through a ball placement process or other suitable processes. In
some embodiments, the passive components 700b may be mounted on the
connection pads 606b through a soldering process, a reflowing
process, or other suitable processes.
[0031] Referring to FIG. 1J, the dielectric layer 104 formed on the
bottom surface of the encapsulant 400' is de-bonded from the
de-bonding layer 102 such that the dielectric layer 104 is
separated from the carrier 100. That is, the carrier 100 is
removed. In some embodiments, the de-bonding layer 102 (e.g., the
LTHC release layer) may be irradiated by an UV laser such that the
dielectric layer 104 is peeled off from the carrier 100. As
illustrated in FIG. 1J, the dielectric layer 104 is then patterned
such that a plurality of contact openings O is formed to partially
expose the conductive structures 300. In some embodiments, the
contact openings O of the dielectric layer 104 are formed by a
laser drilling process, a mechanical drilling process, or other
suitable processes.
[0032] Referring to FIG. 1K and FIG. 1L, a plurality of conductive
terminals 800 is placed in the contact openings O. The conductive
terminals 800 are electrically connected to the conductive
structures 300. Herein, formation of an integrated fan-out (InFO)
package array is substantially completed. As illustrated in FIG. 1K
and FIG. 1L, after the conductive terminals 800 are formed, the
InFO package array is diced to form a plurality of InFO packages 10
having dual-side terminal design. In some embodiment, the dicing
process or singulation process typically involves dicing with a
rotating blade or a laser beam. In other words, the dicing or
singulation process is, for example, a laser cutting process, a
mechanical cutting process, or other suitable processes.
[0033] FIG. 2A is a schematic cross-sectional view illustrating an
intermediate step of a manufacturing process of an InFO package 20
in accordance with some alternative embodiments of the disclosure.
FIG. 2B is a schematic cross-sectional view illustrating an InFO
package 20 in accordance with some alternative embodiments of the
disclosure. Referring to FIG. 2B, the manufacturing steps of InFO
package 20 are similar to the steps illustrated in FIG. 1A to FIG.
1L except the step illustrated in FIG. 1E is replaced by the step
illustrated in FIG. 2A. As illustrated in FIG. 2A, the portion of
the encapsulant material 400 may be removed such that the top
surface 400a' of the encapsulant 400' is lower than the active
surfaces 200a of the dies 200. In other words, after the plasma
etching process, the conductive posts 206, the active surfaces
200a, and a portion of sidewalls SW of the dies 200 are exposed by
the encapsulant 400'. For example, as illustrated in FIG. 2B, the
encapsulant 400' covers a portion of the sidewalls SW of the die
200 and a portion of sidewalls of the conductive structures 300. On
the other hand, the enhancement layer 500' covers another portion
of the sidewalls SW of the die 200, another portion of sidewalls of
the conductive structures 300, the active surface 200a of the die
200, and sidewalls of the conductive posts 206. Since the level
height of the top surface 400a' of the encapsulant 400' is not
particularly limited, a high plasma etching precision is not
required. As such, the process complexity may be reduced, thereby
achieving an easier manufacturing process.
[0034] FIG. 3A to FIG. 3D are schematic cross-sectional views
illustrating intermediate steps of a manufacturing process of an
InFO package 30 in accordance with some alternative embodiments of
the disclosure. FIG. 3E is a schematic cross-sectional view
illustrating an InFO package 30 in accordance with some alternative
embodiments of the disclosure. Referring to FIG. 3E, the
manufacturing steps of InFO package 30 are similar to the steps
illustrated in FIG. 1A to FIG. 1L except the steps illustrated in
FIG. 1F to FIG. 1H are replaced by the steps illustrated in FIG. 3A
to FIG. 3D. Referring to FIG. 3A and FIG. 3B, when the material of
the enhancement layer 500' is the same as the material of the
dielectric layer (for example, the first dielectric layer 602a in
FIG. 3B) in the redistribution structure 600, the first
redistribution conductive patterns 604a may be formed prior to the
formation of the first dielectric layer 602a. As illustrated in
FIG. 3A, the first redistribution conductive patterns 604a are
formed over the enhancement layer 500', the conductive structures
300, and the conductive posts 206. The formation method and the
material of the first redistribution conductive patterns 604a may
be referred to the descriptions related to FIG. 1G presented above,
so the detailed description thereof is omitted herein.
[0035] Referring to FIG. 3B, the first dielectric layer 602a is
formed over the first redistribution conductive patterns 604a. The
first dielectric layer 602a has a plurality of openings OP exposing
the first redistribution conductive patterns 604a. The formation
method and the material of the first dielectric layer 602a may be
referred to the descriptions related to FIG. 1F presented above, so
the detailed description thereof is omitted herein.
[0036] Referring to FIG. 3C, a plurality of second redistribution
conductive patterns 604b is formed over the first dielectric layer
602a and extends into the openings OP of the first dielectric layer
602a to be in direct contact with the first redistribution
conductive patterns 604a. The second redistribution conductive
patterns 604b may be formed by similar manner as that of the first
redistribution conductive patterns 604b, so the detailed
description thereof is omitted herein.
[0037] Referring to FIG. 3D, the steps similar to the steps
illustrated in FIG. 3B to FIG. 3C may be repeated to form a second
dielectric layer 602b, a third dielectric layer 602c, a fourth
dielectric layer 602d, a plurality of third redistribution
conductive patterns 604c, a plurality of fourth redistribution
conductive patterns 604d, a plurality of UBM patterns 606a, and a
plurality of connection pads 606b. For example, the second
dielectric layer 602b may be formed over the first dielectric layer
602a and the second redistribution conductive patterns 604b.
Similar to the first dielectric layer 602a, the second dielectric
layer 602b also has a plurality of openings exposing the second
redistribution conductive patterns 604b. Subsequently, the third
redistribution conductive patterns 604c is formed over the second
dielectric layer 602b and extends into the openings of the second
dielectric layer 602b to be in direct contact with the second
redistribution conductive patterns 604b. The third dielectric layer
602c, the fourth dielectric layer 602d, the fourth redistribution
conductive patterns 604d, the UBM patterns 606a, and the connection
pads 606b may be formed by the similar manner, so the detailed
descriptions thereof are omitted herein. It should be noted that
the number of the dielectric layer and the number of the
redistribution conductive patterns of the redistribution structure
600 depicted in FIG. 3D merely serve as an exemplary illustrations,
and the disclosure is not limited thereto. In some alternative
embodiments, fewer or more dielectric layers and/or redistribution
conductive patterns may be adapted based on circuit design.
[0038] FIG. 4 is a schematic cross-sectional view illustrating an
InFO package 40 in accordance with some alternative embodiments of
the disclosure. Referring to FIG. 4, the manufacturing steps of
InFO package 40 are similar to the steps illustrated in FIG. 1A to
FIG. 1L except the step illustrated in FIG. 1E is replaced by the
step illustrated in FIG. 2A and the steps illustrated in FIG. 1F to
FIG. 1H are replaced by the steps illustrated in FIG. 3A to FIG.
3D. Therefore, the detailed descriptions of the manufacturing steps
of the InFO package 40 are omitted herein. As illustrated in FIG.
4, the top surface 400a' of the encapsulant 400' is lower than the
active surface 200a of the die 200.
[0039] FIG. 5 is a schematic cross-sectional view illustrating an
InFO package 50 in accordance with some alternative embodiments of
the disclosure. Referring to FIG. 5, the InFO package 50 is similar
to the InFO package 10 illustrated in FIG. 1L except InFO package
50 further includes an additional die 900. Similar to the die 200,
the additional die 900 also includes a semiconductor substrate 902,
a plurality of conductive pads 904, and a plurality of conductive
posts 906. The detailed descriptions of the semiconductor substrate
902, the conductive pads 904, and the conductive posts 906 may be
respectively referred to the descriptions related to the
semiconductor substrate 202, the conductive pads 204, and the
conductive posts 206, so the detailed descriptions thereof are
omitted herein. In some embodiments, a thickness t1 of the die 200
may be different from a thickness t2 of the additional die 900. For
example, as illustrated in FIG. 5, the thickness t1 of the die 200
is larger than the thickness t2 of the additional die 900. In some
embodiments, the die 200 and the additional die 900 may be
different dies performing different logic functions. However, it
construes no limitation in the disclosure. In some alternative
embodiments, the thickness t1 of the die 200 may be smaller than or
equal to the thickness t2 of the additional die 900. In addition,
in some alternative embodiments, the die 200 and the additional die
900 may be identical dies performing the same logic function.
[0040] It should be noted that although not illustrated, the InFO
package 20 in FIG. 2B, the InFO package 30 in FIG. 3E, and the InFo
package 40 in FIG. 4 may also include an additional die similar to
the additional die 900 in FIG. 5.
[0041] In accordance with some embodiments of the disclosure, and
integrated fan-out (InFO) package includes at least one die, a
plurality of conductive structures, an encapsulant, an enhancement
layer, and a redistribution structure. The at least one die has an
active surface and includes a plurality of conductive posts on the
active surface. The conductive structures surround the at least one
die. The encapsulant partially encapsulates the at least one die.
The enhancement layer is over the encapsulant. A top surface of the
enhancement layer is substantially coplanar with top surfaces of
the conductive posts and the conductive structures. A material of
the enhancement layer is different from a material of the
encapsulant. A roughness (Ra) of an interface between the
encapsulant and the enhancement layer is larger than a roughness of
the top surface of the enhancement layer. A redistribution
structure is over the enhancement layer and is electrically
connected to the conductive structures and the at least one
die.
[0042] In accordance with some alternative embodiments of the
disclosure, a method of manufacturing an integrated fan-out (InFO)
package includes at least the following steps. A plurality of dies
and a plurality of conductive structures are provided on a carrier.
Each of the dies has an active surface and includes a plurality of
conductive posts on the active surface. The active surface is
exposed. The dies and the conductive structures are encapsulated
with an encapsulant material. A portion of the encapsulant material
is removed to form an encapsulant. The encapsulant exposes at least
a portion of sidewalls of the conductive structures and at least a
portion of sidewalls of the conductive posts. An enhancement layer
is formed over the encapsulant. The enhancement layer seals the at
least a portion of sidewalls of the conductive posts exposed by the
encapsulant and the at least a portion of sidewalls of the
conductive structures exposed by the encapsulant. A top surface of
the enhancement layer is substantially coplanar with top surfaces
of the conductive posts and the conductive structures. A
redistribution structure is formed over the enhancement layer.
[0043] In accordance with some alternative embodiments of the
disclosure, a method of manufacturing an integrated fan-out (InFO)
package includes at least the following steps. A plurality of dies
and a plurality of conductive structures are provided on a carrier.
Each of the dies has an active surface and includes a plurality of
conductive posts on the active surface. The active surface is
exposed. The dies and the conductive structures are encapsulated
with an encapsulant material. A portion of the encapsulant material
is removed to form an encapsulant. The encapsulant covers a portion
of sidewalls of the conductive structures and a portion of
sidewalls of the conductive posts. An enhancement layer is formed
over the encapsulant. The enhancement layer covers another portion
of sidewalls of the conductive posts and another portion of
sidewalls of the conductive structures. A ratio of a coverage of
the sidewalls of the conductive posts by the encapsulant to a
coverage of the sidewalls of the conductive posts by the
enhancement layer ranges between 50%:50% and 80%:20%. A
redistribution structure is formed over the enhancement layer.
[0044] The foregoing outlines features of several embodiments so
that those skilled in the art may better understand the aspects of
the present disclosure. Those skilled in the art should appreciate
that they may readily use the present disclosure as a basis for
designing or modifying other processes and structures for carrying
out the same purposes and/or achieving the same advantages of the
embodiments introduced herein. Those skilled in the art should also
realize that such equivalent constructions do not depart from the
spirit and scope of the present disclosure, and that they may make
various changes, substitutions, and alterations herein without
departing from the spirit and scope of the present disclosure.
* * * * *